Datasheet si4532ady Datasheet

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Page 1

N- and P-Channel 30-V (D-S) MOSFET

Si4532ADY

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) R

N-Channel 30

P-Channel - 30

0.053 at V

0.075 at V

0.080 at V

0.135 at V

SO-8

Top View

Ordering Information: Si4532ADY-T1-E3 (Lead (Pb-free)

Si4532ADY-T1-GE3 (Lead (Pb-free and Halogen-free)

(Ω)I

DS(on)

= 10 V

= 4.5 V

= - 10 V

= - 4.5 V

(A)

4.9

4.1

- 3.9

- 3.0

FEATURES

• Halogen-free According to IEC 61249-2-21 Available

• TrenchFET

N-Channel MOSFET

Power MOSFETs

P-Channel MOSFET

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

N-Channel P-Channel

Parameter Symbol

Drain-Source Voltage

Gate-Source Voltage

TA = 25 °C

Continuous Drain Current (T

= 150 °C)

= 70 °C

Pulsed Drain Current

Continuous Source Current (Diode Conduction)

Maximum Power Dissipation

TA = 25 °C

= 70 °C

Operating Junction and Storage Temperature Range

, T

stg

10 s Steady State 10 s Steady State

30 - 30

± 20 ± 20

4.9 3.7 - 3.9 - 3.0

3.9 2.9 - 3.1 - 2.4

1.7 0.94 - 1.7 - 1.0

21.132 1.2

1.3 0.73 1.3 0.76

- 55 to 150 °C

THERMAL RESISTANCE RATINGS

N-Channel P-Channel

Parameter Symbol

Maximum Junction-to-Ambient

Maximum Junction-to-Foot (Drain) Steady State

t ≤ 10 s

Steady State 90 110 87 105

thJA

thJF

Notes: a. Surface Mounted on 1" x 1" FR4 board.

Document Number: 71133 S09-0393-Rev. C, 09-Mar-09

Typ. Max. Typ. Max.

55 62.5 54 62.5

40 50 34 45

Unit

°C/W

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Page 2

Si4532ADY

Vishay Siliconix

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

Gate Threshold Voltage

Gate-Body Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

Drain-Source On-State Resistance

Forward Transconductance

Diode Forward Voltage

Dynamic

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

Tur n -O n De l ay T i me

Rise Time

Turn-Off Delay Time

Fall Time

Source-Drain Reverse Recovery Time

GS(th)

GSS

DSS

D(on)

DS(on)

d(on)

d(off)

Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing.

= VGS, ID = 250 µA

= VGS, ID = - 250 µA

VDS = 0 V, VGS = ± 20 V

= 0 V, VGS = ± 20 V

= 30 V, V

= - 30 V, V

= 30 V, V

= - 30 V, V

≥ 5 V, V

≤ - 5 V, V

= 10 V, ID = 4.9 A

= - 10 V, ID = - 3.9 A

= 4.5 V, ID = 4.1 A

= - 4.5 V, ID = - 3.0 A

= 0 V, TJ = 55 °C

VDS = 15 V, ID = 4.9 A

= - 15 V, ID = - 2.5 A

IS = 1.7 A, V

= - 1.7 A, V

N-Channel

= 10 V, V

= 10 V, ID = 4.9 A

P-Channel

= - 4 V, V

= - 10 V, ID = - 3.9 A

N-Channel

= 10 V, RL = 10 Ω

≅ 1 A, V

= 10 V, Rg = 6 Ω

GEN

P-Channel

= - 10 V, RL = 10 Ω

≅ - 1 A, V

= - 10 V, Rg = 6 Ω

GEN

IF = 1.7 A, dI/dt = 100 A/µs

= - 1.7 A, dI/dt = 100 A/µs

= 0 V

= 10 V

= - 10 V

= 0 V

N-Ch 1.0

P-Ch - 1.0

N-Ch ± 100

P-Ch ± 100

N-Ch 1

P-Ch - 1

N-Ch 5

P-Ch - 5

N-Ch 20

P-Ch - 20

N-Ch 0.044 0.053

P-Ch 0.062 0.080

N-Ch 0.062 0.075

P-Ch 0.105 0.135

N-Ch 11

P-Ch 5

N-Ch 0.80 1.2

P-Ch - 0.82 - 1.2

N-Ch 8 16

P-Ch 10 20

N-Ch 1.4

P-Ch 2

N-Ch 1.2

P-Ch 1.9

N-Ch 12 20

P-Ch 8 15

N-Ch 10 20

P-Ch 9 18

N-Ch 23 45

P-Ch 21 40

N-Ch 8 15

P-Ch 10 20

N-Ch 25 40

P-Ch 27 40

µA

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the de vice. These are stress rating s only, and functiona l operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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Document Number: 71133

S09-0393-Rev. C, 09-Mar-09

Page 3

N-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Si4532ADY

Vishay Siliconix

VGS = 10 V thru 5 V

- Drain Current (A)I

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

- Drain-to-Source Voltage (V)

Output Characteristics

0.15

0.12

0.09

VGS = 4.5 V

0.06

- On-Resistance (Ω)R

DS(on)

0.03

0.00 048121620

4 V

3 V

VGS = 10 V

- Drain Current (A)I

012345

TC = 125 °C

25 °C

- Gate-to-Source Voltage (V)

- 55 °C

Transfer Characteristics

600

500

400

300

200

C - Capacitance (pF)

100

0 6 12 18 24 30

oss

rss

iss

On-Resistance vs. Drain Current

VDS = 10 V

= 4.9 A

- Gate-to-Source Voltage (V)

02468

Document Number: 71133 S09-0393-Rev. C, 09-Mar-09

ID - Drain Current (A)

Qg - Total Gate Charge (nC)

Gate Charge

VDS - Drain-to-Source Voltage (V)

Capacitance

1.8

VGS = 10 V

= 4.9 A

1.6

1.4

1.2

- On-Resistance (Normalized)

1.0

DS(on)

0.8

0.6

- 50 - 25 0 25 50 75 100 125 150

- Junction Temperature (°C)

On-Resistance vs. Junction Temperature

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Page 4

Si4532ADY

Vishay Siliconix

N-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

- Source Current (A)I

Variance (V)V

GS(th)

TJ = 150 °C

TJ = 25 °C

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

VSD - Source-to-Drain Voltage (V)

Source-Drain Diode Forward Voltage

0.4

0.2

0.0

- 0.2

- 0.4

ID = 250 µA

- On-Resistance (Ω)R

DS(on)

Power (W)

0.15

0.12

0.09

ID = 4.9 A

0.06

0.03

0.00 0246810

VGS - Gate-to-Source Voltage (V)

On-Resistance vs. Gate-to-Source Voltage

- 0.6

- 0.8

- 50 - 25 0 25 50 75 100 125 150

Thermal Impedance

Normalized Effective Transient

0.01

0.1

0.05

0.02

-4

TJ - Temperature (°C)

Threshold Voltage

Duty Cycle = 0.5

0.2

0.1

Single Pulse

-3

-1

-2

1 100 6001010

Time (s)

Single Pulse Power

Notes:

thJA

100

= 90 °C/W

(t)

1. Duty Cycle, D =

2. Per Unit Base = R

- TA = PDMZ

3. T

4. Surface Mounted

-3

-2

-1

1 10 60010

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

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Document Number: 71133

S09-0393-Rev. C, 09-Mar-09

Page 5

N-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Duty Cycle = 0.5

0.2

0.1

Thermal Impedance

0.05

Si4532ADY

Vishay Siliconix

0.01

0.02

Single Pulse

-4

-3

-2

Square Wave Pulse Duration (s)

-1

Normalized Effective Transient

Normalized Thermal Transient Impedance, Junction-to-Foot

P-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

VGS = 10 V thru 6 V

5 V

- Drain Current (A)I

2 V

02468

- Drain-to-Source Voltage (V)

4 V

3 V

Output Characteristics

- Drain Current (A)I

01234567

11010

TC = - 55 °C

25 °C

- Gate-to-Source Voltage (V)

Transfer Characteristics

125 °C

0.30

0.24

0.18

VGS = 4.5 V

0.12

- On-Resistance (Ω)R

DS(on)

0.06

0.00 0 3 6 9 12 15

On-Resistance vs. Drain Current

Document Number: 71133 S09-0393-Rev. C, 09-Mar-09

ID - Drain Current (A)

VGS = 10 V

1000

800

600

400

C - Capacitance (pF)

200

rss

0 6 12 18 24 30

iss

oss

VDS - Drain-to-Source Voltage (V)

Capacitance

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Page 6

Si4532ADY

Vishay Siliconix

P-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

- Gate-to-Source Voltage (V)

VDS = 10 V

= 3.9 A

0246810

Qg - Total Gate Charge (nC)

Gate Charge

TJ = 150 °C

- On-ResistanceR

DS(on)

1.8

VGS = 10 V

= 3.9 A

1.6

1.4

1.2

(Normalized)

1.0

0.8

0.6

- 50 - 25 0 25 50 75 100 125 150

- Junction Temperature (°C)

On-Resistance vs. Junction Temperature

0.40

0.32

ID = 3.9 A

0.24

- Source Current (A)I

0 0.3 0.6 0.9 1.2 1.5

VSD - Source-to-Drain Voltage (V)

TJ = 25 °C

Source-Drain Diode Forward Voltage

0.8

0.6

ID = 250 µA

0.4

0.2

Variance (V)V

GS(th)

0.0

- 0.2

- 0.4

- 50 - 25 0 25 50 75 100 125 150

TJ - Temperature (°C)

Threshold Voltage

- On-Resistance (Ω)R

DS(on)

Power (W)

0.16

0.08

0.00 0246810

VGS - Gate-to-Source Voltage (V)

On-Resistance vs. Gate-to-Source Voltage

-2

-1

1 1001010

Time (s)

Single Pulse Power, Junction-to-Ambient

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Document Number: 71133

S09-0393-Rev. C, 09-Mar-09

Page 7

P-CHANNEL TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Duty Cycle = 0.5

Si4532ADY

Vishay Siliconix

0.1

Thermal Impedance

Normalized Effective Transient

0.01

0.1

Thermal Impedance

Normalized Effective Transient

0.2

0.1

0.05

0.02

-4

Duty Cycle = 0.5

0.2

0.1

0.02

-3

Single Pulse

-2

-1

1 10 60010

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

0.05

Notes:

- TA = PDMZ

1. Duty Cycle, D =

2. Per Unit Base = R

3. T

4. Surface Mounted

thJA

t t

thJA

100

= 87 °C/W

(t)

Single Pulse

0.01

-4

-3

-2

-1

11010

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Foot

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71133

Document Number: 71133

www.vishay.com

S09-0393-Rev. C, 09-Mar-09

Page 8

SOIC (NARROW): 8-LEAD

JEDEC Part Number: MS-012

Package Information

Vishay Siliconix

DIM

A 1.35 1.75 0.053 0.069

B 0.35 0.51 0.014 0.020

C 0.19 0.25 0.0075 0.010

D 4.80 5.00 0.189 0.196

E 3.80 4.00 0.150 0.157

e 1.27 BSC 0.050 BSC

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.50 0.93 0.020 0.037

q0°8°0°8°

S 0.44 0.64 0.018 0.026

ECN: C-06527-Rev. I, 11-Sep-06 DWG: 5498

0.25 mm (Gage Plane)

h x 45

MILLIMETERS INCHES

Min Max Min Max

0.10 0.20 0.004 0.008

All Leads

0.101 mm

0.004"

Document Number: 71192 11-Sep-06

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Page 9

VISHAY SILICONIX

TrenchFET® Power MOSFETs

Application Note 808

Mounting LITTLE FOOT®, SO-8 Power MOSFETs

Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use

integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and

0.050

1.27

design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same.

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/ppg?72286), for the

0.027

0.69

0.07

1.98

Figure 2. Dual MOSFET SO-8 Pad Pattern

basis of the pad design for a LITTLE FOOT SO-8 power MOSFET. In converting this recommended minimum pad to the pad set for a power MOSFET, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package.

In the case of the SO-8 package, the thermal connections are very simple. Pins 5, 6, 7, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In a dual package, pins 5 and 6 are one drain, and pins 7 and 8 are the other drain. For a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The

The minimum recommended pad patterns for the single-MOSFET SO-8 with copper spreading (Figure 1) and dual-MOSFET SO-8 with copper spreading (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose.

total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board.

Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder

0.288

7.3

connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the

0.050

1.27

0.027

0.69

0.078

1.98

0.2

5.07

0.196

5.0

Figure 1. Single MOSFET SO-8 Pad

Pattern With Copper Spreading

Document Number: 70740 www.vishay.com Revision: 18-Jun-07 1

drain pins, the solder mask generation occurs automatically.

A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least

0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device.

0.288

7.3

0.2

5.07

With Copper Spreading

0.088

2.25

0.088

2.25

APPLICATION NOTE

Page 10

Application Note 826

Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR SO-8

0.172

(4.369)

0.028

(0.711)

Return to Index

0.022

(0.559)

0.246 (6.248)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.050

(1.270)

0.152

0.047

(3.861)

(1.194)

APPLICATION NOTE

www.vishay.com Document Number: 72606 22 Revision: 21-Jan-08

Page 11

Legal Disclaimer Notice

Vishay

Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.

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Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.

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Document Number: 91000 www.vishay.com Revision: 11-Mar-11 1