Datasheet si4423dy Datasheet

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Page 1

P-Channel 20-V (D-S) MOSFET

Si4423DY

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) R

- 20

DS(on)

0.0075 at V

0.009 at V

0.0115 at V

(Ω)I

(A)

= - 4.5 V - 14

= - 2.5 V - 13

= - 1.8 V - 12

FEATURES

• Halogen-free According to IEC 61249-2-21 Definition

• TrenchFET

Power MOSFET

• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

• Game Station

SO-8

T op V i e w

Ordering Information: Si4423DY-T1-E3 (Lead (Pb)-free)

Si4423DY-T1-GE3 (Lead (Pb)-free and Halogen-free)

- Load Switch

P-Channel MOSFE

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol 10 s Steady State Unit

Drain-Source Voltage

Gate-Source Voltage

Continuous Drain Current (T

= 150 °C)

Pulsed Drain Current

Continuous Source Current (Diode Conduction)

Maximum Power Dissipation

Operating Junction and Storage Temperature Range

TA = 25 °C

= 70 °C

TA = 25 °C

= 70 °C

, T

stg

- 14 - 10

- 11.5 - 8

- 2.7 - 1.36

- 20

± 8

- 50

3.0 1.5

1.9 0.95

- 55 to 150 °C

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambient

t ≤ 10 s

Maximum Junction-to-Foot (Drain) Steady State R

Notes: a. Surface Mounted on 1" x 1" FR4 board.

Document Number: 72085 S09-0705-Rev. D, 27-Apr-09

thJA

thJF

33 42

°C/WSteady State 70 84

16 21

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Page 2

Si4423DY

Vishay Siliconix

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

Gate Threshold Voltage

Gate-Body Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

Drain-Source On-State Resistance

Forward Transconductance

Diode Forward Voltage

Dynamic

Total Gate Charge

Gate-Drain Charge

Gate Resistance

Tur n - O n De l a y Ti m e

Rise Time

Tur n - O f f D e l ay T i m e

Fall Time

Source-Drain Reverse Recovery Time

GS(th)

GSS

DSS

D(on)

DS(on)

d(on)

d(off)

Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the de vice. These are stress rating s only, and functiona l operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

= VGS, ID = - 600 µA

VDS = 0 V, VGS = ± 8 V

= - 20 V, V

= - 5 V, V

= - 4.5 V, ID = - 14 A

= - 2.5 V, ID = - 13 A

= - 1.8 V, ID = - 12 A

= 0 V

= 0 V, TJ = 70 °C

= - 4.5 V

VDS = - 10 V, ID = - 14 A

IS = - 2.7 A, V

= - 10 V, V

= - 10 V, RL = 10 Ω

≅ - 1 A, V

GEN

= 0 V

= - 5 V, ID = - 14 A

= - 4.5 V, Rg = 6 Ω

IF = - 2.1 A, dI/dt = 100 A/µs

- 0.4 - 0.9 V

± 100 nA

- 1

- 10

- 30 A

0.006 0.0075

0.0071 0.009

0.009 0.0115

60 S

- 0.6 - 1.1 V

116 175

3.2 Ω

75 115

165 250

460 700

210 320

105 160

µA

nCGate-Source Charge

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

VGS = 5 thru 2 V

- Drain Current (A)I

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012345

- Drain-to-Source Voltage (V)

Output Characteristics

1.5 V

- Drain Current (A)I

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75

TC = 125 °C

25 °C

- Gate-to-Source Voltage (V)

Transfer Characteristics

Document Number: 72085

S09-0705-Rev. D, 27-Apr-09

- 55 °C

Page 3

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

1.6

Si4423DY

Vishay Siliconix

Ω )

- On-Resistance (R

DS(on)

0.015

0.012

VGS = 1.8 V

0.009

0.006

0.003

0.000 0 8 16 24 32 40

ID - Drain Current (A)

VGS = 2.5 V

VGS = 4.5 V

On-Resistance vs. Drain Current

VDS = 10 V I

= 13 A

12000

10000

8000

6000

C - Capacitance (pF)

4000

2000

048121620

1.4

1.2

iss

oss

rss

VDS - Drain-to-Source Voltage (V)

Capacitance

= 4.5 V

= 13 A

- Gate-to-Source Voltage (V)

0 25 50 75 100 125

Qg - Total Gate Charge (nC)

Gate Charge

100

- Source Current (A)I

0.1

0.0 0.2 0.4 0.6 0.8 1.0 1.2

TJ = 150 °C

VSD - Source-to-Drain Voltage (V)

Source-Drain Diode Forward Voltage

TJ = 25 °C

- On-Resistance R (Normalized)

1.0

DS(on)

0.8

0.6

- 5 0 - 25 0 2 5 5 0 7 5 100 125 150

- Junction T emperature (°C)

On-Resistance vs. Junction Temperature

0.030

0.024

Ω)

0.018

0.012

- On-Resistance (R

DS(on)

0.006

0.000

0.0 1.6 3.2 4.8 6.4 8.0

ID = 13 A

VGS - Gate-to-Source Voltage (V)

On-Resistance vs. Gate-to-Source Voltage

Document Number: 72085 S09-0705-Rev. D, 27-Apr-09

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Page 4

Si4423DY

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

0.6

0.4

ID = 250 µA

0.2

Variance (V)V

0.0

GS(th)

-0.2

-0.4

-50 -25 0 25 50 75 100 125 150

TJ - Temperature (°C)

Threshold Voltage

100

Limited by R *

DS ( on)

Power (W)

100

0.1 1010.010.001

Time (s)

Single Pulse Power, Junction-to-Ambient

1 ms

10 ms

100 ms

0.1

Thermal Impedance

Normalized Ef fective T ransient

0.01

Duty Cycle = 0.5

0.2

0.1

0.05

0.02

-4

Single Pulse

- Drain Current (A) I

0.1 T C = 25 °C

Single Pulse

1 s

10 s DC

0.1

0.1 1 10 100

VDS - Drain-to-Source Voltage (V)

> minimum VGS at which R

* V

DS(on)

is specified

Safe Operating Area, Junction-to-Case

-3

-2

-1

1 1 0 60010

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

Notes:

- T A = P

DM Z th J A

1. Duty Cycle, D =

2. Per Unit Base = R

3. T

4. Surface Mounted

= 70 °C/W

th J A

(t )

100

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Document Number: 72085

S09-0705-Rev. D, 27-Apr-09

Page 5

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Duty Cycle = 0.5

0.2

0.1

0.01

0.05

0.02

Single Pulse

-4

-3

-2

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Foot

Thermal Impedance

Normalized Effective Transient

Si4423DY

Vishay Siliconix

-1

11010

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72085

Document Number: 72085

www.vishay.com

S09-0705-Rev. D, 27-Apr-09

Page 6

SOIC (NARROW): 8-LEAD

JEDEC Part Number: MS-012

Package Information

Vishay Siliconix

DIM

A 1.35 1.75 0.053 0.069

B 0.35 0.51 0.014 0.020

C 0.19 0.25 0.0075 0.010

D 4.80 5.00 0.189 0.196

E 3.80 4.00 0.150 0.157

e 1.27 BSC 0.050 BSC

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.50 0.93 0.020 0.037

q0°8°0°8°

S 0.44 0.64 0.018 0.026

ECN: C-06527-Rev. I, 11-Sep-06 DWG: 5498

0.25 mm (Gage Plane)

h x 45

MILLIMETERS INCHES

Min Max Min Max

0.10 0.20 0.004 0.008

All Leads

0.101 mm

0.004"

Document Number: 71192 11-Sep-06

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Page 7

VISHAY SILICONIX

Trench FE T® Power MOSFETs

Application Note 808

Mounting LITTLE FOOT®, SO-8 Power MOSFETs

Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use

integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and

0.050

1.27

design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same.

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/ppg?72286), for the

0.027

0.69

0.07

1.98

Figure 2. Dual MOSFET SO-8 Pad Pattern

basis of the pad design for a LITTLE FOOT SO-8 power MOSFET. In converting this recommended minimum pad to the pad set for a power MOSFET, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package.

In the case of the SO-8 package, the thermal connections are very simple. Pins 5, 6, 7, and 8 are the drain of the MOSFET for a single MOSFET package and are connected together. In a dual package, pins 5 and 6 are one drain, and pins 7 and 8 are the other drain. For a small-signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The

The minimum recommended pad patterns for the single-MOSFET SO-8 with copper spreading (Figure 1) and dual-MOSFET SO-8 with copper spreading (Figure 2) show the starting point for utilizing the board area available for the heat-spreading copper. To create this pattern, a plane of copper overlies the drain pins. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. These patterns use all the available area underneath the body for this purpose.

total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board.

Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder

0.288

7.3

connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the

0.050

1.27

0.027

0.69

0.078

1.98

0.2

5.07

0.196

5.0

Figure 1. Single MOSFET SO-8 Pad

Pattern With Copper Spreading

Document Number: 70740 www.vishay.com Revision: 18-Jun-07 1

drain pins, the solder mask generation occurs automatically.

A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least

0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device.

0.288

7.3

0.2

5.07

With Copper Spreading

0.088

2.25

0.088

2.25

APPLICATION NOTE

Page 8

Application Note 826

Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR SO-8

0.172

(4.369)

0.028

(0.711)

Return to Index

0.022

(0.559)

0.246 (6.248)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.050

(1.270)

0.152

0.047

(3.861)

(1.194)

APPLICATION NOTE

www.vishay.com Document Number: 72606 22 Revision: 21-Jan-08

Page 9

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Vishay

Disclaimer

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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.

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Document Number: 91000 www.vishay.com Revision: 11-Mar-11 1