Datasheet si3410dv Datasheet

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Page 1

N-Channel 30-V (D-S) MOSFET

Si3410DV

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) R

Ordering Information: Si3410DV-T1-E3 (Lead (Pb)-free)

0.0195 at V

0.023 at V

3 mm

(Ω)

DS(on)

= 10 V 8

= 4.5 V 8

TSOP-6

Top View

Si3410DV-T1-GE3 (Lead (Pb)-free and Halogen-free)

2.85 mm

FEATURES

(A)

Qg (Typ.)

9.2 nC

• Halogen-free According to IEC 61249-2-21

Definition

•TrenchFET

Power MOSFET

• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

• Notebook Load Switch

• Low Current dc-to-dc

Marking Code

AM XXX

Part # Code

Lot Traceability and Date Code

(3)

N-Channel MOSFET

(1, 2, 5, 6)

(4)

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol Limit Unit

Drain-Source Voltage

Gate-Source Voltage

Continuous Drain Current (T

Pulsed Drain Current

= 150 °C)

Continuous Source-Drain Diode Current

Maximum Power Dissipation

Operating Junction and Storage Temperature Range

= 25 °C

= 70 °C 8

TA = 25 °C

TA = 70 °C

= 25 °C

= 70 °C 2.6

= 25 °C

TA = 70 °C

± 20

7.5

5.9 30

2.7

1.7

b,c

4.1

, T

stg

b,c

1.25

- 55 to 150 °C

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambient Maximum Junction-to-Foot

Notes: a. Package Limited. b. Surface mounted on 1" x 1" FR4 board. c. t = 5 s. d. Maximum under Steady State conditions is 110 °C/W.

b, d

t ≤ 5 s

Steady State

thJA

thJF

45 62.5

25 30

°C/W

Document Number: 69254 S09-2110-Rev. B, 12-Oct-09

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Page 2

Si3410DV

Vishay Siliconix

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

Drain-Source Breakdown Voltage V

Temperature Coefficient ΔVDS/T

Temperature Coefficient ΔV

GS(th)

Gate-Source Threshold Voltage

Gate-Source Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

Drain-Source On-State Resistance

Forward Transconductance

Dynamic

Input Capacitance

Reverse Transfer Capacitance

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

Gate Resistance

Tur n - O n D e l ay Time

Rise Time

Turn-Off DelayTime

Fall Ti me

Tur n - O n D e l ay Time

Rise Time

Turn-Off DelayTime

Fall Ti me

GS(th)/TJ

GS(th)

GSS

DSS

D(on)

DS(on)

iss

oss

rss

d(on)

d(off)

d(on)

d(off)

Drain-Source Body Diode Characteristics

Continous Source-Drain Diode Current

Pulse Diode Forward Current

Body Diode Voltage

Body Diode Reverse Recovery Time

Body Diode Reverse Recovery Charge

Reverse Recovery Fall Time

Reverse Recovery Rise Time

Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing.

IF = 3 A, dI/dt = 100 A/µs, TJ = 25 °C

= 0 V, ID = 250 µA

ID = 250 µA

= VGS, ID = 250 µA

VDS = 0 V, VGS = ± 20 V

= 30 V, VGS = 0 V

= 30 V, V

= 15 V, V

= 0 V, TJ = 55 °C

≥ 5 V, V

= 10 V, ID = 5 A

= 4.5 V, ID = 4 A

= 10 V, ID = 5 A

= 0 V, f = 1 MHz

= 10 V, ID = 5 A

= 4.5 V, ID = 5 A

= 10 V 20 A

f = 1 MHz 2.4 Ω

= 15 V, RL = 3 Ω

≅ 5 A, V

= 4.5 V, Rg = 1 Ω

GEN

= 15 V, RL = 3 Ω

= 10 V, Rg = 1 Ω

GEN

TC = 25 °C

IS = 1.7 A, V

= 0 V

30 V

- 6.2

mV/°C

13V

± 100 nA

0.016 0.0195

0.019 0.023

µA

24 S

1295

170

pFOutput Capacitance

21.8 33

9.2 14

3.8

2.5

21 40

14 25

20 40

918

10 20

816

21 35

816

2.7

0.77 1.2 V

21 40 ns

15 30 nC

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the de vice. These are stress rating s only, and functiona l operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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Document Number: 69254

S09-2110-Rev. B, 12-Oct-09

Page 3

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Si3410DV

Vishay Siliconix

VGS = 10 V thru 4 V

- Drain Current (A)I

VGS = 3 V

0.0 0.5 1.0 1.5 2.0 2.5

- Drain-to-Source Voltage (V)

Output Characteristics

0.030

0.026

0.022

VGS = 4.5 V

1.5

1.2

0.9

0.6

- Drain Current (A)I

0.3

0.0 012345

TC = 25 °C

TC = 125 °C

TC = - 55 °C

VGS - Gate-to-Source Voltage (V)

Transfer Characteristics

1600

iss

1280

960

0.018

- On-Resistance (Ω)R

DS(on)

0.014

0.010 0 6 12 18 24 30

VGS = 10 V

ID - Drain Current (A)

On-Resistance vs. Drain Current and Gate Voltage

ID = 5 A

VDS = 10 V

- Gate-to-Source Voltage (V)

0 5 10 15 20 25

Qg - Total Gate Charge (nC)

VDS = 15 V

VDS = 20 V

Gate Charge

640

C - Capacitance (pF)

320

061218 24 30

1.7

1.5

1.3

- On-Resistance

1.1

(Normalized)

DS(on)

0.9

0.7

- 50 - 25 0 25 50 75 100 125 150

oss

rss

VDS - Drain-to-Source Voltage (V)

Capacitance

ID = 5 A

VGS = 10 V

VGS = 4.5 V

- Junction Temperature (°C)

On-Resistance vs. Junction Temperature

Document Number: 69254 S09-2110-Rev. B, 12-Oct-09

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Page 4

Si3410DV

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

100

TJ = 150 °C

0.1

- Source Current (A)I

0.01

0.001

0.0 0.2 0.4 0.6 0.8 1.0 1.2

VSD - Source-to-Drain Voltage (V)

Source-Drain Diode Forward Voltage

0.6

ID = 250 µA

0.3

ID = 5 mA

TJ = 25 °C

0.10

0.08

0.06

- On-Resistance (Ω)R

0.04

DS(on)

0.02

012345678 910

VGS - Gate-to-Source Voltage (V)

On-Resistance vs. Gate-to-Source Temperature

TA = 125 °C

TA = 25 °C

Variance (V)

- 0.3

GS(th)

- 0.6

- 0.9

- 50 - 25 0 25 50 75 100 125 150

TJ - Temperature (°C)

Threshold Voltage

100

0.1

- Drain Current (A)I

0.01

0.001

0.1 1 10 100

Safe Operating Area, Junction-to-Ambient

Limited by R *

TA = 25 °C

Single Pulse

* V

DS(on)

VDS - Drain-to-Source Voltage (V)

minimum VGS at which R

Power (W)

DS(on)

1100.10.010.001

Time (s)

Single Pulse Power, Junction-to-Ambient

1 ms

10 ms

100 ms

1 s, 10 s

is specified

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Document Number: 69254

S09-2110-Rev. B, 12-Oct-09

Page 5

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Package Limited

- Drain Current (A)

0 25 50 75 100 125 150

TC - Case Temperature (°C)

Current Derating*

Si3410DV

Vishay Siliconix

1.5

Power (W)

0 25 50 75 100 125 150

TC - Case Temperature (°C)

Power Derating, Junction-to-Foot

* The power dissipation PD is based on T

= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper

J(max)

1.2

0.9

Power (W)

0.6

0.3

0.0 0 25 50 75 100 125 150

TA - Ambient Temperature (°C)

Power Derating, Junction-to-Ambient

dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit.

Document Number: 69254 S09-2110-Rev. B, 12-Oct-09

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Page 6

Si3410DV

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Duty Cycle = 0.5

0.2

0.1

0.01

Thermal Impedance

Normalized Effective Transient

0.001 10

0.1

Thermal Impedance

Normalized Effective Transient

0.01 10

0.1

0.05

0.02

-4

Duty Cycle = 0.5

0.2

0.1

0.05

0.02

Single Pulse

-4

Single Pulse

-3

-2

-1

Square Wave Pulse Duration (s)

Normalized Thermal Transient Impedance, Junction-to-Ambient

-3

-2

Square Wave Pulse Duration (s)

-1

Normalized Thermal Transient Impedance, Junction-to-Foot

Notes:

- TA = PDMZ

1. Duty Cycle, D =

2. Per Unit Base = R

3. T

4. Surface Mounted

100

thJA

(t)

= 110 °C/W

000101110

01110

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?69254

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Document Number: 69254

S09-2110-Rev. B, 12-Oct-09

Page 7

TSOP: 5/6−LEAD

JEDEC Part Number: MO-193C

Package Information

Vishay Siliconix

5 4

E 1 E

-B-

C 0.15 M B A

6 5 4

5-LEAD TSOP 6-LEAD TSOP

-C-

-A-

A 2 A

Seating Plane

C 0.08

E 1 E

(L 1 )

-B-

C 0.15 M B A

0.17 Ref c

Gauge Plane

Seating Plane

Document Number: 71200 18-Dec-06

MILLIMETERS INCHES

Dim Min Nom Max Min Nom Max

0.91 - 1.10 0.036 - 0.043

0.01 - 0.10 0.0004 - 0.004

0.90 - 1.00 0.035 0.038 0.039

0.30 0.32 0.45 0.012 0.013 0.018

0.10 0.15 0.20 0.004 0.006 0.008

2.95 3.05 3.10 0.116 0.120 0.122

2.70 2.85 2.98 0.106 0.112 0.117

1.55 1.65 1.70 0.061 0.065 0.067

ECN: C-06593-Rev. I, 18-Dec-06 DWG: 5540

0.95 BSC 0.0374 BSC

1.80 1.90 2.00 0.071 0.075 0.079

0.32 - 0.50 0.012 - 0.020

0.60 Ref 0.024 Ref

0.25 BSC 0.010 BSC

0.10 - - 0.004 - -

0 4 8 0 4 8

7 Nom 7 Nom

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Page 8

Vishay Siliconix

Mounting LITTLE FOOTR TSOP-6 Power MOSFETs

AN823

Surface mounted power MOSFET packaging has been based on integrated circuit and small signal packages. Those packages have been modified to provide the improvements in heat transfer required by power MOSFETs. Leadframe materials and design, molding compounds, and die attach materials have been changed. What has remained the same is the footprint of the packages.

The basis of the pad design for surface mounted power MOSFET is the basic footprint for the package. For the TSOP-6 package outline drawing see http://www.vishay.com/doc?71200 and see

http://www.vishay.com/doc?72610 for the minimum pad footprint.

In converting the footprint to the pad set for a power MOSFET, you must remember that not only do you want to make electrical connection to the package, but you must made thermal connection and provide a means to draw heat from the package, and move it away from the package.

In the case of the TSOP-6 package, the electrical connections are very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and are connected together. For a small signal device or integrated circuit, typical connections would be made with traces that are

0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board.

Since surface mounted packages are small, and reflow soldering is the most common form of soldering for surface mount components, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically.

A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device.

REFLOW SOLDERING

Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow temperature profile used, and the temperatures and time duration, are shown in Figures 2 and 3.

Figure 1 shows the copper spreading recommended footprint for the TSOP-6 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlays the basic pattern on pins 1,2,5, and 6. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. Notice that the planar copper is shaped like a “T” to move heat away from the drain leads in all directions. This pattern uses all the available area underneath the body for this purpose.

0.167

4.25

0.074

0.010

0.25

1.875

0.122

3.1

0.014

0.35

0.026

0.65

0.049

1.25

FIGURE 1. Recommended Copper Spreading Footprint

Document Number: 71743 27-Feb-04

Ramp-Up Rate

Temperature @ 155 " 15_C

Temperature Above 180_C

Maximum Temperature

Time at Maximum Temperature 20 − 40 Seconds

Ramp-Down Rate

FIGURE 2. Solder Reflow Temperature Profile

+6_C/Second Maximum

120 Seconds Maximum

70 − 180 Seconds

240 +5/−0_C

+6_C/Second Maximum

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Page 9

AN823

Vishay Siliconix

10 s (max)

255 − 260_C

1X4_C/s (max) 3-6_C/s (max)

140 − 170_C

3_C/s (max)

Maximum peak temperature at 240_C is allowed.

60-120 s (min)

Pre-Heating Zone

FIGURE 3. Solder Reflow Temperature and Time Durations

THERMAL PERFORMANCE

A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, Rq

, or the

junction-to-foot thermal resistance, Rqjf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows the thermal performance of the TSOP-6.

TABLE 1.

Equivalent Steady State Performance—TSOP-6

Thermal Resistance Rq

30_C/W

1.6

1.4

1.2

− On-Resiistance

1.0

(Normalized)

DS(on)

0.8

217_C

60 s (max)

Reflow Zone

On-Resistance vs. Junction Temperature

VGS = 4.5 V

= 6.1 A

SYSTEM AND ELECTRICAL IMPACT OF TSOP-6

In any design, one must take into account the change in MOSFET r

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with temperature (Figure 4).

DS(on)

0.6

−50 −25 0 25 50 75 100 125 150

− Junction Temperature (_C)

FIGURE 4. Si3434DV

Document Number: 71743

27-Feb-04

Page 10

Application Note 826

Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR TSOP-6

0.099

(2.510)

Return to Index

0.119 (3.023)

0.039

(1.001)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.020

(0.508)

0.019

(0.493)

0.064

0.028

(1.626)

(0.699)

APPLICATION NOTE

www.vishay.com Document Number: 72610 26 Revision: 21-Jan-08

Page 11

Legal Disclaimer Notice

Vishay

Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

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Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability.

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Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.

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Document Number: 91000 www.vishay.com Revision: 11-Mar-11 1