Datasheet si2318cd Datasheet

New Product

Marking Code

P9 XXX

Lot Traceability
and Date Code

Part # Code

Ordering Information: Si2318CDS-T1-GE3 (Lead (Pb)-free and Halogen-free)

N-Channel MOSFET

G

D

S

G

S

D

Top View

2

3

SOT-23

1

(3)

(2)

(1)

N-Channel 40 V (D-S) MOSFET

Si2318CDS

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) R

0.042 at V

40

0.051 at V

DS(on)

()

GS

GS

= 10 V

= 4.5 V

a

I

(A)

D

5.6

Qg (Typ.)

2.9 nC

5.1

FEATURES

• Halogen-free According to IEC 61249-2-21
Definition

• TrenchFET® Power MOSFET

• 100 % R

Tested

g

• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

• DC/DC Converters

• Load Switch

• Portable and Consumer Applications

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

Parameter Symbol Limit Unit

Drain-Source Voltage V
Gate-Source Voltage V

T

= 25 °C

C

T

= 70 °C

Continuous Drain Current (T

= 150 °C)

J

C

T

= 25 °C

A

TA = 70 °C

Pulsed Drain Current I

T

= 25 °C

Continuous Source-Drain Diode Current

Maximum Power Dissipation

C

= 25 °C

T

A

T

= 25 °C

C

= 70 °C

T

C

= 25 °C

T

A

P

TA = 70 °C

Operating Junction and Storage Temperature Range TJ, T

Soldering Recommendations (Peak Temperature)

DS

GS

I

D

DM

I

S

D

stg

40

± 20

a

5.6

4.5

b, c

4.3

b, c

3.5
20

1.75

b, c

1.04

2.1

1.3

b, c

1.25

b, c

0.8

- 55 to 150
260

V

A

W

°C

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambient
Maximum Junction-to-Foot (Drain) Steady State R

Notes:
a. Based on T
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. Maximum under steady state conditions is 125 °C/W.

= 25 °C

C

Document Number: 67030
S10-2250-Rev. A, 04-Oct-10

b, d

t  5 s R

thJA

thJF

80 100

40 60

°C/W

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New Product

Si2318CDS

Vishay Siliconix

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

V

Drain-Source Breakdown Voltage

V

Temperature Coefficient

DS

Temperature Coefficient

V

GS(th)

Gate-Source Threshold Voltage

Gate-Source Leakage

Zero Gate Voltage Drain Current

On-State Drain Current

a

Drain-Source On-State Resistance

Forward Transconductance

Dynamic

b

a

Input Capacitance

Reverse Transfer Capacitance

Total Gate Charge

Gate-Source Charge

Gate-Drain Charge

Gate Resistance

Tur n -O n De l ay T i m e

Rise Time

Turn-Off Delay Time

Fall Time

Tur n -O n De l ay T i m e

Rise Time

Turn-Off Delay Time

Fall Time

a

V

DS

V

DS/TJ

V

GS(th)/TJ

V

GS(th)

I

GSS

I

DSS

I

V

D(on)

R

DS(on)

g

fs

C

iss

C

oss

C

rss

Q

g

Q

gs

Q

gd

R

g

t

d(on)

t

r

t

d(off)

t

f

t

d(on)

t

r

t

d(off)

t

f

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current

Pulse Diode Forward Current

Body Diode Voltage

Body Diode Reverse Recovery Time

Body Diode Reverse Recovery Charge

Reverse Recovery Fall Time

Reverse Recovery Rise Time

I

S

I

SM

V

SD

t

rr

Q

rr

t

a

t

b

Notes:
a. Pulse test; pulse width  300 µs, duty cycle  2 %
b. Guaranteed by design, not subject to production testing.

V

DS

V

V

DS

V

DS

I

D

I

D

IF = 3.5 A, dI/dt = 100 A/µs, TJ = 25 °C

= 0 V, ID = 250 µA

GS

VDS = V

V

= 0 V, V

DS

V

= 40 V, V

DS

= 40 V, V

5 V, V

DS

V

10 V, ID = 4.3 A

GS

V

4.5 V, ID = 3.9 A

GS

V

= 20 V, ID = 4.3 A

DS

= 20 V, V

DS

= 20 V, V

= 20 V, V

= 20 V, RL = 5.7 

V

DD

 3.5 A, V

= 20 V, RL = 5.7 

V

DD

 3.5 A, V

TC = 25 °C

IS = 3.5 A, V

ID = 250 µA

, ID = 250 µA

GS

= ± 20 V

GS

GS

= 0 V, TJ = 70 °C

GS

= 10 V

GS

= 0 V, f = 1 MHz

GS

= 10 V, ID = 4.3 A

GS

= 4.5 V, ID = 4.3 A

GS

f = 1 MHz

= 4.5 V, Rg = 1 

GEN

= 10 V, Rg = 1 

GEN

0 V

GS

= 0 V

40 V

39

- 4.7

mV/°C

1.2 2.5

± 100 nA

1

10

20

0.035 0.042

0.041 0.051

17 S

340

60

30

5.8 9

2.9 6

1.1

0.9

0.6 3.3 6.6

12 20

50 75

10 20

8 16

714

20 30

14 21

8 16

1.75

20

0.851.2 V

15 23 ns

714nC

11

4

V

µA

A



pFOutput Capacitance

nC



ns

A

ns

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

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Document Number: 67030

S10-2250-Rev. A, 04-Oct-10

New Product

0.02

0.03

0.04

0.05

0.06

0 5 10 15 20

VGS=4.5V

VGS=10V

R

DS(on)

- On-Resistance (Ω)

ID - Drain Current (A)

0

2

4

6

8

10

0123456

ID=4.3A

VDS=20V

VDS=10V

VDS=32V

Qg - Total Gate Charge (nC)

V

GS

- Gate-to-Source Voltage (V)

C

rss

0

90

180

270

360

450

0 5 10 15 20

C

iss

C

oss

VDS - Drain-to-Source Voltage (V)

C - Capacitance (pF)

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Si2318CDS

Vishay Siliconix

20

VGS=10Vthru4V

15

10

- Drain Current (A)

D

I

5

0

0.0 0.5 1.0 1.5 2.0

VDS - Drain-to-Source Voltage (V)

Output Characteristics

5

4

=3V

V

GS

3

2

- Drain Current (A)

D

I

1

0

0.0 0.6 1.2 1.8 2.4 3.0

VGS - Gate-to-Source Voltage (V)

TC= - 55 °C

TC= 25 °C

TC= 125 °C

Transfer Characteristics

On-Resistance vs. Drain Current and Gate Voltage

Document Number: 67030
S10-2250-Rev. A, 04-Oct-10

Gate Charge

Capacitance

1.65

1.45

1.25

- On-Resistance

1.05

(Normalized)

DS(on)

R

0.85

0.65

- 50 - 25 0 25 50 75 100 125 150

VGS=10V;ID=4.3A

VGS=4.5V;ID=3.9A

TJ - Junction Temperature (°C)

On-Resistance vs. Junction Temperature

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New Product

0.1

1

10

100

0 0.3 0.6 0.9 1.2

TJ= 25 °C

TJ= 150 °C

VSD - Source-to-Drain Voltage (V)

I

S

- Source Current (A)

Si2318CDS

Vishay Siliconix

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

0.10

ID=4.3A

0.08

Source-Drain Diode Forward Voltage

2.0

1.8

1.6

(V)

GS(th)

V

1.4

1.2

1.0

- 50 - 25 0 25 50 75 100 125 150

TJ - Temperature (°C)

ID= 250 μA

Threshold Voltage

0.06

- On-Resistance (Ω)

DS(on)

0.04

R

0.02
246810

VGS - Gate-to-Source Voltage (V)

TJ= 125 °C

TJ= 25 °C

On-Resistance vs. Gate-to-Source Voltage

32

24

16

Power (W)

8

0

0.001 0.01 0.1 1 10 100

Time (s)

Single Pulse Power (Junction-to-Ambient)

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4

100

Limited by R

10

1

- Drain Current (A)

D

I

0.1

TA= 25 °C

Single Pulse

0.01

0.1 1 10 100

VDS - Drain-to-Source Voltage (V)

> minimum VGS at which R

* V

GS

*

DS(on)

BVDSS Limited

DS(on)

is specied

Safe Operating Area, Junction-to-Ambient

100 μs

1ms

10 ms

100 ms

1s,10s
DC

Document Number: 67030

S10-2250-Rev. A, 04-Oct-10

New Product

0

0.3

0.6

0.9

1.2

0 25 50 75 100 125 150

TA - Ambient Temperature (°C)

Power (W)

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

6.0

4.5

3.0

- Drain Current (A)

D

I

1.5

0

0 25 50 75 100 125 150

TC - Case Temperature (°C)

Current Derating*

Si2318CDS

Vishay Siliconix

2.5

2.0

1.5

Power (W)

1.0

0.5

0

0 25 50 75 100 125 150

TC - Case Temperature (°C)

Power Derating, Junction-to-Foot

* The power dissipation PD is based on T
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package

= 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper

J(max.)

Power Derating, Junction-to-Ambient

limit.

Document Number: 67030
S10-2250-Rev. A, 04-Oct-10

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New Product

10

-3

10

-2

1

10

10 00010

-1

10

-4

100

0.2

0.1

Square Wave Pulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1

0.1

0.01

t

1

t

2

Notes:

P

DM

1. Duty Cycle, D =

2. Per Unit Base = R

thJA

= 125 °C/W

3. T

JM-TA=PDMZthJA

(t)

t

1

t

2

4. Surface Mounted

Duty Cycle = 0.5

Single Pulse

0.02

0.05

1000

10

-3

10

-2

01110

-1

10

-4

0.2

0.1

Duty Cycle = 0.5

Square Wave Pulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1

0.1

0.05

Single Pulse

0.02

Si2318CDS

Vishay Siliconix

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Normalized Thermal Transient Impedance, Junction-to-Ambient

Normalized Thermal Transient Impedance, Junction-to-Foot

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for
Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?67030

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6

.

Document Number: 67030

S10-2250-Rev. A, 04-Oct-10

SOT-23 (TO-236): 3-LEAD

b

3

1

Package Information

Vishay Siliconix

E

E

1

2

S

A

A

2

A

1

Dim

A 0.89 1.12 0.035 0.044

A

1

A

2

b 0.35 0.50 0.014 0.020

c 0.085 0.18 0.003 0.007

D 2.80 3.04 0.110 0.120

E 2.10 2.64 0.083 0.104

E

1

e 0.95 BSC 0.0374 Ref

e

1

L 0.40 0.60 0.016 0.024

L

1

S 0.50 Ref 0.020 Ref

q 3°8°3°8°

ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479

e

e

1

D

0.10 mm

Seating Plane

C

0.004"

C

C

q

L

L

1

MILLIMETERS INCHES

Min Max Min Max

0.01 0.10 0.0004 0.004

0.88 1.02 0.0346 0.040

1.20 1.40 0.047 0.055

1.90 BSC 0.0748 Ref

0.64 Ref 0.025 Ref

0.25 mm

Gauge Plane

Seating Plane

Document Number: 71196
09-Jul-01

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Mounting LITTLE FOOTR SOT-23 Power MOSFETs

Wharton McDaniel

AN807

Vishay Siliconix

Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis

of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.

The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.

ambient air. This pattern uses all the available area underneath the
body for this purpose.

0.114

2.9

0.081

2.05

0.150

3.8

0.059

1.5

0.0394

FIGURE 1. Footprint With Copper Spreading

1.0

0.037

0.95

Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.

Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the

Document Number: 70739
26-Nov-03

A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.

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RECOMMENDED MINIMUM PADS FOR SOT-23

Application Note 826

Vishay Siliconix

0.106
(2.692)

0.037

(0.950)

0.053

(1.341)

0.097

(2.459)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.022

(0.559)

0.049

0.029

(1.245)

(0.724)

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Document Number: 72609 www.vishay.com
Revision: 21-Jan-08 25

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