Datasheet Si2312BDS Datasheet (Vishay)

N-Channel 20 V (D-S) MOSFET

Si2312BDS

Vishay Siliconix

PRODUCT SUMMARY

VDS (V) R

0.031 at V

20

0.047 at V

(Ω)I

DS(on)

= 4.5 V 5.0

GS

= 2.5 V 4.6

GS

= 1.8 V 4.1

GS

(A) Qg (Typ.)

D

7.50.037 at V

FEATURES

• Halogen-free According to IEC 61249-2-21
Definition

• TrenchFET

• 100 % R

• Compliant to RoHS Directive 2002/95/EC

®

Power MOSFET

Tested

g

TO-236

(SOT-23)

G

1

D

3

S

2

Top View

Si2312BDS (M2)*

* Marking Code

Ordering Information: Si2312BDS-T1-E3 (Lead (Pb)-free)
Si2312BDS-T1-GE3 (Lead (Pb)-free and Halogen-free)

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol 5 s Steady State Unit

Drain-Source Voltage V

Gate-Source Voltage V

Continuous Drain Current (T

Pulsed Drain Current

Avalanche Current

b

b

= 150 °C)

J

a

Single Avalanche Energy E

Continuous Source Current (Diode Conduction)

Power Dissipation

a

a

TA = 25 °C

= 70 °C 4.0 3.1

T

A

L = 0.1 mH

TA = 25 °C

T

= 70 °C 0.80 0.48

A

Operating Junction and Storage Temperature Range T

DS

GS

I

D

I

DM

I

AS

AS

I

S

P

D

, T

J

stg

5.0 3.9

1.0 0.63 A

1.25 0.75

20

± 8

15

13

8.45 mJ

W

- 55 to 150 °C

V

A

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambient

a

t ≤ 5 s

Maximum Junction-to-Foot Steady State R

Notes:
a. Surface mounted on 1" x 1" FR4 board.
b. Pulse width limited by maximum junction temperature.

Document Number: 73235
S10-0791-Rev. D, 05-Apr-10

R

thJA

thJF

80 100

°C/WSteady State 120 166

50 60

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Si2312BDS

Vishay Siliconix

SPECIFICATIONS TA = 25 °C, unless otherwise noted

Limits

Parameter Symbol Test Conditions

Min. Typ. Max.

Static

Drain-Source Breakdown Voltage V

Gate-Threshold Voltage V

Gate-Body Leakage I

Zero Gate Voltage Drain Current I

On-State Drain Current

Drain-Source On-Resistance

Forward Transconductance

a

a

a

Diode Forward Voltage V

Dynamic

b

GS(th)

GSS

DSS

I

D(on)

R

DS(on)

DS

g

SD

Total Gate Charge Qg

Gate-Drain Charge Q

Gate Resistance R

V

fs

gs

1.2

gd

g

VGS = 0 V, ID = 250 µA 20

V

= VGS, ID = 250 µA 0.45 0.85

DS

VDS = 0 V, VGS = ± 8 V ± 100 nA

V

V

DS

= 20 V, V

DS

= 20 V, V

GS

≥ 10 V, V

DS

V

= 4.5 V, ID = 5.0 A 0.025 0.031

GS

= 2.5 V, ID = 4.6 A 0.030 0.037

GS

V

= 1.8 V, ID = 4.1 A 0.036 0.047

GS

= 0 V 1

GS

= 0 V, TJ = 70 °C 75

= 4.5 V 15 A

GS

VDS = 15 V, ID = 5.0 A 30 S

IS = 1.0 A, V

= 0 V 0.8 1.2 V

GS

7.5 12

V

DS

= 10 V, V

= 4.5 V, ID = 5.0 A

GS

1.4

f = 1.0 MHz 1.1 2.2 3.3 Ω

Switching

Tur n -O n De l ay Ti m e t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Source-Drain Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

d(on)

V

r

d(off)

f

rr

rr

I

35 55

D

= 10 V, RL = 10 Ω

DD

≅ 1.0 A, V

= 4.5 V, Rg = 6 Ω

GEN

IF = 1.0 A, dI/dt = 100 A/µs

915

30 45

10 15

13 25

4.5 7 nC

Notes:
a. Pulse test: Pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

Unit

V

µA

ΩV

nCGate-Source Charge Q

ns

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

15

12

9

6

- Drain Current (A)I

D

3

0

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2

01234

VGS = 4.5 V thru 2 V

- Drain-to-Source Voltage (V)

V

DS

Output Characteristics

1.5 V

1 V

15

12

9

6

- Drain Current (A)I

D

3

0

0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0

TC = 125 °C

25 °C

- Gate-to-Source Voltage (V)

V

GS

- 55 °C

Transfer Characteristics

Document Number: 73235

S10-0791-Rev. D, 05-Apr-10

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

Si2312BDS

Vishay Siliconix

- On-Resistance (Ω)R

DS(on)

0.06

0.05

0.04

0.03

0.02

0.01

0.00

VGS = 1.8 V

VGS = 2.5 V

VGS = 4.5 V

03691215

ID - Drain Current (A)

On-Resistance vs. Drain Current

5

VDS = 10 V
I

= 5.0 A

D

4

3

1200

1000

800

600

400

C - Capacitance (pF)

200

C

rss

0

0 4 8 12 16 20

1.6

1.4

1.2

C

iss

C

oss

VDS - Drain-to-Source Voltage (V)

Capacitance

VGS = 4.5 V
I

= 5.0 A

D

2

- Gate-to-Source Voltage (V)

GS

1

V

0

012345678

Qg - Total Gate Charge (nC)

Gate Charge

20

10

TJ = 150 °C

1

TJ = 25 °C

0.1

- Source Current (A)I

S

0.01

0.001

0.0 0.2 0.4 0.6 0.8 1.0 1.2

VSD - Source-to-Drain Voltage (V)

Source-Drain Diode Forward Voltage

- On-Resistance

1.0

(Normalized)

DS(on)

R

0.8

0.6

- 50 - 25 0 25 50 75 100 125 150

0.20

0.15

0.10

- On-Resistance (Ω)R

DS(on)

0.05

0.00
012345678

- Junction Temperature (°C)

T

J

On-Resistance vs. Junction Temperature

ID = 5.0 A

VGS - Gate-to-Source Voltage (V)

On-Resistance vs. Gate-to-Source Voltage

Document Number: 73235
S10-0791-Rev. D, 05-Apr-10

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Si2312BDS

Vishay Siliconix

TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

0.3

0.2

8

7

0.1

ID = 250 µA

0.0

- 0.1

Variance (V)V

- 0.2

GS(th)

- 0.3

- 0.4

- 0.5

- 50 - 25 0 25 50 75 100 125 150
TJ - Temperature (°C)

Threshold Voltage

100

10

- Drain Current (A)I

D

0.1

0.01

6

5

4

Power (W)

3

2

1

0

0.01

Limited

by R

DS(on)*

10 µs

100 µs

1

1 ms

10 ms

100 ms

TA = 25 °C

Single Pulse

1 s
10 s
100 s, DC

Only valid when VGS = or > 1.8 V

0.1 1 10 100

- Drain-to-Source Voltage (V)

V

* V

DS

> minimum VGS at which R

GS

DS(on)

is specified

Safe Operating Area

TA = 25 °C

1

10

Time (s)

Single Pulse Power

100 6000.1

2

1

Duty Cycle = 0.5

0.1

Thermal Impedance

Normalized Effective Transient

0.01

0.2

0.1

0.05

0.02

Single Pulse

4

-

10

3

-

10

2

-

10

1

-

Square Wave Pulse Duration (s)

1 10 60010

Notes:

P

DM

t

1

t

- TA = PDMZ

JM

2

1. Duty Cycle, D =

2. Per Unit Base = R

3. T

4. Surface Mounted

t

1

t

2

= 166 °C/W

thJA

(t)

thJA

100

Normalized Thermal Transient Impedance, Junction-to-Ambient

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?73235

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4

.

Document Number: 73235

S10-0791-Rev. D, 05-Apr-10

SOT-23 (TO-236): 3-LEAD

b

3

1

Package Information

Vishay Siliconix

E

E

1

2

S

A

A

2

A

1

Dim

A 0.89 1.12 0.035 0.044

A

1

A

2

b 0.35 0.50 0.014 0.020

c 0.085 0.18 0.003 0.007

D 2.80 3.04 0.110 0.120

E 2.10 2.64 0.083 0.104

E

1

e 0.95 BSC 0.0374 Ref

e

1

L 0.40 0.60 0.016 0.024

L

1

S 0.50 Ref 0.020 Ref

q 3°8°3°8°

ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479

e

e

1

D

0.10 mm

Seating Plane

C

0.004"

C

C

q

L

L

1

MILLIMETERS INCHES

Min Max Min Max

0.01 0.10 0.0004 0.004

0.88 1.02 0.0346 0.040

1.20 1.40 0.047 0.055

1.90 BSC 0.0748 Ref

0.64 Ref 0.025 Ref

0.25 mm

Gauge Plane

Seating Plane

Document Number: 71196
09-Jul-01

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Mounting LITTLE FOOTR SOT-23 Power MOSFETs

Wharton McDaniel

AN807

Vishay Siliconix

Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis

of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.

The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.

ambient air. This pattern uses all the available area underneath the
body for this purpose.

0.114

2.9

0.081

2.05

0.150

3.8

0.059

1.5

0.0394

FIGURE 1. Footprint With Copper Spreading

1.0

0.037

0.95

Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.

Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the

Document Number: 70739
26-Nov-03

A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.

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RECOMMENDED MINIMUM PADS FOR SOT-23

Application Note 826

Vishay Siliconix

0.106
(2.692)

0.037

(0.950)

0.053

(1.341)

0.097

(2.459)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.022

(0.559)

0.049

0.029

(1.245)

(0.724)

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Document Number: 72609 www.vishay.com
Revision: 21-Jan-08 25

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definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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Revision: 02-Oct-12

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Document Number: 91000