Datasheet si2301cd Datasheet

P-Channel 20 V (D-S) MOSFET

G

TO-236

(SOT-23)

S

D

Top View

2

3

1

Si2301CDS (N1)*

* Marking Code

Ordering Information: Si2301CDS-T1-E3 (Lead (Pb)-free)
Si2301CDS-T1-GE3 (Lead (Pb)-free and Halogen-free)

Si2301CDS

Vishay Siliconix

MOSFET PRODUCT SUMMARY

VDS (V) R

0.112 at V

- 20

0.142 at V

DS(on)

GS

GS

()

= - 4.5 V

= - 2.5 V

I

D

- 3.1

- 2.7

(A)

a

Qg (Typ.)

3.3 nC

FEATURES

• Halogen-free According to IEC 61249-2-21
Definition

• TrenchFET® Power MOSFET

• Compliant to RoHS Directive 2002/95/EC

APPLICATIONS

• Load Switch

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)

Parameter Symbol Limit Unit

Drain-Source Voltage

Gate-Source Voltage

Continuous Drain Current (T

= 150 °C)

J

T

= 25 °C

C

T

= 70 °C

C

= 25 °C - 2.3

T

A

V

V

TA = 70 °C - 1.8

Pulsed Drain Current

Continuous Source-Drain Diode Current

Maximum Power Dissipation

T

= 25 °C

C

T

= 25 °C - 0.72

A

T

= 25 °C

C

T

= 70 °C

C

T

= 25 °C 0.86

A

I

P

TA = 70 °C 0.55

Operating Junction and Storage Temperature Range TJ, T

DS

GS

I

D

DM

I

S

D

stg

- 20

± 8

- 3.1

- 2.5

b, c

b, c

- 10

- 1.3

b, c

1.6

1.0

b, c

b, c

- 55 to 150

V

A

W

°C

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit

Maximum Junction-to-Ambient

Maximum Junction-to-Foot (Drain)

Notes:
a. Based on T
b. Surface mounted on 1" x 1" FR4 board.
c. t = 5 s.
d. Maximum under steady state conditions is 175 °C/W.

Document Number: 68741
S10-2430-Rev. C, 25-Oct-10

= 25 °C.

C

b, d

Steady State

5 s

R

thJA

R

thJF

120 145

62 78

°C/W

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Si2301CDS

Vishay Siliconix

MOSFET SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

Parameter Symbol Test Conditions Min. Typ. Max. Unit

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient VDS/T

DS

Temperature Coefficient

V

GS(th)

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

On-State Drain Current

Drain-Source On-State Resistance

Forward Transconductance

Dynamic

b

a

a

a

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Source Charge Q

Gate-Drain Charge Q

Gate Resistance R

Tur n - O n D e l ay Time t

Rise Time t

Turn-Off Delay Time t

Fall Ti me t

DS

J



V

GS(th)/TJ

GS(th)

GSS

DSS

I

V

D(on)

R

DS(on)

g

fs

iss

75

oss

55

rss

g

gs

1.3

gd

f = 1 MHz 6.0 

g

d(on)

r

30 50

d(off)

f

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulse Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Reverse Recovery Fall Time t

Reverse Recovery Rise Time t

S

I

SM

SD

rr

rr

a

b

Notes:
a. Pulse test; pulse width  300 µs, duty cycle  2 %.
b. Guaranteed by design, not subject to production testing.

V

= 0 V, ID = - 250 µA - 20 V

GS

ID = - 250 µA

V

= VGS, ID = - 250 µA - 0.4 - 1 V

DS

- 18

2.2

VDS = 0 V, VGS = ± 8 V ± 100 nA

V

V

DS

= - 20 V, V

DS

= - 20 V, V

DS

V

V

GS

- 5 V, V

= - 4.5 V, ID = - 2.8 A 0.090 0.112

GS

= - 2.5 V, ID = - 2.0 A 0.110 0.142

GS

= 0 V - 1

GS

= 0 V, TJ = 55 °C - 10

= - 4.5 V - 6 A

GS

VDS = - 5 V, ID = - 2.8 A 9.5 S

405

V

DS

= - 10 V, V

V

DS

= - 10 V, V

= 0 V, f = 1 MHz

GS

= - 4.5 V, ID = - 3 A 5.5 10

GS

3.3 6

= - 10 V, V

V

DS

= - 2.5 V, ID = - 3 A

GS

0.7

11 20

V

I

= - 1 A, V

D

= - 10 V, RL = 10 

DD

= - 4.5 V, Rg = 1 

GEN

35 60

10 20

TC = 25 °C - 1.3

IS = - 0.7 A - 0.8 - 1.2 V

30 50 ns

IF = - 3.0 A, dI/dt = 100 A/µs, TJ = 25 °C

25 50 nC

15

15

- 10

mV/°C

µA



pFOutput Capacitance C

nC

ns

A

ns

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the de vice. These are stress rating s only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

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Document Number: 68741

S10-2430-Rev. C, 25-Oct-10

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

VGS=1.5V

0

2

4

6

8

10

0.0 0.5 1.0 1.5 2.0

V

DS

- Drain-to-Source Voltage (V)

- Drain Current (A)I

D

VGS=5V thru 2.5 V

V

GS

=1V

V

GS

=2V

0.00

0.05

0.10

0.15

0.20

02468 10

- On-Resistance (Ω)R

DS(on)

ID- Drain Current (A)

VGS=4.5V

VGS=2.5V

0

2

4

6

8

02468 10

- Gate-to-Source Voltage (V)

Qg- Total Gate Charge (nC)

V

GS

ID=3A

VDS=10V

VDS=5V

VDS=15V

0.00

0.25

0.50

0.75

1.00

0.0 0.3 0.6 0.9 1.2 1.5

V

GS

- Gate-to-Source Voltage (V)

- Drain Current (A)I

D

TC= 25 °C

TC= 125 °C

TC= - 55 °C

Si2301CDS

Vishay Siliconix

Output Characteristics

On-Resistance vs. Drain Current and Gate Voltage

Transfer Characteristics

800

600

C

iss

400

C - Capacitance (pF)

200

C

0

0 5 10 15 20

C

oss

rss

VDS- Drain-to-Source Voltage (V)

Capacitance

1.5

ID=2.8 A

1.3

Document Number: 68741
S10-2430-Rev. C, 25-Oct-10

Gate Charge

1.1

- On-Resistance
(Normalized)

VGS=4.5V

DS(on)

R

0.9

VGS=1.8V

0.7

- 50 - 25 0 25 50 75 100 125 150

T

-Junction Temperature (°C)

J

On-Resistance vs. Junction Temperature

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3

Si2301CDS

- 0.2

- 0.1

0.0

0.1

0.2

0.3

0.4

- 50 - 25 0 25 50 75 100 125 150

ID= 250 µA

Variance (V)V

GS(th)

TJ- Temperature (°C)

ID=1mA

0.00

0.15

0.30

0.45

0.60

012345

- On-Resistance (Ω)R

DS(on)

VGS- Gate-to-Source Voltage (V)

TJ=25 °C

TJ= 125 °C

ID=2.8 A

Vishay Siliconix

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

10

TJ= 150 °C

1

TJ= 25 °C

- Source Current (A)I

S

0.1

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

-Source-to-Drain Voltage (V)

V

SD

Source-Drain Diode Forward Voltage

TJ= - 50 °C

On-Resistance vs. Gate-to-Source Voltage

10

8

6

Power (W)

4

2

TA= 25 °C

Threshold Voltage

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4

10

Limited byR

1

- Drain Current (A)I

0.1

D

Single Pulse

0.01

0.1 1 10

* V

*

DS(on)

TA= 25 °C

VDS- Drain-to-Source Voltage (V)

> minimum VGSat which R

GS

Safe Operating Area

BVDSS Limited

0

0.01 0.1 1 10 100 1000

Time (s)

Single Pulse Power

100 µs

1ms

10 ms

100 ms

1s
10 s
100 s, DC

100

is specified

DS(on)

Document Number: 68741

S10-2430-Rev. C, 25-Oct-10

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

10

-3

10

-2

1

10

100010

-1

10

-4

100

0.2

0.1

Square WavePulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1

0.1

0.01

Duty Cycle = 0.5

Single Pulse

0.02

0.05

10

-3

10

-2

01110

-1

10

-4

0.2

0.1

Duty Cycle = 0.5

Square WavePulse Duration (s)

Normalized Effective Transient

Thermal Impedance

1

0.1

0.01

Single Pulse

0.02

0.05

t

1

t

2

Notes:

P

DM

1. Duty Cycle, D =

2. Per Unit Base = R

thJF

=50 °C/W

3. T

JM-TA=PDMZthJA

(t)

t

1

t

2

4. Surface Mounted

Normalized Thermal Transient Impedance, Junction-to-Ambient

Si2301CDS

Vishay Siliconix

Normalized Thermal Transient Impedance, Junction-to-Foot

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?68741

.

Document Number: 68741
S10-2430-Rev. C, 25-Oct-10

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SOT-23 (TO-236): 3-LEAD

b

3

1

Package Information

Vishay Siliconix

E

E

1

2

S

A

A

2

A

1

Dim

A 0.89 1.12 0.035 0.044

A

1

A

2

b 0.35 0.50 0.014 0.020

c 0.085 0.18 0.003 0.007

D 2.80 3.04 0.110 0.120

E 2.10 2.64 0.083 0.104

E

1

e 0.95 BSC 0.0374 Ref

e

1

L 0.40 0.60 0.016 0.024

L

1

S 0.50 Ref 0.020 Ref

q 3°8°3°8°

ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479

e

e

1

D

0.10 mm

Seating Plane

C

0.004"

C

C

q

L

L

1

MILLIMETERS INCHES

Min Max Min Max

0.01 0.10 0.0004 0.004

0.88 1.02 0.0346 0.040

1.20 1.40 0.047 0.055

1.90 BSC 0.0748 Ref

0.64 Ref 0.025 Ref

0.25 mm

Gauge Plane

Seating Plane

Document Number: 71196
09-Jul-01

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Mounting LITTLE FOOTR SOT-23 Power MOSFETs

Wharton McDaniel

AN807

Vishay Siliconix

Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.

See Application Note 826, Recommended Minimum Pad

Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis

of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.

The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.

ambient air. This pattern uses all the available area underneath the
body for this purpose.

0.114

2.9

0.081

2.05

0.150

3.8

0.059

1.5

0.0394

FIGURE 1. Footprint With Copper Spreading

1.0

0.037

0.95

Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.

Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the

Document Number: 70739
26-Nov-03

A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.

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RECOMMENDED MINIMUM PADS FOR SOT-23

Application Note 826

Vishay Siliconix

0.106
(2.692)

0.037

(0.950)

0.053

(1.341)

0.097

(2.459)

Recommended Minimum Pads

Dimensions in Inches/(mm)

0.022

(0.559)

0.049

0.029

(1.245)

(0.724)

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Document Number: 72609 www.vishay.com
Revision: 21-Jan-08 25

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