Datasheet SG6742HL, SG6742HR Datasheet (Fairchild)

SG6742HL/HR Highly Integrated Green-Mode PWM Controller

SG6742HL/HR — Highly Integrated Green-Mode PWM Controller

April 2009

Features

 High-Voltage Startup  Low Operating Current: 2.7mA  Linearly Decreasing PWM Frequency to 22KHz  Frequency Hopping to Reduce EMI Emission  Fixed PWM Frequency: 100KHz  Peak-Current-Mode Control  Cycle-by-Cycle Current Limiting  Leading-Edge Blanking (LEB)  Synchronized Slope Compensation  Internal Open-Loop Protection  GATE Output Maximum Voltage Clamp: 18V  V  V

Under-Voltage Lockout (UVLO)

DD

Over-Voltage Protection (OVP)

DD

 Programmable Over-Temperature Protection (OTP)  Internal Latch Circuit (OVP, OTP)  Internal-Sense, Short-Circuit Protection  Built-in 6ms Soft-Start Function  Constant Power Limit (Full AC Input Range)  Internal OTP Sensor with Hysteresis

Applications

General-purpose switch-mode power supplies and flyback power converters, including:

 Power Adapters  Open-Frame SMPS

Description

The highly integrated SG6742HL/HR PWM controller provides several features to enhance the performance of flyback converters.

To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to linearly decrease the switching frequency at light-load conditions. To avoid acoustic-noise problems, the minimum PWM frequency is set above 22KHz. This green-mode function enables the power supply to meet international power conservation requirements. With the internal high-voltage startup circuitry, the power loss due to bleeding resistors is eliminated. To further reduce power consumption, SG6742HL/HR is manufactured using the BiCMOS process, which allows an operating current of 2.7mA.

SG6742HL/HR integrates a frequency-hopping function internally that helps reduce EMI emission of a power supply with minimum line filters. Its built-in synchronized slope compensation achieves stable peak-current-mode control. The proprietary, internal line compensation ensures constant output power limit over a wide AC input voltage range, from 90V

SG6742HL/HR provides many protection functions. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety should an open-loop or output short-circuit failure occur. PWM output is disabled until V limit, when the controller starts up again. As long as V exceeds ~25V, the internal OVP circuit is triggered.

SG6742HL/HR is available in an 8-pin SOP package.

to 264VAC.

AC

drops below the UVLO lower

DD

Ordering Information

Part

Number

SG6742HLSY -40 to +105°C Latch 8-Lead Small Outline Package (SOP) Green Tape & Reel

SG6742HRSY -40 to +105°C Restart 8-Lead Small Outline Package (SOP) Green Tape & Reel

For Fairchild’s definition of “green” Eco Status, please vis i t : http://www.fairchildsemi.com/company/green/rohs_green.html.

Operating

Temperature

Range

OLP

Function

Package

Eco

Status

Packing

Method

R

Application Diagram

SG6742HL/HR — Highly Integrated Green-Mode PWM Controller

Internal Block Diagram

Figure 1. Typical Application

SG6742HL

SG6742H

Figure 2. Functional Block Diagram

Marking Information

ZXYTT 6742HR TPM

Pin Configuration

ZXYTT 6742HL TPM

Figure 3. Top Mark

SG6742HL/HR — Highly Integrated Green-Mode PWM Controller

F - Fairchild Logo

Z - Plant Code X - 1-Digit Year Code Y - 1-Digit Week Code TT - 2-Digit Die Run Code T - Package Type (S=SOP) P - Y: Green Package M - Manufacture Flow Code

SOP-8

GND

FB

NC

18

2

3

7

6

GATE

VDD

SENSE

HV

54

RT

Figure 4. Pin Configuration (Top View)

Pin Definitions

Pin # Name Description

1 GND Ground.

2 FB

3 NC No connection.

4 HV For startup, this pin is pulled high to the line input or bulk capacitor via resistors.

5 RT

6 SENSE

7 VDD

8 GATE The totem-pole output driver. Soft driving waveform is implemented for improved EMI.

The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is determined in response to the signal on this pin and the current-sense signal on the SENSE pin.

For over-temperature protection, an external NTC thermistor is connected from this pin to the GND pin. The impedance of the NTC decreases at high temperatures. Once the voltage of the RT pin drops below a fixed limit, PWM output is latched.

Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting.

Power supply. The internal protection circuit disables PWM output as long as V OVP trigger point.

exceeds the

DD

SG6742HL/HR — Highly Integrated Green-Mode PWM Controller

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

V

DC Supply Voltage

VDD

VFB FB Pin Input Voltage -0.3 7.0 V

V

SENSE Pin Input Voltage -0.3 7.0 V

SENSE

VRT RT Pin Input Voltage -0.3 7.0 V

VHV HV Pin Input Voltage 500 V

PD

ΘJA

Power Dissipation (T

Thermal Resistance (Junction-to-Air) 141

TJ Operating Junction Temperature -40 +125

T

Storage Temperature Range -55 +150

STG

TL Lead Temperature (Wave Soldering or IR, 10 Seconds) +260

Human Body Model,

ESD

JEDEC:JESD22-A114

Charged Device Model, JEDEC:JESD22-C101

Notes:

1. All voltage values, except differential voltages, are given with respect to the network ground terminal.

2. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.

(1, 2)

30 V

＜50°C)

A

400 mW

°C/W

°C

All pins except HV pin 4.0

kV

All pins except HV pin 1.5

SG6742HL/HR — Highly Integrated Green-Mode PWM Controller

Electrical Characteristics

VDD=15V and TA=25°C unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Units

VDD Section

VOP Continuously Operating Voltage 22 V

V

Start Threshold Voltage 14.5 15.5 16.5 V

DD-ON

V

Minimum Operating Voltage 8.5 9.5 10.5 V

DD-OFF

I

Startup Current V

DD-ST

I

Operating Supply Current VDD=15V, GATE Open 2.7 3.7 mA

DD-OP

I

Internal Sink Current

DD-OLP

V

I

TH-OLP

V

VDD Over-Voltage Protection 24 25 26 V

DD-OVP

t

D-VDDOVP

VDD Over-Voltage Protection Debounce Time

HV Section

off Voltage 6.5 7.5 8.0 V

DD-OLP

– 0.16V 30 µA

DD-ON

V

TH-OLP

+0.1V

30 60 90 µA

75 125 200 µs

IHV Supply Current from HV Pin

I

Leakage Current After Startup

HV-LC

VAC=90V (VDC=120V), V

=0V

DD

HV=500V, VDD=V

+1V

OFF

DD-

1.75 2.30 3.35

1 20 µA

Oscillator Section

f

Frequency in Normal Mode

OSC

t

Hopping Period 4.9 5.6 6.3 ms

HOP

f

Green-Mode Frequency 18 22 25 KHz

OSC-G

fDV

fDT

Frequency Variation vs. VDD Deviation

Frequency Variation vs. Temperature Deviation

Center Frequency

Hopping Range ±4.2 ±4.7 ±5.2

VDD=11V to 22V 5 %

TA=-40 to 105°C

PWM Frequency

f

OSC

f

OSC-G

V

FB-ZDC

FB-G

V

FB-N

Figure 5. V

vs. PWM Frequency

FB

90 100 110

5 %

Continued on the following page…

V

FB

mA

KHz

Electrical Characteristics (Continued)

VDD=15V and TA=25°C unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Units

Feedback Input Section

AV Input Voltage to Current-Sense Attenuation 1/4.15 1/4.00 1/3.85 V/V

ZFB Input Impedance 4 7 kΩ

V

Current-Sense Section

GATE Section

DCY

V

I

GATE-SINK

RT Section

Over-Temperature Protection Section (OTP)

Notes:

3. When activated, the output is disabled and the latch is turned off.

4. The threshold temperature for enabling the output again and resetting the latch after OTP has been activated.

Output High Voltage FB Pin Open 5.2 V

FB-OPEN

FB Open-Loop Trigger Level 4.6 4.8 5.0 V

FB-OLP

t

Delay Time of FB Pin Open-loop Protection 50 56 62 ms

D-OLP

V

Green-Mode Entry FB Voltage 3.1 3.3 3.5 V

FB-N

V

-

V

Green-Mode Ending FB Voltage

FB-G

Zero Duty-Cycle Input Voltage

FB-ZDC

Z

Input Impedance 12 KΩ

SENSE

V

Current Limit Flatten Threshold Voltage Duty cycle=45% 0.97 1.00 1.03 V

STHFL

V

Current Limit Valley Threshold Voltage V

STHVA

STHFL–VSTHVA

0.27 0.30 0.33 V

1.6

FB-N

0.5

V

tPD Delay to Output 100 200 ns

t

Leading-Edge Blanking Time 100 140 180 ns

LEB

V

Threshold Voltage for SENSE Short-Circuit Protection 0.10 0.15 0.20 V

S-SCP

t

D-SSCP

Delay Time for SENSE Short-Circuit Protection

V

SENSE

<0.15V

100 150 200 µs

tSS Period During Soft-Startup Time Startup Time 5 6 7 ms

Maximum Duty Cycle 60 65 70 %

MAX

Gate Low Voltage

GATE-L

Gate High Voltage

GATE-H

tr

Gate Rising Time V

tf

Gate Falling Time V

I

GATE-

SOURCE

V

GATE-

CLAMP

Gate Source Current V

Gate Sink Current V

Gate Output Clamping Voltage V

V

=15V, IO=50mA

DD

V

=12V, IO=50mA

DD

=15V, CL=1nF 150 250 350

DD

=15V, CL=1nF 30 50 90

DD

=15V, GATE=6V 250

DD

=15V, GATE=1V 300

DD

=22V 18

DD

1.5 V

8 V

RRT Internal Resistor from RT Pin 10.08 10.50 10.92 KΩ

V

RTTH1

V

RTTH2

t

D-OTP1

t

D-OTP2

T

OTP

T

Restart

Over-Temperature Protection Threshold Voltage

V

Over-Temperature Latch-off Debounce

Protection Junction Temperature

Restart Junction Temperature

(3)

+135 °C

(4)

T

0.7V ＜ V After 12ms Latch Off

V

＜ 0.7V, After

RT

100µs Latch Off

RTTH2

VRT< V

＜ 1.05V,

RT

1.015 1.050 1.085 V

0.65 0.70 0.75 V

＜ V

RT

90 130 170 µs

RTTH2

16 20 24 ms

RTTH1

-25 °C

OTP

V

ns

mA

V

SG6742HL/HR — Highly Integrated Green-Mode PWM Controller

Typical Performance Characteristics

25

SG6742HL/HR — Highly Integrated Green-Mode PWM Controller

5

20

15

(μA)

DD_ST

10

I

5

0

-40 -30 -15 0 25 50 75 85 100 125

Figure 6. Startup Current (I

18

17

16

(V)

DD-ON

V

15

14

13

-40 -30 -15 0 2 5 50 75 85 100 125

Temperature (℃)

DD-ST

Temperature (℃)

) vs. Temperature

Figure 8. Start Threshold Voltage (V

vs. Temperature

5

DD-ON

)

4

3

(mA)

DD-OP

I

2

1

0

-40 -3 0 - 15 0 25 50 75 85 100 125

Temperature (℃)

Figure 7. Operation Supply Current (I

vs. Temperature

12

11

10

(V)

DD-OFF

9

V

8

7

-40 -30 -15 0 2 5 50 75 85 100 125

Temperature (℃)

Figure 9. Minimum Operating Voltage (V

vs. Temperature

10

DD-OP

DD-OFF

)

4

3

(mA)

HV

I

2

1

0

-40 -3 0 - 15 0 25 50 75 85 100 125

Temperature (℃)

Figure 10. Supply Current Drawn from HV Pin (IHV)

vs. Temperature

105

103

101

(kHz)

OSC

99

F

97

95

-40 -30 - 15 0 25 50 75 85 100 125

Figure 12. Frequency in Normal Mode (f

Temperature (℃)

OSC

vs. Temperature

)

8

6

(μA)

HV-LC

I

4

2

0

-40 -30 -15 0 2 5 50 75 85 100 125

Temperature (℃)

Figure 11. HV Pin Leakage Current after Startup

(I

) vs. Temperature

HV-LC

70

68

66

(%)

MAX

64

DCY

62

60

-40 -30 -15 0 2 5 50 75 85 100 125

Temperature (℃)

Figure 13. Maximum Duty Cycle (DCY

vs. Temperature

MAX

)

Typical Performance Characteristics

7

SG6742HL/HR — Highly Integrated Green-Mode PWM Controller

62

6

(V)

5

FB-OLP

V

4

3

-40 -3 0 - 15 0 25 50 75 85 100 125

Temperature (℃)

Figure 14. FB Open-Loop Trigger Level (V

Temperature

0.15

0.145

(V)

0.14

S-SCP

V

0.135

0.13

-40 -30 -15 0 25 50 75 85 100 125

Temperature (℃)

FB-OLP

) vs.

Figure 16. Threshold Voltage for SENSE Short-Circuit

Protection (V

1.2

) vs. Temperature

S-SCP

60

58

(ms)

56

D-OLP

t

54

52

50

-40 -30 -15 0 2 5 50 75 85 100 125

Temperature (℃)

Figure 15. Delay Time of FB Pin Open-Loop Protection

(t

) vs. Temperature

D-OLP

100

99

98

(μA

RT

I

97

96

-40 -30 -15 0 25 50 75 85 100 125

Temperature (℃)

Figure 17. Output Current from RT Pin (IRT)

vs. Temperature

0.9

1.1

(V)

1

RTTH1

V

0.9

0.8

-40 -30 -15 0 25 50 75 85 100 125

Temperature (℃)

Figure 18. Over-Temperature Protection Threshold

Voltage (V

28

27

26

(V)

DD-OVP

25

V

24

23

-40 -30 -15 0 2 5 50 75 85 100 125

) vs. Temperature

RTTH1

Temperature (℃)

0.8

(V)

0.7

RTTH2

V

0.6

0.5

-40 -30 -15 0 25 50 75 85 100 125

Temperature (℃)

Figure 19. Over-Temperature Protection Threshold

Voltage (V

) vs. Temperature

RTTH2

Figure 20. VDD Over-Voltage Protection (V

vs. Temperature

DD-OVP

)

Functional Description

SG6742HL/HR — Highly Integrated Green-Mode PWM Controller

Startup Current

For startup, the HV pin is connected to the line input or bulk capacitor through an external diode and resistor, R

, (1N4007 / 100KΩ recommended). Typical startup

HV

current drawn from pin HV is 2.3mA and charges the hold-up capacitor through the diode and resistor. When the V current switches off. At this moment, the V only supplies the SG6742HL/HR to keep the V

capacitor level reaches V

DD

, the startup

DD-ON

DD

capacitor

before

DD

the auxiliary winding of the main transformer to provide the operating current.

Operating Current

Operating current is around 2.7mA. The low operating current enables better efficiency and reduces the requirement of V

hold-up capacitance.

DD

Green-Mode Operation

The proprietary green-mode function provides an offtime modulation to reduce the switching frequency in the light-load and no-load conditions. The on time is limited for better abnormal or brownout protection. V

,

FB

which is derived from the voltage feedback loop, is taken as the reference. Once V

is lower than the

FB

threshold voltage, switching frequency is continuously decreased to the minimum green-mode frequency of around 22KHz.

Current Sensing / PWM Current Limiting

Peak-current-mode control is utilized to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current sense signal and V When the voltage on SENSE pin reaches around V

=(VFB–0.6)/4, a switch cycle is terminated

COMP

immediately. V

is internally clamped to a variable

COMP

voltage around 0.85V for output power limit.

, the feedback voltage.

FB

Gate Output / Soft Driving

The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A soft driving waveform is implemented to minimize EMI.

Soft-Start

For many applications, it is necessary to minimize the inrush current at startup. The built-in 6ms soft-start circuit significantly reduces the startup current spike and output voltage overshoot.

Built-in Slope Compensation

The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability and prevents sub-harmonic oscillation. SG6742HL/HR inserts a synchronized positive-going ramp at every switching cycle.

Constant Output Power Limit

When the SENSE voltage, across the sense resistor R

, reaches the threshold voltage, around 1V, the

S

output GATE drive is turned off after a small delay, t This delay introduces an additional current proportional to t

• VIN / LP. Since the delay is nearly constant

PD

regardless of the input voltage V

, higher input voltage

IN

results in a larger additional current and the output power limit is higher than under low input line voltage. To compensate this variation for wide AC input range, a sawtooth power-limiter is designed to solve the unequal power-limit problem. The power limiter is designed as a positive ramp signal fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at low-line inputs.

PD

.

Leading-Edge Blanking (LEB)

Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver.

VDD Over-Voltage Protection (OVP)

VDD over-voltage protection has been built in to prevent damage due to abnormal conditions. If the V is over the over-voltage protection voltage (V lasts for t the V

DD

D-VDDOVP

voltage drops below the UVLO, then starts

, the PWM pulses are disabled until

again. Over-voltage conditions are usually caused by

voltage

DD

DD-OVP

) and

open feedback loops.

Under-Voltage Lockout (UVLO)

The turn-on and turn-off thresholds are fixed internally at 15.5V and 9.5V. During startup, the hold-up capacitor must be charged to 15.5V through the startup resistor to enable the IC. The hold-up capacitor continues to supply V auxiliary winding of the main transformer. V drop below 9.5V during this startup process. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply V

before the energy can be delivered from

DD

during startup.

DD

must not

DD

Functional Description (Continued)

SG6742HL/HR — Highly Integrated Green-Mode PWM Controller

Thermal Protection

An NTC thermistor, R can be connected from the RT pin to ground. A constant current I voltage on the RT pin can be expressed as V (R

+ RA), where IRT is 100µA. At high ambient

NTC

temperatures, R When V

RT

off after 20ms (t

NTC

is less than 1.05V (V

D-OTP1

PWM turns off immediately after 130µs (t

, in series with a resistor RA,

NTC

is output from the RT pin. The

RT

= IRT •

RT

is smaller, such that VRT decreases.

), the PWM turns

). If VRT is less than 0.7V (V

RTTH1

D-OTP2

RTTH2

).

),

Limited Power Control

The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than t

, PWM output is turned off. As PWM output is

D-OLP

turned off, V

When V controller is totally shut down. V turn-on threshold voltage of 15.5V through the startup resistor until PWM output is restarted. This protection feature continues as long as the overloading condition persists. This prevents the power supply from overheating due to overloading conditions. When V less than 1.05V (V 20ms (t turned off immediately after 130µs (t

begins decreasing.

DD

goes below the turn-off threshold (~9.5V) the

DD

), the PWM is turned off after

RTTH1

). If VRT is less than 0.7V (V

D-OTP1

is charged up to the

DD

), PWM is

RTTH2

).

D-OTP2

is

RT

Noise Immunity

Noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuousconduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the SG6742HL/HR, and increasing the power MOS gate resistance improve performance.

Applications Information

SG6742HL/HR — Highly Integrated Green-Mode PWM Controller

BOM

F1

CN1

1 2 3

CN1

L1

1 2

3 4

T1

C1

1 2

3 4

R3

U1

1

GND

2

FB

C12

3

NC HV4RT

C2

21

SG6742MR

GATE

VDD

SENSE

VZ1

D4

8

7

6

5

2

BD1

4

C3

21

+

C9

R6

THER1

1

21

+

3

R4

D3

21

R5

C10

43

U2

U3

R1

C5

C4

D2

2 1

23

Q2

1

R7

R8

12

R9

R10

C11

R

R11

A K

T2

4

8

5

6 2

3 7

VO+

C6R2

1

2

3

Q1

21

+

1 2

C7

VO+

L2

21

+

C8

1 2

VO+

L3

D1

3 4

2 1

VO-

Figure 21. 60W Flyback 12V/5A Application Circuit

Designator Part Type Designator Part Type

BD1

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

BD 4A/600V

XC 0.68µF/300V

XC 0.1µF/300V

YC 2200pF/Y1

EC 120µF/400V

CC 0.01µF/500V

CC 1000pF/100V

EC 1000µF/25V

EC 470µF/25V

EC 22µF/50V

CC 47pF/50V

CC 2200pF/50V

CC 0.01µF/50V

D1 Zener Diode 15V 1/2W (option) THER1 Thermistor TTC104

D2 BYV95C T1 10mH

D3 FR103 T2 255µH(PQ2620)

D4 1N4007 U1 IC SG6742

F1 FUSE 4A/250V U2 IC PC817

L1 Inductor (900µH) U3 IC TL431

L2 Inductor (2µH) VZ1 VZ 9G

L3 Inductor (900µH)

Q1 STP20-100CT

Q2 MOS 7A/600V

R1

R2

R3

R4

R5

R6, R9

R7

R8

R10

R11

R 100KΩ 1/2W

R 47Ω 1/4W

R 100KΩ 1/2W

R 4.7Ω 1/8W

R 100Ω 1/8W

R 4.7KΩ 1/8W

R 0.3Ω 2W

R 680Ω 1/8W

R 150KΩ 1/8W

R 39KΩ 1/8W

Physical Dimensions

8

5.00

4.80

3.81

SG6742HL/HR — Highly Integrated Green-Mode PWM Controller

A

0.65

5

B

6.20

5.80

PIN ONE

INDICATOR

(0.33)

1.75 MAX

R0.10

8° 0°

0.90

0.406

1

0.25

0.10

DETAIL A

SCALE: 2:1

4

1.27

0.51

0.33

0.50

0.25

SEATING PLANE

(1.04)

4.00

3.80

CMBA0.25

C

0.10 C

x 45°

GAGE PLANE

0.36

1.75

5.60

1.27

LAND PATTERN RECOMMENDATION

SEE DETAIL A

0.25

0.19

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13

Figure 22. 8-Pin SOP-8 Package

Package drawings are provided as a service to cust omers considering Fairchild components. Drawings may change in any manner without notice. Pl ease note the revision and/or date on t he drawing and contact a Fairchild S emic onductor representative to ver ify or obtain the most recent revis i on. Package specific ations do not expand the terms of Fairc hi l d’s worl dwide terms and conditions, specifically t he warranty therein, which covers Fairchild products .

Always visi t Fai rchild Semiconductor’s online packaging area f or the most recent package drawings :

http://www.fairchildsemi.com/packaging/

.

SG6742HL/HR — Highly Integrated Green-Mode PWM Controller