Datasheet SG6741A Datasheet (Fairchild)

SG6741A Highly Integrated Green-Mode PWM Controller

SG6741A — Highly Integrated Green-Mode PWM Controller

August 2010

Features

 High-Voltage Startup  Low Operating Current: 4mA  Linearly Decreasing PWM Frequency to 18kHz  Frequency Hopping to Reduce EMI Emissions  Peak-Current-Mode Control  Cycle-by-Cycle Current Limiting  Leading-Edge Blanking (LEB)  Synchronized Slope Compensation  GATE Output Maximum Voltage Clamp: 18V  V  V

Over-Voltage Protection (Auto Restart)

DD

Under-Voltage Lockout (UVLO)

DD

 Internal Open-Loop Protection  Constant Power Limit (Full AC Input Range)

Applications

General-purpose switch-mode power supplies and flyback power converters, including:

 Power Adapters  Open-Frame SMPS

Description

The highly integrated SG6741A series of PWM controllers provides several features to enhance the performance of flyback converters.

To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to linearly decrease the switching frequency at light-load conditions. To avoid acoustic-noise problems, the minimum PWM frequency is set above 18KHz. This green-mode function enables the power supply to meet international power conservation requirements. With the internal high-voltage startup circuitry, the power loss due to bleeding resistors is eliminated. To further reduce power consumption, SG6741A is manufactured using the BiCMOS process, which allows an operating current of only 4mA.

SG6741A integrates a frequency-hopping function internally to reduce EMI emission of a power supply with minimum line filters. A built-in synchronized slope compensation achieves stable peak-current-mode control. The proprietary internal line compensation ensures constant output power limit over a wide AC input voltages, from 90V

SG6741A provides many protection functions. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety when an open-loop or output short-circuit failure occurs. PWM output is disabled until V limit, when the controller starts up again. As long as V exceeds ~26V, the internal OVP circuit is triggered.

SG6741A is available in an 8-pin SOP package.

to 264 VAC.

AC

drops below the UVLO lower

DD

Ordering Information

Part Number

SG6741ASY -40 to +105°C 8-Lead Small Outline Package (SOP) Tape & Reel

Operating

Temperature Range

Package Packing Method

Application Diagram

SG6741A — Highly Integrated Green-Mode PWM Controller

Figure 1. Typical Application

Block Diagram

OSC

Generator

Figure 2. Block Diagram

Marking Information

Pin Configuration

ZXYTT 6741A TPM

GND

SG6741A — Highly Integrated Green-Mode PWM Controller

F: Fairchild Logo Z: Plant Code X: 1-Digit Year Code Y: 1-Digit Week Code TT: 2-Digit Die Run Code T: Package Type (S = SOP) P: Y=Green Package M: Manufacture Flow Code

Figure 3. Top Mark

GATE

FB

NC

HV

Figure 4. Pin Configuration

VDD

SENSE

RI

Pin Definitions

Pin # Name Description

1 GND Ground.

Feedback. The signal from the external compensation circuit is fed into this pin. The PWM duty

2 FB

3 NC No Connection.

4 HV Startup Input. For startup, this pin is pulled HIGH to the line input or bulk capacitor via resistors.

5 RI

6 SENSE

7 VDD

8 GATE Driver Output. Totem-pole output driver. Soft driving waveform is implemented for improved EMI.

cycle is determined in response to the signal on this pin and the current-sense signal on SENSE pin.

Reference Setting. A resistor connected from the RI pin to GND pin provides a constant current source, which determines the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26KΩ resistor for R

Current Sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting.

Power Supply. The internal protection circuit disables PWM output as long as V OVP trigger point.

results in a 65kHz center PWM frequency.

I

DD

exceeds the

SG6741A — Highly Integrated Green-Mode PWM Controller

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are given with respect to the ground pin.

Symbol Parameter Min. Max. Unit

V

DC Supply Voltage

VDD

VFB FB Pin Input Voltage -0.3 7.0 V

V

SENSE Pin Input Voltage -0.3 7.0 V

SENSE

VRI RI Pin Input Voltage -0.3 7.0 V

VHV HV Pin Input Voltage 500 V

PD

ΘJA

Power Dissipation

Thermal Resistance (Junction-to-Air) 141

TJ Operating Junction Temperature -40 +125

T

Storage Temperature Range -55 +150

STG

TL Lead Temperature (Wave Soldering or IR, 10 Seconds) +260

ESD

Electrostatic Discharge Capability

Notes:

1. All voltage values, except differential voltages, are given with respect to the network ground terminal.

2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

(1, 2)

30 V

(T

＜50°C)

A

400 mW

°C/W

°C

Human Body Model, JESD22-A114, All Pins Except HV Pin

Machine Model, JESD22-A115, All Pins Except HV Pin

4 kV

200 V

SG6741A — Highly Integrated Green-Mode PWM Controller

Electrical Characteristics

VDD=15V; TA=25C°, unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Units

VDD Section

V

Continuously Operating Voltage 22 V

DD-OP

V

Start Threshold Voltage 15.5 16.5 17.5 V

DD-ON

V

Minimum Operating Voltage 9.5 10.5 11.5 V

DD-OFF

I

Startup Current V

DD-ST

I

Operating Supply Current VDD=15V, GATE Open 4 5 mA

DD-OP

I

Internal Sink Current V

DD-OLP

V

DD-OLP

V

DD-OVP

t

D-VDDOVP

I

VDD Over-Voltage Protection Auto Restart 25 26 27 V

off Voltage

DD-OLP

V

Over-Voltage Protection

DD

Debounce Time

HV Electrical Characteristics

IHV

I

HV-LC

Supply Current Drawn from HV Pin

Leakage Current After Startup

Oscillator Section

f

Frequency in Nominal Mode

OSC

t

Hopping Period 4.4 ms

HOP

f

Green-Mode Frequency 16 18 21 kHz

OSC-G

fDV

fDT

Frequency Variation vs. VDD Deviation

Frequency Variation vs. Temperature Deviation

Feedback Input Section

AV

Input Voltage to Current-Sense Attenuation

ZFB Input Impedance 4 7 kΩ

V

FB Output High Voltage FB Pin Open 5.5 V

FB-OPEN

FB Open-loop Trigger Level 3.7 4.0 4.3 V

FB-OLP

t

D-OLP

V

FB-N

V

FB-G

FB-ZDC

The Delay Time of FB Pin OpenLoop Protection

Green-Mode Entry FB Voltage

Green-Mode Ending FB Voltage

Zero Duty-Cycle Input Voltage 1 V

– 0.16V 30 µA

DD-ON

+0.1V 50 70 90 µA

DD-OLP

6.5 7.5 8.0 V

Auto Restart 100 180 260 µs

VAC=90V, (VDC=120V) V

=10µF

DD

HV=500V, VDD=V

+1V

OFF

DD-

Center Frequency 62 65 68

Hopping Range ±3.7 ±4.2 ±4.7

2 mA

1 20 µA

kHz

VDD=11V to 22V 5 %

TA=-20 to 85°C

5 %

1/3.75 1/3.20 1/2.75 V/V

RI=26kΩ

50 56 62

1.9 2.1 2.3

-

V

FB-N

0.5

V

ms

V

Continued on the following page…

Electrical Characteristics (Continued)

VDD=15V; TA=25C°, unless otherwise noted.

PWM Frequency

f

OSC

f

-

OSC

SG6741A — Highly Integrated Green-Mode PWM Controller

V

FB-ZDC

V

FB-G

V

FB-N

V

FB

Figure 5. PWM Frequency

Symbol Parameter Conditions Min. Typ. Max. Units

Current Sense Section

Z

Input Impedance 12 KΩ

SENSE

V

Current Limit Flatten Threshold Voltage 0.87 0.90 0.93 V

STHFL

V

Current Limit Valley Threshold Voltage V

STHVA

STHFL–VSTHVA

tPD Delay to Output 100 200 ns

t

Leading-Edge Blanking Time 275 350 425 ns

LEB

Gate Section

DCY

V

Maximum Duty Cycle 60 65 70 %

MAX

Gate Low Voltage VDD=15V, IO=50mA 1.5 V

GATE-L

Gate High Voltage VDD=12.5V, IO=-50mA 8 V

GATE-H

tr Gate Rising Time VDD=15V, CL=1nF 150 250 350 ns

tf Gate Falling Time VDD=15V, CL=1nF 30 50 90 ns

I

GATE-SOURCE

V

GATE-CLAMP

DCY

Gate Source Current VDD=15V, GATE=6V 250 mA

Gate Output Clamping Voltage VDD=22V 18 V

Maximum Duty Cycle 60 65 70 %

MAX

0.18 0.22 0.26 V

(°C)

I

(

A )

V

(V)

m

p

C

)

V

(V)

DC

Y

(%)

Typical Performance Characteristics

25

SG6741A — Highly Integrated Green-Mode PWM Controller

5.0

20

15

(µA)

10

DD- ST

I

5

0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature

Figure 6. Startup Current (I

20.0

19.0

18.0

DD -ON

17.0

16.0

15.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Tempe rature ( )

Figure 8. Start Threshold Voltage (V

) vs. Temperature Figure 7. Operating Supply Current (I

DD-ST

°C

DD-ON

vs. Temperature

5.0

)

4.0

3.0

m

2.0

DD- OP

1.0

0.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Tempe ratur e (°C)

vs. Temperature

13.0

12.0

11.0

DD- OFF

10.0

9.0

8.0

-40 -25 -10 5 20 35 50 65 80 95 11 0 125

Te

er ature(°

Figure 9. Minimum Operating Voltage (V

vs. Temperature

10

DD-OP

DD-OFF

)

4.0

3.0

(mA)

HV

I

2.0

1.0

0.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Tem peratur e (° C)

Figure 10. Supply Current Drawn from HV Pin (IHV)

vs. Temperature

70

68

66

(kHz)

OSC

64

f

62

60

-4 0 -25 -10 5 20 35 50 65 80 95 110 125

Tempe ratur e (°C)

Figure 12. Frequency in Nominal Mode (f

OSC

)

vs. Temperature

8

6

(µA)

4

HV-LC

I

2

0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Tempe rature (°C)

Figure 11. Leakage Current After Startup (I

vs. Temperature

70.0

68.0

66.0

MAX

64.0

62.0

60.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Tempe rature (°C )

Figure 13. Maximum Duty Cycle (DCY

MAX

vs. Temperature

HV_LC

)

Functional Description

SG6741A — Highly Integrated Green-Mode PWM Controller

Startup Current

For startup, the HV pin is connected to the line input or bulk capacitor through an external resistor, R

, which

HV

is recommended as 100KΩ. Typical startup current drawn from pin HV is 2mA and charges the hold-up capacitor through the resistor R capacitor level reaches V

DD-ON

switches off. At this moment, the V supplies the SG6741A to maintain V

. When the VDD

HV

, the startup current

capacitor only

DD

before the

DD

auxiliary winding of the main transformer provides the operating current.

Operating Current

Operating current is around 4mA. The low operating current enables a better efficiency and reduces the

requirement of V

hold-up capacitance.

DD

Green-Mode Operation

The proprietary green-mode function provides an offtime modulation to reduce the switching frequency in the light-load and no-load conditions. The on-time is limited for better abnormal or brownout protection. V which is derived from the voltage feedback loop, is taken as the reference. Once V

is lower than the

FB

threshold voltage, switching frequency is continuously decreased to the minimum green-mode frequency around 18KHz (R

=26KΩ).

I

,

FB

Leading-Edge Blanking (LEB)

Each time the power MOSFET is switched on, a turn-on spike occurs on the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate driver.

Under-Voltage Lockout (UVLO)

The turn-on and turn-off thresholds are fixed internally at 16.5V and 10.5V. During startup, the hold-up capacitor must be charged to 16.5V through the startup resistor to enable the IC. The hold-up capacitor continues to supply V

before the energy can be

DD

delivered from auxiliary winding of the main transformer.

must not drop below 10.5V during startup. This

V

DD

UVLO hysteresis window ensures that hold-up capacitor is adequate to supply V

during startup.

DD

Gate Output / Soft Driving

The BiCMOS output stage is a fast totem-pole gate driver. Cross conduction is avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode to protect power MOSFET transistors against undesirable gate over voltage. A soft driving waveform is implemented to minimize EMI.

Oscillator Operation

A resistor connected from the RI pin to the GND pin generates a constant current source for the controller. This current is used to determine the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26KΩ resistor R

results in a

I

corresponding 65KHz PWM frequency. The relationship between R

f

and the switching frequency is:

I

1690

PWM

=

)(K

R

Ω

I

(KHz)

(1)

The range of the PWM oscillation frequency is designed as 47kHz ~ 109kHz.

Current Sensing and PWM Current Limiting

Peak-current-mode control is utilized in SG6741A to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current sense signal and V feedback voltage. When the voltage on the SENSE pin reaches around V terminates immediately. V

= (VFB–1.2)/3.2, a switch cycle

COMP

is internally clamped to a

COMP

variable voltage around 0.85V for output power limit.

FB

, the

Built-in Slope Compensation

The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability or prevents sub-harmonic oscillation. SG6741A inserts a synchronized positive-going ramp at every switching cycle.

Constant Output Power Limit

When the SENSE voltage, across the sense resistor Rs, reaches the threshold voltage, around 0.9V, the output GATE drive is turned off after a small delay, t delay introduces an additional current proportional to t

• VIN / LP. Since the delay is nearly constant, regardless of the input voltage V

higher input voltage results in a

IN,

larger additional current and the output power limit is higher than that under low input line voltage. To compensate this variation for wide AC input range, a sawtooth power-limiter is designed to solve the unequal power-limit problem. The power limiter is designed as a positive ramp signal fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at low-line inputs.

. This

PD

VDD Over-voltage Protection (OVP)

VDD over-voltage protection has been built in to prevent damage due to abnormal conditions. Once the V voltage is over the VDD over-voltage protection voltage (V

) and lasts for t

DD-OVP

disabled until the V

D-VDDOVP

voltage drops below the UVLO,

DD

, the PWM pulses are

then starts again. Over-voltage conditions are usually caused by open feedback loops.

Limited Power Control

The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than

, PWM output is turned off. As PWM output is

t

D-OLP

turned off, the supply voltage V

begins decreasing.

DD

When V the controller is totally shut down. V

goes below the turn-off threshold (~10.5V)

DD

is charged up to

DD

the turn-on threshold voltage of 16V through the startup resistor until PWM output is restarted. This protection feature continues as long as the overloading condition persists. This prevents the power supply from overheating due to overloading conditions.

Noise Immunity

Noise on the current sense or control signal may cause significant pulse-width jitter, particularly in continuousconduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near the SG6741A, and increasing the power MOS gate resistance improve performance.

SG6741A — Highly Integrated Green-Mode PWM Controller

Reference Circuit

CN1

1 2 3

CN1

L1

C1

1 2

3 4

1 2

C12

SG6741A — Highly Integrated Green-Mode PWM Controller

2

T1

3 4

R3

U1

1

GND

2

FB

3

NC HV4RI

C2

SG6741A

GATE

VDD

SENSE

VZ1

8 7 6

R6

5

BD1

4

C3

21

+

C9

1

21

+

3

D3

C10

C4

R4

21

R5

12

43

U2

U3

A K

R1

C5

D2

2 1

23

Q2

1

R7

R8

R9

R10

C11

R

R11

T2

4

8

5

6 2

3 7

VO+

C6R2

1

2

3

Q1

21

+

1 2

C7

VO+

L4

21

L2

+

C8

1 2

VO+

D1

3 4

2 1

VO-

Figure 14. Circuit (12V/5A)

BOM

Reference Component Reference Component

BD1

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

D1

D2

D3

F1

L1

Q1

BD 4A/600V Q2 MOS 7A/600V

XC 0.68µF/300V R1 R 100KΩ 1/2W

XC 0.1µF/300V R2 R 47Ω 1/4W

YC 222pF/Y1 R3 R 100KΩ 1/2W

EC 120µF/400V R4 R 20Ω 1/8W

CC 0.01µF/500V R5 R 100Ω 1/8W

CC 102pF/100V R6 R 33KΩ 1/8W

EC 1000µF/25V R7 R 0.3Ω 2W

EC 470µF/25V R8 R 680Ω m 1/8W

EC 22µF/50V R9 R 4.7KΩ 1/8W

CC 470pF/50V R10 R 150KΩ m 1/8W

CC 222pF/50V R11 R 39KΩ 1/8W

CC 103pF/50V T1 10mH

Zener Diode 15V 1/2W (option) T2 600µH(PQ2620)

BYV95C U1 IC SG6741A

FR103 U2 IC PC817

FUSE 4A/250V U3 IC TL431

900µH VZ1 VZ 9G

STP20-100CT

Physical Dimensions

8

5.00

4.80

3.81

SG6741A — Highly Integrated Green-Mode PWM Controller

A

0.65

5

B

6.20

5.80

PIN ONE

INDICATOR

(0.33)

1.75 MAX

R0.10

8° 0°

0.90

0.406

1

0.25

0.10

DETAIL A

SCALE: 2:1

4

1.27

0.51

0.33

0.50

0.25

SEATING PLANE

(1.04)

4.00

3.80

CMBA0.25

C

0.10 C

x 45°

GAGE PLANE

0.36

1.75

5.60

1.27

LAND PATTERN RECOMMENDATION

SEE DETAIL A

0.25

0.19

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13

Figure 15. 8-Lead Small Outline Package (SOP)

Package drawings are provided as a service to customers c onsidering Fairchild components. Drawings may change in any manner without notice. Pl ease note the revision and/or date on the draw i ng and contact a Fairchild Semiconduct or representative to verify or obtain the most recent revis i on. Package specificat i ons do not expand the terms of Fairchild’s worldw i de t erms and conditions, specifically t he warranty therein, which covers Fairchild products.

Always visi t Fai rchild Semiconductor’s online packaging area for t he most recent package drawings:

http://www.fairchildsemi.com/packaging/

.

SG6741A — Highly Integrated Green-Mode PWM Controller