Datasheet SG2524N, SG2524P, SG3524N, SG3524P Datasheet (SGS Thomson Microelectronics)

SG2524
REGULATING PULSE WIDTH MODULATORS
COMPLETE PWM POWER CONTROL CIR­CUITRY
UNCOMMITTED OUTPUTS FOR SINGLE­ENDED OR PUSH PULLAPPLICATIONS
LOW STANDBY CURRENT8mA TYPICAL OPERATIONUP TO 300KHz 1% MAXIMUM TEMPERATURE VARIATION
OF REFERENCEVOLTAGE
DESCRIPTION
The SG2524, and SG3524 incorporate on a sin­gle monolithic chip all thefunction required for the construction of regulating power suppies inverters or switching regulators.They can also be usedas the control element for high power-outputapplica­tions. The SG3524 family was designed for switching regulators of either polarity, trans­former-coupled dc-to-dc converters, transformer­less voltage doublers and polarityconverter appli­cations employing fixed-frequency, pulse-width modulation techniques. The dual alternating out­puts allows either single-ended or push-pull appli-
SG3524
DIP16 SO16
ORDERING NUMBERS: SG2524N (DIP16)
SG3524N (DIP16) SG2524P (SO16) SG3524P (SO16)
cations. Each device includes an on-ship refer­ence, error amplifier, programmable oscillator, pulse-steering flip flop, two uncommitted output transistors, a high-gain comparator, and current­limiting andshut-down circuitry.
BLOCK DIAGRAM
June 2000
This is advanced information on a new product now in development or undergoingevaluation. Details are subject to change without notice.
1/9
SG2524 - SG3524
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit
V
IN
I
C
I
R
I
T
P
tot
T
stg
T
op
PIN CONNECTION(Top view)
Supply Voltage 40 V Collector Output Current 100 mA Reference Output Current 50 mA Current Through CTTerminal – 5 mA Total Power Dissipation at T
=70°C 1000 mW
amb
Storage Temperature Range – 65 to 150 °C Operating Ambient Temperature Range:
SG2524 SG3524
–25to85
0to70
°C
C
°
THERMAL DATA
Symbol Parameter DIP16 SO16 Unit
R
th j-amb
R
th j-alumina
(*) Thermal resistance junction-alumina with the device soldered onthe middle of an alumina supporting substrate measuring 15 x 20mm;
0.65mm thickness with infiniteheatsink.
Thermal Resistance Junction-ambient Max. Thermal Resistance Junction-alumina (*) Max.
2/9
80
50
°C/W
C/W
°
SG2524- SG3524
ELECTRICAL CHARACTERISTICS (unless otherwise stated, these specifications apply for Tj = -25 to
+85°C for the SG2524, and0 to70°C for the SG3524,V
= 20V, and f = 20KHz).
IN
Symbol Parameter Test Condition
SG2524 SG3524
Min. Typ. Max. Min. Typ. Max.
REFERENCE SECTION
V
VV
Output Voltage 4.8 5 5.2 4.6 5 5.4 V
REF
Line Regulation VIN= 8 to 40V 10 20 10 30 mV
REF
Load Regulation IL= 0 to 20mA 20 50 20 50 mV
REF
Ripple Rejection f = 120Hz, T Short Circuit Current
=0,Tj=25°C 100 100 mA
V
REF
=25°C66 66dB
j
Limit
V
/T Temperature Stability Over Operating
REF
0.3 1 0.3 1 %
Temperature range
V
Long Term Stability Tj = 125°C, t = 1000Hrs 20 20 mV
REF
OSCILLATOR SECTION
f
MAX
f/∆T Temperature Stability Over Operating
Maximum Frequency CT= 0.001µF, RT=2K 300 300 KHz Initial Accuracy R Voltage Stability V
and CTConstant 5 5 %
T
= 8 to 40V, Tj=25°C1 1%
IN
22%
Temperature Range Output Amplitude Pin 3, T Output Pulse Width C
=25°C 3.5 3.5 V
j
= 0.01µF, Tj=25°C 0.5 0.5 µs
T
ERROR AMPLIFIER SECTION
V
G CMV Common Mode Voltage T CMR Common Mode Rejection T
V
Input Offset Voltage VCM= 2.5V 0.5 5 2 10 mV
OS
Input Bias Current 2 10 2 10 µA
I
b
Open Loop Voltage Gain 72 80 60 80 dB
V
=25°C 1.8 3.4 1.8 3.4 V
j
=25°C7070dB
j
B Small Signal Bandwidth A
Output Voltage Tj=25°C 0.5 3.8 0.5 3.8 V
O
= 0dB, Tj=25°C 3 3 MHz
V
COMPARATOR SECTION
Duty-cycle % Each Output On 0 45 0 45 %
V
Input Threshold Zero Duty-cycle 1 1 V
IT
Maximum Duty-cycle 3.5 3.5 V
Input Bias Current 1 1 µA
I
b
CURRENT LIMITING SECTION
Sense Voltage Pin 9 = 2V with Error
190 200 210 180 200 220 mV Amp. Set for Max. Out. T
=25°C
j
Sense Voltage T.C. 0.2 0.2 mV/°C
CMV Common Mode Voltage –1 1 –1 1
OUTPUT SECTION(each output)
Collector-emitter Voltage 40 40 V Collector Leackage Curr. V Saturation Voltage I Emitter Output Voltage V Rise Time RC=2KΩ,Tj=25°C 0.2 0.2
t
r
Fall Time RC=2KΩ,Tj=25°C 0.1 0.1 µs
t
f
(*) Total Standby Current VIN= 40V 8 10 8 10 mA
I
q
(*) Excluding oscillator charging current,error and current limit dividers, and with outputs open.
= 40V 0.1 50 0.1 50 µA
CE
= 50mA 1 2 1 2 V
C
= 20V 17 18 17 18 V
IN
Unit
µ
s
3/9
SG2524 - SG3524
Figure 1:
Figure 3:
Open-loopVoltage Amplificationof
ErrorAmplifier vs. Frequency
OutputDead Time vs. Timing
CapacitanceValue.
Figure2:
Figure4:
OscillatorFrequency vs. Timing
Components.
OutputSaturationVoltagevs. load
Current.
Figure 5:
4/9
OpenLoop Test Circuit.
SG2524- SG3524
PRINCIPLESOF OPERATION
The SG2524/3524 is a fixed frequency pulse­with-modulation voltage regulator control circuit. The regulator operates at a frequency that is pro­grammed by one timing resistor (R ing capacitor (C charging current for C voltage ramp at C
). RTestablished a constant
T
. This results in a linear
T
, which is fed to the compara-
T
) and one tim-
T
tor providing linear control of the output pulse width by the error amplifier. the SG2524/3524 contains, an on-board5V regulatorthat serves as a reference as well as powering the SG2524/3524’s internal control circuitry and is also useful in supplyingexternal support functions. This reference voltage is lowered externally by a resistor divider to provide a reference within the common mode range the error amplifier or an ex­ternal reference may be used. The power supply output is sensed by a second resistor divider net­work to generalea feedbacksignal to error ampli­fier. The amplifier output voltage is then com­pared to the linear voltage ramp at C
. The
T
resulting modulated pulse out of the high-gain comparator is then steered to the appropriate out­put pass transistors (Q
or QB) by the pulse-
A
steering flip-flop, which is synchronously toggled by the oscillator output. The oscillator output pulse also serves as a blanking pulse to assure both output are never on simultaneously during the transition times. The width of the blanking pulse is controlled by the value of C
. Theoutputs
T
may be applied in a push-pull configuration in which their frequencyishalf that of the base oscil­lator, or paralleled for single-ended applicationsin which the frequency is equal to that of the oscilla­tor. The output of the error amplifier shares a common input to the comparator with the current limiting at shutdown circuitry and can be overrid­den by signals from either of these inputs. This common point is also available externally and may be employed to control the gain of, or to compensate, the error amplifier, or to provide ad­ditional controlto the regulator.
RECOMMENDED OPERATING CONDITIONS
Supply voltage V Reference Output Current 0 to 20mA Current trough C Timing Resistor, R Timing Capacitor, C
IN
Terminal - 0.03to -2mA
T
T
T
8 to 40V
1.8 to 100K
0.001 to 0.1µF
TYPICALAPPLICATIONSDATA
OSCILLATOR The oscillator controls the frequency of the
SG2524 and is programmed by R
and CTac-
T
cording to the approximateformula:
1.18
=
f
R
TCT
where:
is in K
R
T
C
is in µF
T
f is in KHz Pratical values of C
0.1µF. Pratical values of R
fall between 0.001 and
T
fall between 1.8 and
T
100KΩ. This results in a frequency rangetypically from 120Hzto to 500KHz.
BLANKING The output pulse of oscillator is used as a blank-
ing pulse at the output. This pulse width is con­trolled by the value of C
.If small values of CTare
T
required for frequency control, the oscillator out­put pulse width may still be increased by applying a shunt capacitance of up to 100pF from pin 3 to ground. If still greater dead-time is required, it should be accomplished by limiting the maximum duty cycle by clamping the output of the error am­plifier. This can easily be done with the circuit be­low:
Figure6.
SYNCRONOUS OPERATION When an external clock is desired, a clock pulse
of approximately 3V can be applied directlyto the oscillator output terminal. The impedance to ground at this point is approximately 2KΩ. In this configuration R
must be selected for a clock
TCT
period slightlygreater than that the external clock. If two more SG2524 regulatorsare to be operated
synchronously, all oscillator output terminals should be tied together, all C
terminals con-
T
nected to a single timing capacitor, and timing re­sistor connected to a single R other R V
REF
tween the C
terminals can be left open or shorted to
T
. Minimum lead lengths should be used be-
terminals.
T
terminal. The
T
5/9
SG2524 - SG3524
Figure 7
: FlybackConverter Circuit.
Figure 8: PUSH-PULLTransformer-coupledcircuit.
6/9
SG2524- SG3524
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.77 1.65 0.030 0.065
b 0.5 0.020
b1 0.25 0.010
D 20 0.787 E 8.5 0.335
e 2.54 0.100
e3 17.78 0.700
F 7.1 0.280
I 5.1 0.201 L 3.3 0.130
Z 1.27 0.050
mm inch
OUTLINE AND
MECHANICAL DATA
DIP16
7/9
SG2524 - SG3524
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 1.75 0.069 a1 0.1 0.25 0.004 0.009 a2 1.6 0.063
b 0.35 0.46 0.014 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.020 c1 45°(typ.)
D (1) 9.8 10 0.386 0.394
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F (1) 3.8 4 0.150 0.157
G 4.6 5.3 0.181 0.209
L 0.4 1.27 0.016 0.050 M 0.62 0.024 S
mm inch
8°(max.)
OUTLINE AND
MECHANICAL DATA
SO16 Narrow
(1)D and F do not include mold flashor protrusions. Moldflashor potrusions shall not exceed0.15mm (.006inch).
8/9
SG2524- SG3524
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