Datasheet SFU9224, SFR9224 Datasheet (Fairchild Semiconductor)

Page 1
Advanced Power MOSFET
SFR/U9224
FEATURES
Avalanche Rugged Technology Rugged Gate Oxide Technology Lower Input Capacitance Improved Gate Charge Extended Safe Operating Area Lower Leakage Current : 10 µA (Max.) @ VDS = -250V Lower R
: 1.65 (Typ.)
DS(ON)
Absolute Maximum Ratings
Characteristic Value UnitsSymbol
Drain-to-Source Voltage Continuous Drain Current (T Continuous Drain Current (T
=25oC)
C
=100oC)
C
Drain Current-Pulsed Gate-to-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Total Power Dissipation (T Total Power Dissipation (T
=25oC)
A
=25oC)
C
*
Linear Derating Factor Operating Junction and Storage Temperature Range Maximum Lead Temp. for Soldering Purposes, 1/8 “ from case for 5-seconds
T
V
DSS
I
I
DM
V E
I
AR
E
dv/dt
P
, T
J
T
D
GS
AS
AR
D
STG
L
O O
O O O
BV R I
1
1. Gate 2. Drain 3. Source
-250
-2.5
-1.5
1
2
1 1
3
-10
+
_
156
-2.5
3.0
-4.8
2.5 30
0.24
30
= -250 V
DSS
= 2.4
DS(on)
= -2.5 A
D
D-PAK
2
3
I-PAK
1
2
3
V A A
V
mJ
A
mJ
V/ns
W W
W/
o
C
- 55 to +150
o
C
300
Thermal Resistance
Characteristic Max. UnitsSymbol Typ.
R
θJC
R
θJA
R
θJA
*
When mounted on the minimum pad size recommended (PCB Mount).
©1999 Fairchi ld Semiconduc tor Corpor ation
Junction-to-Case Junction-to-Ambient Junction-to-Ambient
*
--
--
--
4.17 50
110
o
C/W
Rev. B
Page 2
SFR/U9224
P-CHANNEL
POWER MOSFET
Electrical Characteristics (T
CharacteristicSymbol
BV BV/∆T V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
C
C
C
t
d(on)
t
d(off)
Q Q Q
Drain-Source Breakdown Voltage
DSS
Breakdown Voltage Temp. Coeff.
J
Gate Threshold Voltage Gate-Source Leakage , Forward Gate-Source Leakage , Reverse
Drain-to-Source Leakage Current
Static Drain-Source On-State Resistance Forward Transconductance
fs
Input Capacitance
iss
Output Capacitance
oss
Reverse Transfer Capacitance
rss
Turn-On Delay Time
t
Rise Time
r
Turn-Off Delay Time
t
Fall Time
f
Total Gate Charge
g
Gate-Source Charge
gs
Gate-Drain( “ Miller “ ) Charge
gd
=25oC unless otherwise specified)
C
Max. UnitsTyp.Min. Test Condition
V
-250
--
-2.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-0.22
--
--
--
--
--
--
1.9
415
65 24 11 19 34 15 16
3.3
7.8
-4.0
-100 100
-100
--
--
-10
2.4
--
540
95 35 30 50 80 40 20
--
--
V
GS
o
I
V/
nA
µA
nC
=-250µA See Fig 7
C
D
V
V
DS
V
GS
V
GS
V
DS
V
DS
V
GS
V
DS
V
GS
pF
ns
See Fig 5
V
DD
=18
R
G
V
DS
I
=-2.7A
D
See Fig 6 & Fig 12
=0V,ID=-250µA
=-5V,ID=-250µA =-30V =30V =-250V =-200V,TC=125oC
=-10V,ID=-1.3A =-40V,ID=-1.3A
O O
4
4
=0V,VDS=-25V,f =1MHz
=-125V,ID=-2.7A,
See Fig 13
O
4
O
=-200V,VGS=-10V,
4
O
O
5
5
Source-Drain Diode Ratings and Characteristics
CharacteristicSymbol Max. UnitsTyp.Min. Test Condition
I
I
SM
V
t
Q
Notes ;
Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature
1
O
2
L=40mH, I
O
3
I
O
SD
Pulse Test : Pulse Width = 250µs, Duty Cycle 2%
4
O
Essentially Independent of Operating Temperature
5
O
Continuous Source Current
S
Pulsed-Source Current Diode Forward Voltage
SD
Reverse Recovery Time
rr
Reverse Recovery Charge
rr
=-2.5A, VDD=-50V, RG=27Ω*, Starting TJ =25oC
AS
_
-2.7A, di/dt 300A/µs, VDDBV
_
<
<
_
<
DSS
1
O
4
O
, Starting TJ =25oC
_
<
--
--
--
140
0.7
-2.5
-10
-5.0
--
--
--
--
--
--
--
Integral reverse pn-diode
A
in the MOSFET
V
T
=25oC,IS=-2.4A,VGS=0V
J
ns
T
=25oC,IF=-2.7A
J
µC
/dt=100A/µs
di
F
O
4
Page 3
P-CHANNEL
POWER MOSFET
SFR/U9224
1
Fig 1. Output Characteristics Fig 2. Transfer Characteristics
10
V
GS
Top : - 15 V
- 10 V
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
0
- 5.0 V
10
Bottom : - 4.5 V
, Drain Current [A]
D
-I
-1
10
-1
10
-VDS , Drain-Source Voltage [V]
6
5
]
4
, [
DS(on)
R
3
V
GS
2
Drain-Source On-Resistance
1
0
0 2 4 6 8 10
-I
@ Notes :
1. 250
s Pulse Test
µ
2. T
= 25 oC
C
0
10
= -10 V
VGS = -20 V
, Drain Current [A]
D
1
10
@ Note : TJ = 25 oC
1
10
0
10
, Drain Current [A]
D
-I
-1
10
2 4 6 8 10
25 oC
150
o
C
@ Notes :
= 0 V
1. V
GS
2. V
= -40 V
DS
3. 250
s Pulse Test
- 55
o
C
µ
-VGS , Gate-Source Voltage [V]
Fig 4. Source-Drain Diode Forward VoltageFig 3. On-Resistance vs. Drain Current
1
10
0
10
150 oC
@ Notes :
= 0 V
1. V
, Reverse Drain Current [A]
DR
-I
-1
10
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
o
C
25
-VSD , Source-Drain Voltage [V]
2. 250
GS
s Pulse Test
µ
800
C
600
400
Capacitance [pF]
200
iss
C
oss
C
rss
0
0
10
-VDS , Drain-Source Voltage [V]
C
= Cgs+ Cgd ( Cds= shorted )
iss
C
= Cds+ C
oss
gd
C
= C
rss
gd
@ Notes :
1. V
2. f = 1 MHz
1
10
GS
= 0 V
Fig 6. Gate Charge vs. Gate-Source VoltageFig 5. Capacitance vs. Drain-Source Voltage
= -50 V
V
DS
= -125 V
10
V
DS
VDS = -200 V
5
, Gate-Source Voltage [V]
GS
-V
0
0 3 6 9 12 15 18
@ Notes : ID =-2.7 A
QG , Total Gate Charge [nC]
Page 4
SFR/U9224
Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature
1.2
1.1
3.0
2.5
2.0
POWER MOSFET
P-CHANNEL
1.0
, (Normalized)
DSS
-BV
0.9
Drain-Source Breakdown Voltage
0.8
-75 -50 -25 0 25 50 75 100 125 150 175
@ Notes :
1. V
2. I
TJ , Junction Temperature [oC]
Operation in This Area is Limited by R
1
10
0
10
, Drain Current [A]
D
-I
-1
10
-2
10
10
0
@ Notes :
1. T
2. T
3. Single Pulse
= 25 oC
C
= 150 oC
J
DS(on)
10
1 ms
10 ms
DC
1
10
-VDS , Drain-Source Voltage [V]
= 0 V
GS
= -250 µA
D
0.1 ms
2
1.5
, (Normalized)
1.0
DS(on)
R
0.5
Drain-Source On-Resistance
0.0
-75 -50 -25 0 25 50 75 100 125 150 175
@ Notes :
1. V
2. I
TJ , Junction Temperature [oC]
Fig 10. Max. Drain Current vs. Case TemperatureFig 9. Max. Safe Operating Area
3.0
2.5
2.0
1.5
1.0
, Drain Current [A]
D
0.5
-I
0.0 25 50 75 100 125 150
Tc , Case Temperature [oC]
= -10 V
GS
= -1.4 A
D
D=0.5
0
10
0.2
0.1
0.05
0.02
-1
0.01
10
(t) , Thermal Response
JC
θ
Z
-5
10
single pulse
-4
10
t1 , Square Wave Pulse Duration [sec]
Fig 11. Thermal Response
@ Notes :
1. Z
2. Duty Factor, D=t
3. TJM-TC=PDM*Z
P
DM.
-3
10
-2
10
10
(t)=4.17 oC/W Max.
JC
θ
t
1.
t
2.
-1
1/t2
(t)
JC
θ
0
10
1
10
Page 5
P-CHANNEL
POWER MOSFET
SFR/U9224
Fig 12. Gate Charge Test Circuit & Waveform
-10V
“ Current Regulator
200nF12V
-3mA
V
R
G
50K
300nF
V
GS
R
1
Current Sampling (IG)
Resistor
Fig 13. Resistive Switching Test Circuit & Waveforms
V
out
in
DUT
Same Type
as DUT
DUT
R
2
Current Sampling (ID)
Resistor
R
L
V
DD
( 0.5 rated V
V
GS
Q
-10V
V
DS
Q
gs
g
Q
gd
Charge
t
on
t
d(on)tr
)
DS
V
in
10%
90%
V
out
t
off
t
f
t
d(off)
Vary tp to obtain required peak I
-10V
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
BV
L
V
DS
D
R
G
L
I
D
V
DD
C
V
DD
E
= LL I
AS
----
1 2
2
AS
t
p
(t)
I
D
DSS
-------------------­BV
-- V
DSS
DD
Time
V
(t)
DS
DUT
I
AS
t
p
BV
DSS
Page 6
SFR/U9224
Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
P-CHANNEL
POWER MOSFET
+
V
DS
--
I
S
L
V
GS
( Driver )
I
S
( DUT )
V
DS
( DUT )
V
GS
V
GS
Driver
R
G
D =
IFM , Body Diode Forward Current
Compliment of DUT
Gate Pulse Width
-------------------------­Gate Pulse Period
Body Diode
Forward Voltage Drop
(N-Channel)
• dv/dt controlled by “RG”
• I
controlled by Duty Factor “D”
S
Body Diode Reverse Current
I
RM
V
f
di/dt
V
DD
10V
V
DD
Body Diode Recovery dv/dt
Page 7
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx™ CoolFET™ CROSSVOLT™ E2CMOS
TM
FACT™ FACT Quiet Series™
®
FAST FASTr™ GTO™ HiSeC™
ISOPLANAR™ MICROWIRE™ POP™ PowerTrench™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 TinyLogic™
UHC™ VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
PRODUCT STA TUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
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