Avalanche Rugged Technology
Rugged Gate Oxide Technology
Lower Input Capacitance
Improved Gate Charge
Extended Safe Operating Area
Lower Leakage Current : 10 µA (Max.) @ VDS = -250V
Lower R
: 1.65 Ω (Typ.)
DS(ON)
Absolute Maximum Ratings
CharacteristicValueUnitsSymbol
Drain-to-Source Voltage
Continuous Drain Current (T
Continuous Drain Current (T
=25oC)
C
=100oC)
C
Drain Current-Pulsed
Gate-to-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation (T
Total Power Dissipation (T
=25oC)
A
=25oC)
C
*
Linear Derating Factor
Operating Junction and
Storage Temperature Range
Maximum Lead Temp. for Soldering
Purposes, 1/8 “ from case for 5-seconds
T
V
DSS
I
I
DM
V
E
I
AR
E
dv/dt
P
, T
J
T
D
GS
AS
AR
D
STG
L
O
O
O
O
O
BV
R
I
1
1. Gate 2. Drain 3. Source
-250
-2.5
-1.5
1
2
1
1
3
-10
+
_
156
-2.5
3.0
-4.8
2.5
30
0.24
30
= -250 V
DSS
= 2.4 Ω
DS(on)
= -2.5 A
D
D-PAK
2
3
I-PAK
1
2
3
V
A
A
V
mJ
A
mJ
V/ns
W
W
W/
o
C
- 55 to +150
o
C
300
Thermal Resistance
CharacteristicMax.UnitsSymbolTyp.
R
θJC
R
θJA
R
θJA
*
When mounted on the minimum pad size recommended (PCB Mount).
Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature
1
O
2
L=40mH, I
O
3
I
O
SD
Pulse Test : Pulse Width = 250µs, Duty Cycle 2%
4
O
Essentially Independent of Operating Temperature
5
O
Continuous Source Current
S
Pulsed-Source Current
Diode Forward Voltage
SD
Reverse Recovery Time
rr
Reverse Recovery Charge
rr
=-2.5A, VDD=-50V, RG=27Ω*, Starting TJ =25oC
AS
_
-2.7A, di/dt 300A/µs, VDDBV
_
<
<
_
<
DSS
1
O
4
O
, Starting TJ =25oC
_
<
--
--
--
140
0.7
-2.5
-10
-5.0
--
--
--
--
--
--
--
Integral reverse pn-diode
A
in the MOSFET
V
T
=25oC,IS=-2.4A,VGS=0V
J
ns
T
=25oC,IF=-2.7A
J
µC
/dt=100A/µs
di
F
O
4
Page 3
P-CHANNEL
POWER MOSFET
SFR/U9224
1
Fig 1. Output CharacteristicsFig 2. Transfer Characteristics
10
V
GS
Top : - 15 V
- 10 V
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
0
- 5.0 V
10
Bottom : - 4.5 V
, Drain Current [A]
D
-I
-1
10
-1
10
-VDS , Drain-Source Voltage [V]
6
5
]
Ω
4
, [
DS(on)
R
3
V
GS
2
Drain-Source On-Resistance
1
0
0246810
-I
@ Notes :
1. 250
s Pulse Test
µ
2. T
= 25 oC
C
0
10
= -10 V
VGS = -20 V
, Drain Current [A]
D
1
10
@ Note : TJ = 25 oC
1
10
0
10
, Drain Current [A]
D
-I
-1
10
246810
25 oC
150
o
C
@ Notes :
= 0 V
1. V
GS
2. V
= -40 V
DS
3. 250
s Pulse Test
- 55
o
C
µ
-VGS , Gate-Source Voltage [V]
Fig 4. Source-Drain Diode Forward VoltageFig 3. On-Resistance vs. Drain Current
1
10
0
10
150 oC
@ Notes :
= 0 V
1. V
, Reverse Drain Current [A]
DR
-I
-1
10
0.51.01.52.02.53.03.54.0
o
C
25
-VSD , Source-Drain Voltage [V]
2. 250
GS
s Pulse Test
µ
800
C
600
400
Capacitance [pF]
200
iss
C
oss
C
rss
0
0
10
-VDS , Drain-Source Voltage [V]
C
= Cgs+ Cgd ( Cds= shorted )
iss
C
= Cds+ C
oss
gd
C
= C
rss
gd
@ Notes :
1. V
2. f = 1 MHz
1
10
GS
= 0 V
Fig 6. Gate Charge vs. Gate-Source VoltageFig 5. Capacitance vs. Drain-Source Voltage
= -50 V
V
DS
= -125 V
10
V
DS
VDS = -200 V
5
, Gate-Source Voltage [V]
GS
-V
0
0369121518
@ Notes : ID =-2.7 A
QG , Total Gate Charge [nC]
Page 4
SFR/U9224
Fig 7. Breakdown Voltage vs. TemperatureFig 8. On-Resistance vs. Temperature
1.2
1.1
3.0
2.5
2.0
POWER MOSFET
P-CHANNEL
1.0
, (Normalized)
DSS
-BV
0.9
Drain-Source Breakdown Voltage
0.8
-75-50-250255075100125150175
@ Notes :
1. V
2. I
TJ , Junction Temperature [oC]
Operation in This Area
is Limited by R
1
10
0
10
, Drain Current [A]
D
-I
-1
10
-2
10
10
0
@ Notes :
1. T
2. T
3. Single Pulse
= 25 oC
C
= 150 oC
J
DS(on)
10
1 ms
10 ms
DC
1
10
-VDS , Drain-Source Voltage [V]
= 0 V
GS
= -250 µA
D
0.1 ms
2
1.5
, (Normalized)
1.0
DS(on)
R
0.5
Drain-Source On-Resistance
0.0
-75-50-250255075100125150175
@ Notes :
1. V
2. I
TJ , Junction Temperature [oC]
Fig 10. Max. Drain Current vs. Case TemperatureFig 9. Max. Safe Operating Area
3.0
2.5
2.0
1.5
1.0
, Drain Current [A]
D
0.5
-I
0.0
255075100125150
Tc , Case Temperature [oC]
= -10 V
GS
= -1.4 A
D
D=0.5
0
10
0.2
0.1
0.05
0.02
-1
0.01
10
(t) , Thermal Response
JC
θ
Z
-5
10
single pulse
-4
10
t1 , Square Wave Pulse Duration [sec]
Fig 11. Thermal Response
@ Notes :
1. Z
2. Duty Factor, D=t
3. TJM-TC=PDM*Z
P
DM.
-3
10
-2
10
10
(t)=4.17 oC/W Max.
JC
θ
t
1.
t
2.
-1
1/t2
(t)
JC
θ
0
10
1
10
Page 5
P-CHANNEL
POWER MOSFET
SFR/U9224
Fig 12. Gate Charge Test Circuit & Waveform
-10V
“ Current Regulator
200nF12V
-3mA
V
R
G
”
50KΩ
300nF
V
GS
R
1
Current Sampling (IG)
Resistor
Fig 13. Resistive Switching Test Circuit & Waveforms
V
out
in
DUT
Same Type
as DUT
DUT
R
2
Current Sampling (ID)
Resistor
R
L
V
DD
( 0.5 rated V
V
GS
Q
-10V
V
DS
Q
gs
g
Q
gd
Charge
t
on
t
d(on)tr
)
DS
V
in
10%
90%
V
out
t
off
t
f
t
d(off)
Vary tp to obtain
required peak I
-10V
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
BV
L
V
DS
D
R
G
L
I
D
V
DD
C
V
DD
E
=LL I
AS
----
1
2
2
AS
t
p
(t)
I
D
DSS
-------------------BV
-- V
DSS
DD
Time
V
(t)
DS
DUT
I
AS
t
p
BV
DSS
Page 6
SFR/U9224
Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
P-CHANNEL
POWER MOSFET
+
V
DS
--
I
S
L
V
GS
( Driver )
I
S
( DUT )
V
DS
( DUT )
V
GS
V
GS
Driver
R
G
D =
IFM , Body Diode Forward Current
Compliment of DUT
Gate Pulse Width
-------------------------Gate Pulse Period
Body Diode
Forward Voltage Drop
(N-Channel)
• dv/dt controlled by “RG”
• I
controlled by Duty Factor “D”
S
Body Diode Reverse Current
I
RM
V
f
di/dt
V
DD
10V
V
DD
Body Diode Recovery dv/dt
Page 7
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PRODUCT STA TUS DEFINITIONS
Definition of Terms
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Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or
In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
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that has been discontinued by Fairchild semiconductor.
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