n Avalanche Rugged Technology
n Rugged Gate Oxide Technology
n Lower Input Capacitance
n Improved Gate Charge
n Extended Safe Operating Area
n Lower Leakage Current : 10 µA(Max.) @ V
n Lower R
: 0.912 Ω (Typ.)
DS(ON)
Absolute Maximum Ratings
CharacteristicValueUnitsSymbol
Drain-to-Source Voltage
Continuous Drain Current (T
Continuous Drain Current (T
=25oC)
C
=100oC)
C
Drain Current-Pulsed
Gate-to-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation (T
Total Power Dissipation (T
=25oC)
A
=25oC)
C
Linear Derating Factor
Operating Junction and
Storage Temperature Range
Maximum Lead Temp. for Soldering
Purposes, 1/8” from case for 5-seconds
T
V
DSS
I
I
DM
V
E
I
AR
E
dv/dt
P
, T
J
T
D
GS
AS
AR
D
STG
L
= -100V
DS
*
O
O
O
O
O
BV
R
DS(on)
DSS
= -100 V
= 1.2 Ω
ID= -2.8 A
D-PAK
1
3
1. Gate 2. Drain 3. Source
-100
-2.8
-2.0
1
2
1
1
3
11
±30
52
-2.8
2.0
-6.5
2.5
20
0.16
- 55 to +150
300
I-PAK
2
1
2
3
V
A
A
V
mJ
A
mJ
V/ns
W
W
o
W/
C
o
C
Thermal Resistance
CharacteristicMax.UnitsSymbolTyp.
R
θJC
R
θJA
R
θJA
When mounted on the mi nimum pad size recommended (PCB Mount).
Repetitive Rating : Pulse Wi dt h Limi t ed by Maximum Junction Temperature
O
2
L=10.0mH, I
O
3
I
O
SD
4
Pulse Test : Pulse Width = 250µs, Duty Cycle 2%
O
5
Essentially Independent of Operating Temperature
O
Continuous Source Current
S
Pulsed-Source Current
Diode Forward Voltage
SD
Reverse Recovery Time
rr
Reverse Recovery Charge
rr
=-2.8A, VDD=-25V, RG=27Ω*, Starting TJ =25oC
AS
_
<
-3.6A, di/dt300A/µs, V
_
<
DD
--
1
O
4
O
_
<
BV
, Starting TJ =25oC
DSS
_
<
--
--
--
-100
--
0.35
--
-11
-3.8
--
--
A
V
ns
µC
-2.8
--
Integral reverse pn-diode
in the MOSFET
T
=25oC,IS=-2.8A,VGS=0V
J
T
=25oC,IF=-3.6A
J
di
/dt=100A/µs
F
O
4
Page 3
P-CHANNEL
POWER MOSFET
Fig 1. Output CharacteristicsFig 2. Transfer Characteristics
1
V
GS
Top : - 1 5 V
- 1 0 V
- 8.0 V
- 7.0 V
- 6.0 V
- 5.5 V
- 5.0 V
Bo tto m : - 4 .5 V
@ Notes :
1. 250 µs Pulse Test
2. TC = 25 oC
-1
0
10
10
-VDS , Drain-Source Voltage [V]
VGS = -10 V
VGS = -20 V
@ Note : TJ = 25 oC
02468101214
-ID , Drain Current [A ]
, Drain Current [A ]
-I
]
Ω
, [
DS(on)
R
10
0
10
D
-1
10
10
5
4
3
2
Drain-Source On-Resistance
1
0
SFR/U9110
1
10
0
10
, Drain Current [A ]
D
-I
-1
1
10
10
10
, Reverse Drain C urrent [A]
DR
-I
-1
10
150 oC
25 oC
- 55 oC
@ Notes :
1. V
2. V
3. 250
= 0 V
GS
= -40 V
DS
s Pulse Test
µ
246810
-VGS , Gate-Source Vo ltage [V]
Fig 4. Source-Drain Diode Forward VoltageFig 3. On-Resistance vs. Drain Current
1
0
150 oC
@ Notes :
= 0 V
1. V
25 oC
2. 250
GS
s Pulse Test
µ
0.51.01.52.02.53. 03.54.0
-VSD , Source-Drain Voltage [V]
500
400
C
iss
300
200
C
Capacitance [pF]
100
oss
C
rss
0
0
10
-VDS , Drain-Source Voltage [V]
C
= Cgs+ Cgd ( Cds= shorted )
iss
= Cds+ C
C
oss
gd
C
= C
rss
gd
@ Notes :
1. V
2. f = 1 MHz
1
10
GS
= 0 V
10
VDS = -20 V
VDS = -50 V
VDS = -80 V
5
, Gate-Source Vo ltage [V]
GS
-V
0
0246810
QG , Total Gate Char ge [nC]
@ Notes : ID =-3.6 A
Fig 6. Gate Charge vs. Gate-Source VoltageFig 5. Capacitance vs. Drain-Source Voltage
Page 4
SFR/U9110
Fig 7. Breakdown Voltage vs. TemperatureFig 8. On-Resistance vs. Temperature
1.2
2.5
POWER MOSFET
P-CHANNEL
1.1
1.0
, (Normalized)
DSS
-BV
0.9
Drain-Source Breakdown Voltage
0.8
-75-50-250255075100125150175
@ Notes :
1. V
2. I
TJ , Junction Temperature [oC]
Operation in This Area
is Limited by R
1
10
DS(on)
0.1 ms
1 ms
, Drain Current [A ]
0
D
10
-I
10
-1
0
10
@ Notes :
1. T
= 25 oC
C
= 150 oC
2. T
J
3. Single Pul se
10
10 ms
DC
1
-VDS , Drain-Source Voltage [V]
= 0 V
GS
= -250 µA
D
10
2.0
1.5
1.0
, (Normalized)
DS(on)
R
0.5
Drain-Source On-Resistance
0.0
-75-50-250255075100125150175
@ Notes :
1. V
2. I
= -10 V
GS
= -1.8 A
D
TJ , Junction Temperature [oC]
Fig 10. Max. Drain Current vs. Case TemperatureFig 9. Max. Safe Operating Area
3.5
3.0
2.5
2.0
1.5
1.0
, Drain Current [A ]
D
I
0.5
2
0.0
255075100125150
Tc , Case Temperature [oC]
1
10
D=0.5
0.2
0
10
0.1
0.05
0.02
0.01
(t) , Thermal Response
-1
JC
10
θ
Z
-5
10
single pulse
-4
10
-3
10
10
@ Notes :
1. Z
2. Duty Factor, D=t1/t
3. TJM-TC=PDM*Z
-2
JC
θ
P
DM
.
-1
10
(t)=6.25 oC/W Max.
2
(t)
JC
θ
t
1.
t
2.
0
10
1
10
t1 , Square Wave Pulse Durati on [sec]
Fig 11. Thermal Response
Page 5
P-CHANNEL
POWER MOSFET
SFR/U9110
Fig 12. Gate Charge Test Circuit & Waveform
12V
-10V
“ Current Regulator
200nF
-3mA
V
R
G
”
Ω
50K
300nF
V
GS
R
1
Current Sampling (IG)
Resistor
Fig 13. Resistive Switching Test Circuit & Waveforms
V
out
in
DUT
Same Type
as DUT
DUT
R
2
Current Sampling (ID)
Resistor
R
L
V
DD
( 0.5 rated V
V
GS
Q
-10V
V
DS
Q
gs
g
Q
gd
Charge
t
on
t
d(on)tr
)
DS
V
in
10%
90%
V
out
t
d(off)
t
off
t
f
Vary tpto obtain
required peak I
-10V
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
BV
L
V
DS
D
R
G
L
I
D
V
DD
C
V
DD
E
=LL I
AS
----
1
2
2
AS
t
p
I
(t)
D
DSS
-------------------BV
DSS
-- V
DD
Time
V
(t)
DS
DUT
I
AS
t
p
BV
DSS
Page 6
SFR/U9110
Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
P-CHANNEL
POWER MOSFET
+
V
DS
--
I
S
L
V
GS
( Driver )
I
S
( DUT )
V
DS
( DUT )
V
GS
V
GS
Driver
R
G
D =
IFM, Body Diode Forward Current
Comp liment of DU T
Gate Pulse Width
-------------------------Gate Pulse Period
Body Diode
Forward Voltage Drop
(N-Channel)
• dv/dt controlled by “RG”
•I
controlled by Duty Factor “D”
S
Body Diode Reverse Current
I
RM
V
f
di/dt
V
DD
10V
V
DD
Body Diode Recovery dv/dt
Page 7
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet IdentificationProduct StatusDefinition
Advance Information
Preliminary
No Identification Needed
Formative or
In Design
First Production
Full Production
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I1
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