Datasheet SFP9640L Datasheet (Fairchild Semiconductor)

Page 1
Advanced Power MOSFET
SFP9640L
FEATURES
Avalanche Rugged TechnologyRugged Gate Oxide Technology Lower Input CapacitancesImproved Gate ChargeExtended Safe Operating AreaLower Leakage Current : -10uA (Max.) @ VLower R
: 0.383 Ω (Typ.)
DS(ON)
Absolute Maximum Ratings
Characteristic Value UnitsSymbol
Drain-to-Source Voltage Continuous Drain Current (T Continuous Drain Current (T Drain Current-Pulsed Gate-to-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Total Power Dissipation (TC=25℃) Linear Derating Factor Operating Junction and Storage Temperature Range Maximum Lead Temp. for Soldering Purposes, 1/8from case for 5-seconds
T
V
DSS
I
I
DM
V E
I
AR
E
dv/dt
P
, T
J
T
D
GS AS
AR
D
STG
L
= -200V
DS
=25℃)
C
=100℃)
C
BV
DSS
R
DS(on)
ID= -11 A
TO-220
1
2
3
1.Gate 2. Drain 3. Source
-200
-11
-7.5
-44
±20
806
-11
9.8
-5.0 98
0.78
- 55 to +150
300
= -200 V
= 0.5Ω
V A A
V
mJ
A
mJ
V/ns
W
W/
Thermal Resistance
R
θJC
R
θCS
R
θJA
Characteristic Max. UnitsSymbol Typ.
Junction-to-Case
Case-to-Sink
Junction-to-Ambient
--
0.5
--
1.27
--
62.5
/W
Rev. A
Page 2
SFP9640L
N-CHANNEL
POWER MOSFET
Electrical Characteristics
CharacteristicSymbol
BV
ΔBV/ΔT
V
GS(th)
I
GSS
I
DSS
R
DS(on)
g
C
C
C
t
d(on)
t
d(off)
Q Q Q
Drain-Source Breakdown Voltage
DSS
Breakdown Voltage Temp. Coeff.
J
Gate Threshold Voltage Gate-Source Leakage , Forward Gate-Source Leakage , Reverse
Drain-to-Source Leakage Current
Static Drain-Source On-State Resistance Forward Transconductance
fs
Input Capacitance
iss
Output Capacitance
oss
Reverse Transfer Capacitance
rss
Turn-On Delay Time
t
Rise Time
r
Turn-Off Delay Time
t
Fall Time
f
Total Gate Charge
g
Gate-Source Charge
gs
Gate-Drain(Miller) Charge
gd
(TC=25℃unless otherwise specified)
Max. UnitsTyp.Min. Test Condition
V
-200
--
-1.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-0.16
--
--
--
--
--
--
5.47
1220
207
81 16 23 54 19 46
9.2
22.9
--
--
-2.0
-100 100
-10
-100
0.5
--
1585
310 120
40 55
115
50 59
--
--
V
V/
V
nA
μA
S
pF
ns
nC
=0V,ID=-250μA
GS
I
=-250μA See Fig 7
D
V
=-5V,ID=-250μA
DS
V
=-20V
GS
V
=20V
GS
VDS=-200V V
=-160V,TC=125
DS
=-5V,ID=-5.5A
V
GS
VDS=-40V,ID=-5.5A VGS=0V,VDS=-25V,f =1MHz
VDD=-100V,ID=-11A, R
=4.6
G
VDS=-160V,VGS=-5V, I
=-11A
D
See Fig 6 & Fig 12
See Fig 5
See Fig 13
④⑤
④⑤
Source-Drain Diode Ratings and Characteristics
CharacteristicSymbol Max. UnitsTyp.Min. Test Condition
I
I
SM
V
t
Q
Notes ;
Repetitive Rating : Pulse Wi dth Lim i ted by Maximum Junction TemperatureL=3mH, II
Pulse Test : Pulse Width = 250μs, Duty Cycl e 2%Essentially Independent of Operating Temperature
Continuous Source Current
S
Pulsed-Source Current Diode Forward Voltage
SD
Reverse Recovery Time
rr
Reverse Recovery Charge
rr
=-11A, VDD=-50V, RG=27Ω, Starting TJ =25
AS
-11A, di/dt100A/μs, VDD≤BV
SD
, Starting TJ =25
DSS
--
--
--
--
-­205
--
1.45
--
-44
-5.0
--
--
A
V
ns
μC
-11
--
Integral reverse pn-diode in the MOSFET T
=25,IS=-11A,VGS=0V
J
T
=25,IF=-11A
J
di
/dt=100A/μs
F
Page 3
P-CHANNEL
POWER MOSFET
Fig 1. Output Characteristics Fig 2. Transfer Characteristics
V
GS
To p : 1 5 V 1 0 V
1
8 .0 V
10
7 .0 V 6 .0 V 5 .5 V 5 .0 V Bo ttom : 4.5 V
0
10
, Drain Current [ A]
D
I
-1
10
-1
10
VDS , Drain-Source Vol tage [V]
@ Notes :
1. 250 µs Pulse Test
2. TC = 25 oC
0
10
SFP9640L
1
10
150 oC
0
10
25 oC
, Drain Current [A]
D
-I
-1
1
10
10
246810
- 55 oC
-VGS , Gate-Source Voltage [V]
@ Notes :
1. V
2. V
3. 250
= 0 V
GS
= 30 V
DS
s Pulse Test
µ
1.0
0.8
]
0.6
VGS = -5 V
, [
DS(on)
0.4
R
Drain-Source On-Res istance
0.2
VGS =-10 V
@ Note : TJ = 25 oC
0.0 0 5 10 15 20 25 30
ID , Drain Current [ A]
Capacitance [pF]
4000
3000
2000
1000
0
0
10
C
= Cgs+ Cgd ( Cds= shorted )
iss
= Cds+ C
C
oss
gd
C
= C
rss
gd
C
iss
@ Notes :
1
10
1. V
2. f = 1 MHz
C
oss
C
rss
-VDS , Drain-Source Voltag e [V]
GS
= 0 V
Fig 4. Source-Drain Diode Forward VoltageFig 3. On-Resistance vs. Drain Current
1
10
0
10
150 oC
, Reverse Drain Curre nt [A]
DR
-I
-1
10
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
25 oC
@ Notes :
1. V
2. 250
GS
= 0 V
µ
s Pulse Test
-VSD , Source-Drain Voltag e [V]
Fig 6. Gate Charge vs. Gate-Source VoltageFig 5. Capacitance vs. Drain-Source Voltage
7.5
5.0
VDS = -40 V
VDS = -100 V
VDS = -160 V
2.5
, Gate-Source Voltage [V]
GS
-V
0.0 0 5 10 15 20 25
@ Notes : ID = -6.5 A
QG , Total Gate Charge [nC]
Page 4
SFP9640L
POWER MOSFET
Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature
1.2
2.5
P-CHANNEL
1.1
1.0
, (Normalized)
DSS
-BV
0.9
Drain-Source Breakd own Voltage
0.8
-75 -50 -25 0 25 50 75 100 125 150 175 200
@ Notes :
1. V
2. I
TJ , Junction Tempera ture [oC]
2
10
1
10
0
, Drain Current [ A]
10
D
-I
-1
10
0
10
Operation in This Area is Limited by R
@ Notes :
1. T
= 25 oC
C
2. T
= 150 oC
J
3. Single Pulse
DS(on)
1 ms
10 ms
DC
1
10
-VDS , Drain-Source Vol tage [V]
GS
= 250 µA
D
0.1 ms
2
10
= 0 V
2.0
1.5
, (Normalized)
1.0
DS(on)
R
Drain-Source On-Resistance
0.5
-75 -50 -25 0 25 50 75 100 125 150 175 200
@ Notes :
1. V
2. I
TJ , Junction Temperature [oC]
Fig 10. Max. Drain Current vs. Case TemperatureFig 9. Max. Safe Operating Area
12
10
8
6
4
, Drain Current [A]
D
2
-I
0
25 50 75 100 125 150
Tc , Case Temp erature [oC]
= -5 V
GS
= -5.5 A
D
10
10
(t) , Thermal Response
JC
θ
Z
10
Fig 11. Thermal Response
0
D=0.5
0.2
0.1
-1
0.05
0.02
0.01
-2
-5
10
single pulse
-4
10
-3
10
@ Notes :
1. Z
2. Duty Factor, D=t1/t
3. TJM-TC=PDM*Z
-2
10
10
(t)=1.02 oC/W Max.
JC
θ
P
DM
t
1
t
-1
2
(t)
JC
θ
2
0
10
1
10
t1 , Square Wave Pulse Duration [sec]
Page 5
P-CHANNEL
POWER MOSFET
SFP9640L
Fig 12. Gate Charge Test Circuit & Waveform
12V
10V
* Current Regulator
200nF
3mA
Current Sampling (IG)
V
in
R
G
V
50KΩ
V
out
Same Type
V
GS
as DUT
300nF
V
GS
10V
DS
DUT
R
1
Resistor
Fig 13. Resistive Switching Test Circuit & Waveforms
DUT
R
2
Current Sampling (ID)
Resistor
R
L
V
DD
( 0.5 rated V
V
out
90%
)
DS
10%
V
in
Q
gs
t
d(on)tr
Q
g
Q
gd
Charge
t
d(off)
t
t
on
f
t
off
Vary tpto obtain required peak I
10V
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
BV
L
I
DUT
L
BV
D
C
V
DD
DSS
I
AS
V
DD
V
DS
D
R
G
t
p
E
=LL I
AS
----
1 2
AS
ID (t)
t
2
p
DSS
-------------------­BV
DSS
-- V
DD
Time
V
(t)
DS
Page 6
SFP9640L
P-CHANNEL
POWER MOSFET
Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
V
V
GS
( Driver )
DUT
+
V
DS
--
I
S
L
V
GS
GS
Driver
R
G
D =
Same Type
as DUT
• dv/dt controlled by "R controlled by Duty Factor "D"
•I
S
Gate P ulse Wid th
-------------------------­Gate Pulse Period
V
DD
G
10V
I
S
( DUT )
V
DS
( DUT )
IFM, Body Diode Forward Current
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
f
Body Diode
Forward Voltage Drop
di/dt
V
DD
Page 7
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOS EnSigna
TM
TM
FACT™ FACT Quiet Series™
STAR*POWER is used under license
FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™
OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench
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SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™
UltraFET
VCX™
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
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PRODUCT STATUS DEFINITIONS Definition of Terms
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Advance Information
Preliminary
No Identification Needed
Formative or In Design
First Production
Full Production
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or
effectiveness.
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
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Rev. H4
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