Datasheet SFH9250L Datasheet (Fairchild Semiconductor)

Page 1
Advanced Power MOSFET
SFH9250L
FEATURES
Logic-Level Gate DriveAvalanche Rugged TechnologyRugged Gate Oxide Technology Lower Input CapacitancesImproved Gate ChargeExtended Safe Operating AreaLower Leakage Current : 10uA (Max.) @ VDS=-200V ❑ Lower R
: 0.175 Ω (Typ.)
DS(ON)
Absolute Maximum Ratings
Characteristic Value UnitsSymbol
Drain-to-Source Voltage Continuous Drain Current (T Continuous Drain Current (T
=25 °C)
C
=100 °C)
C
Drain Current-Pulsed Gate-to-Source Voltage Single Pulsed Avalanche Energy $ Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Total Power Dissipation (TC=25 °C) Linear Derating Factor Operating Junction and Storage Temperature Range Maximum Lead Temp. for Soldering Purposes, 1/8& from case for 5-seconds
T
V
DSS
I
D
I
DM
V
GS
E
AS
I
AR
E
AR
dv/dt
P
, T
J
T
D
STG
#
#
#
%
BV
DSS
R
DS(on)
ID= -19.5 A
TO-3P
1
2
3
1.Gate 2. Drain 3. Source
-200
-19.5
-12.3
-78
!20
990
-19.5
20.4
-5.0 204
1.63
- 55 to +150
300
= -200 V
= 0.23
V A A
V
mJ
A
mJ
V/ns
W
W/ °C
°C
Thermal Resistance
R
"JC
R
"CS
R
"JA
Characteristic Max. UnitsSymbol Typ.
Junction-to-Case
Case-to-Sink
Junction-to-Ambient
--
0.24
--
0.61
--
40
°C/W
Rev. A
Page 2
SFH9250L
P-CHANNEL
POWER MOSFET
Electrical Characteristics
CharacteristicSymbol
BV
BV/,T
,
V
R
GS(th)
I
GSS
I
DSS
DS(on)
g
C
C
C
t
d(on)
t
d(off)
Q Q Q
Drain-Source Breakdown Voltage
DSS
Breakdown Voltage Temp. Coeff.
J
Gate Threshold Voltage Gate-Source Leakage , Forward Gate-Source Leakage , Reverse
Drain-to-Source Leakage Current
Static Drain-Source On-State Resistance Forward Transconductance
fs
Input Capacitance
iss
Output Capacitance
oss
Reverse Transfer Capacitance
rss
Turn-On Delay Time
t
Rise Time
r
Turn-Off Delay Time
t
Fall Time
f
Total Gate Charge
Gate-Source Charge
gs
Gate-Drain(Miller) Charge
gd
(TC=25°C unless otherwise specified)
Max. UnitsTyp.Min.
V
-200
--
-1.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
-0.17
--
--
--
--
--
.175
13
2500
400 210
20 150 100
65
90
12
54
--
--
-2.0 100
-100 10
100
0.23
--
3250
520 270
50 310 210 140 120
--
--
V
V/ °C
V
nA
)A
S
pF
ns
nC
=0V,ID=-250)A
GS
I
=-250)A See Fig 7
D
V
=-5V,ID=-250)A
DS
V
=-20V
GS
VGS=20V V
=-200V
DS
V
=-160V,TC=125 °C
DS
V
=-5V,ID=-9.8A
GS
VDS=-40V,ID=-9.8A
=0V,VDS=-25V,f =1MHz
V
GS
VDD=-100V,ID=-19.5A, R
=6.2
G
VDS=-160V,VGS=-5V, ID=-19.5A
See Fig 6 & Fig 12
Test Condition
See Fig 5
See Fig 13
*
*
*+
*+
Source-Drain Diode Ratings and Characteristics
CharacteristicSymbol Max. UnitsTyp.Min. Test Condition
--
--
--
260
2.8
-19.5
-78
-1.5
--
--
I
I
SM
V
t
Q
Notes ;
# Repetitive Rating : Pulse Wi dth Lim i ted by Maximum Junction Temperature $ L=3.9mH, I % I * Pulse Test : Pulse Width ( 300)s, Duty Cycle ( 2% + Essentially Independent of Operating Temperature
Continuous Source Current
S
Pulsed-Source Current # Diode Forward Voltage
SD
Reverse Recovery Time
rr
Reverse Recovery Charge
rr
=-19.5A, VDD=-50V, RG=27, Starting TJ =25'
AS
(-19.5A, di/dt(500A/)s, VDD(BV
SD
--
--
*
--
--
--
, Starting TJ =25'
DSS
Integral reverse pn-diode
A
in the MOSFET
V
T
ns
T
)C
di
=25 °C,IS=-19.5A,VGS=0V
J
=25 °C,IF=-19.5A,VDD=-160V
J
/dt=100A/)s
F
*
Page 3
P-CHANNEL
POWER MOSFET
SFH9250L
-
Note :
1. 250.s Pulse Te st
'
= 25
2. T
C
0
10
1
10
10
, Drain Current [A]
D
-I
10
V Top : -10.0 V
-8.0 V
-6.0 V
-5.0 V
-4.5 V
-4.0 V
1
-3.5 V Bottom : -3.0 V
0
-1
10
Fig 1. Output Characteristics Fig 2. Transfer Characteristics
GS
-VDS, Drain-Source Voltage [V]
0.8
0.6
VGS = - 10V
VGS = - 5V
-
Note : T
J
= 25
'
]
, [
0.4
DS(on)
R
0.2
Drain-Source On-Resistance
0.0 0 20406080100
-ID , Drain Current [A]
1
10
'
150
0
10
'
25
, Drain Current [A]
D
-I
-1
10
246810
'
-55
-
Note
= -40V
1. V
DS
2. 250.s Pulse Test
-VGS , Gate-Source Voltage [V]
Fig 4. Source-Drain Diode Forward VoltageFig 3. On-Resistance vs. Drain Current
1
10
0
10
, Reverse Drain Current [A]
DR
-I
-1
10
'
150
'
25
-
Note :
= 0V
1. V
GS
2. 250.s Pulse Test
0.6 1.2 1.8 2.4 3.0 3.6
-VSD , Source -Drain V o lta g e [V]
Capacitances [pF]
12000
10500
9000
7500
6000
4500
3000
1500
C
= Cgs + Cgd (Cds = shorted)
iss
= Cds + C
C
oss
gd
C
= C
rss
gd
Fig 6. Gate Charge vs. Gate-Source VoltageFig 5. Capacitance vs. Drain-Source Voltage
6
VDS = -40V
VDS = -100V
4
-
10
1
Note ;
1. V
= 0 V
GS
2. f = 1 MHz
C
iss
C
oss
C
rss
0
-1
10
0
10
2
, Gate-Source Voltage [V]
GS
-V
0
020406080100
-VDS, Drain-Source Voltage [V]
VDS = -160V
QG, Total Gate Cha rge [nC]
-
Note : I
= -19.5 A
D
Page 4
SFH9250L
P-CHANNEL
POWER MOSFET
Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature
1.2
1.1
1.0
, (Normalized)
DSS
-BV
0.9
Drain-Source Breakdown Voltage
0.8
-100 -50 0 50 100 150 200
TJ, Junction Temperature [oC]
Operation in This Area
2
10
is Limited by R
-
Note :
1. VGS = 0 V
2. ID = -250 .A
2.5
2.0
1.5
, (Norma lized)
1.0
DS(ON)
R
0.5
Drain-Source On-Resistance
0.0
-100 -50 0 50 100 150 200
TJ, Junction Temperature [oC]
DS(on)
100 µs
Fig 10. Max. Drain Current vs. Case TemperatureFig 9. Max. Safe Operating Area
20
15
1 ms
= 25 oC
C
= 150 oC
J
10 ms
DC
2
10
10
, Drain Current [A]
D
-I
5
0
25 50 75 100 125 150
TC, Case Temperature [']
1
10
, Drain Current [A]
D
0
10
-I
-1
10
0
10
-
Notes :
1. T
2. T
3. Single Pulse
1
10
-VDS, Drain-Source Voltage [V]
-
1. V
2. I
Note :
= -5 V
GS
= -9.8 A
D
0
10
Fig 11. Thermal Response
D=0.5
-
0.2
-1
10
0.1
0.05
(t), T hermal Response Z
0.02
JC
0.01
/
-2
10
-5
10
single pulse
-4
10
t
1
-3
10
-2
10
, S q u a re W av e P u lse D u ra tio n [s e c]
N o te s :
(t) = 0.61 '/W M a x.
1. Z
/
JC
2. D u ty F a cto r , D = t
3. TJM - TC = PDM * Z
P
DM
t
1
t
2
-1
10
10
1/t2
(t)
/
JC
0
1
10
Page 5
P-CHANNEL
POWER MOSFET
12V
200nF
-3mA
50K0
Fig 12. Gate Charge Test Circuit & Waveform
V
Same Type
GS
as DUT
300nF
V
GS
-5V
V
DS
Q
gs
DUT
Fig 13. Resistive Switching Test Circuit & Waveforms
SFH9250L
Q
Q
gd
Charge
-5V
-5V
R
V
DS
R
G
( 0.5 rated V
V
DD
DS
)
V
in
10%
DUT
V
DS
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
V
L
DS
V
DD
I
D
R
G
E
=LL I
AS
V
DD
DUT
I
AS
BV
DSS
t
d(on)tr
90%
1
---­2
t
on
AS
t
p
I
(t)
D
t
d(off)
BV
DSS
-------------------­BV
DSS
-- V
DD
Time
t
off
t
f
V
(t)
DS
Page 6
SFH9250L
P-CHANNEL
POWER MOSFET
Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
V
GS
( Driver )
DUT
+
V
DS
_
I
S
L
Driver
R
G
V
GS
D =
Compliment of DUT
(N-Channel)
• dv/dt controlled by R
•IScontrolled by pulse period
Gate Pulse Width
-------------------------­Gate Pulse Period
V
DD
G
5V
I
S
( DUT )
V
DS
( DUT )
IFM, Body Diode Forward Current
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
f
Body Diode
Forward Voltage Drop
di/dt
V
DD
Page 7
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOS EnSigna
TM
TM
FACT™ FACT Quiet Series™
STAR*POWER is used under license
FAST FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™
OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench
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SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™
UltraFET
VCX™
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
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PRODUCT STATUS DEFINITIONS Definition of Terms
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Advance Information
Preliminary
No Identification Needed
Formative or In Design
First Production
Full Production
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effectiveness.
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
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Rev. H4
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