The NE555 monolithic timing circuit is a highly
stable controller capab le of producing accurate
time delays or oscillation. In the time delay mode
of operation, the time is precisely controlled by
one external resistor and capacitor. For a stable
operation as an oscillator, the free running
frequency and the duty cycle are both accurately
controlled with two external resistors and one
capacitor.
The circuit may be triggered and reset on falling
wav eforms, and the output structure can source
or sink up to 200mA.
Pin connections
(top view)
1 - GND
2 - Trigger
3 - Output
4 - Reset
5 - Control voltage
6 - Threshold
7 - Discharge
8 - V
Absolute maximum ratings and operating conditionsNE555 - SA555 - SE555
2 Absolute maximum ratings and operating conditions
Table 1.Absolute maximum ratings
SymbolParameterValueUnit
V
CC
T
j
T
stg
Table 2.Operating conditions
Supply voltage18V
Junction temperature150°C
Storage temperature range-65 to 150°C
SymbolParameterValueUnit
Supply voltage
Vth, V
V
trig
CC
, Vcl, V
NE555
SA555
SE555
Maximum input voltageV
reset
4.5 to 16
4.5 to 16
4.5 to 18
CC
Operating free air temperature range
T
oper
NE555
SA555
SE555
0 to 70
-40 to 105
-55 to 125
V
V
°C
4/20
Page 5
NE555 - SA555 - SE555Electrical characteristics
3 Electrical characteristics
Table 3.T
= +25°C, VCC = +5V to +15V (unless otherwise specified)
amb
SymbolParameter
Supply current (RL = ∝)
I
Low stageV
CC
High stateV
= +5V
CC
VCC = +15V
= 5V
CC
Timing error (monostable)
(R
= 2k to 100kΩ, C = 0.1μF)
A
Initial accuracy
(1)
Drift with temperature
Drift with supply voltage
Timing error (astable)
(R
= 1kΩ to 100kΩ, C = 0.1μF, VCC = +15V)
A, RB
Initial accuracy -
(1)
Drift with temperature
Drift with supply voltage
Control voltage level
V
CL
VCC = +15V
= +5V
V
CC
Threshold voltage
V
th
V
CC
= +15V
VCC = +5V
Threshold current
I
th
(2)
Trigger voltage
V
V
I
trig
reset
trig
VCC = +15V
= +5V
V
CC
Trigger current (V
Reset voltage
(3)
= 0V)0.50.90.52.0µA
trig
Reset current
I
reset
V
V
reset
reset
= +0.4V
= 0V
Low level output voltage
= +15VI
V
CC
V
OL
VCC = +5V I
O(sink)
I
O(sink)
I
O(sink)
I
O(sink)
O(sink)
I
O(sink)
= 10mA
= 50mA
= 100mA
= 200mA
= 8mA
= 5mA
High level output voltage
V
= +15VI
V
OH
CC
V
CC
= +5V I
O(sink)
I
O(sink)
O(sink)
= 200mA
= 100mA
= 100mA
SE555NE555 - SA555
Min.Typ.Max.Min.Typ.Max.
3
10
2
0.5
30
0.05
1.5
90
0.15
9.6
2.9103.33
9.4
2.7103.33
5
12
3
10
2
2
100
0.2
1
50
0.130.5
2.25
150
0.3
10.4
3.892.6103.33114
10.648.8
2.4103.33
6
15
ppm/°C
ppm/°C
11.2
4.2
0.10.250.10.25µA
4.8
1.4551.67
5.2
1.9
4.5
1.151.67
5.6
2.2
0.40.710.40.71V
13
0.1
0.4
0.1
0.4
2.5
0.1
0.05
12.5
13.3
3
3.3
0.4
1
0.15
0.5
2
2.2
0.1
0.4
0.1
0.4
2
0.4
1.5
0.25
0.75
2.5
2.5
0.25
0.2
0.3
0.25
0.4
0.35
12.5
12.75
2.75
13.3
3.3
Unit
mA
%
%/V
%
%/V
V
V
V
mA
V
V
5/20
Page 6
Electrical characteristicsNE555 - SA555 - SE555
Table 3.T
= +25°C, VCC = +5V to +15V (unless otherwise specified)
amb
SE555NE555 - SA555
SymbolParameter
Min.Typ.Max.Min.Typ.Max.
I
dis(off)
V
dis(sat)
t
1. Tested at VCC = +5V and VCC = +15V.
2. This will determine the maximum value of R
operation and 3.5MΩ for +5V operation.
3. Specified with trigger input high.
4. No protection against excessive pin 7 current is necessary, providing the package dissipation rating is not exceeded.
5. Time measured from a positive pulse (from 0V to 0.8xV
Output pin. Trigger is tied to Threshold.
Discharge pin leakage current
(output high) V
Discharge pin saturation voltage
(output low)
VCC = +15V, I
VCC = +5V, I
t
Output rise time
r
t
Output fall time
f
Turn off time
off
(4)
(5)
dis
dis
dis
(V
= 10V
= 15mA
= 4.5mA
= VCC)0.50.5µs
reset
+ RB for 15V operation. The maximum total (RA + RB) is 20MΩ for 15V
A
) on the Threshold pin to the transition from high to low on the
CC
2010020100nA
18080480
200
100
100
200
200
18080480
200
100
100
300
300
Unit
mV
ns
6/20
Page 7
NE555 - SA555 - SE555Electrical characteristics
Figure 3.Minimum pulse width required for
triggering
Figure 4. Supply current versus supply
voltage
Figure 5.Delay time versus temperature Figure 6.Low output voltage versus output
sink current
Figure 7.Low output voltage versus output
sink current
Figure 8.Low output voltage versus output
sink current
7/20
Page 8
Electrical characteristicsNE555 - SA555 - SE555
Figure 9.High output voltage drop versus
output
Figure 11. Propagation delay versus voltage
level of trigger value
Figure 10. Delay time versus supply voltage
8/20
Page 9
NE555 - SA555 - SE555Application information
4 Application information
4.1 Monostable operation
In the monostable mode, the timer generates a single pulse. As shown in Figure 12, the
external capacitor is initially held discharged by a transistor inside the timer.
Figure 12. Typical schematics in monostable operation
V
= 5 to 15V
CC
Reset
R1
4
8
Trigger
Output
The circuit triggers on a negative-going input signal when the level reaches 1/3 V
2
NE555
3
1
7
6
Control Voltage
5
0.01
C1
μF
. Once
CC
triggered, the circuit remains in this state until the set time has elapsed, e v en if it is triggered
again during this interval. The duration of the output HIGH state is given by t = 1.1 R
1C1
and
is easily determined by Figure 14.
Note that because the charge rate and the threshold level of the comparator are both
directly proportional to supply voltage, th e ti ming int e rval is inde pende nt of sup ply. Applying
a negative pulse simultaneously to the reset terminal (pin 4) and the trigger terminal (pin 2)
during the timing cycle discharges the external capacitor and causes the cycle to start over.
The timing cycle now starts on the positive edge of the reset pulse. During the time the reset
pulse is applied, the output is driven to its LOW state.
When a negative trigger pulse is applied to pin 2, the f lip-flop is set, releasing the shortcircuit across the external capacitor and driving the output HIGH. The voltage across the
capacitor increases exponentially with the time co nsta nt t = R
the capacitor equals 2/3 V
, the comparator resets the flip-flop which then discharges the
CC
. When the voltage across
1C1
capacitor rapidly and drives the output to its LOW state.
Figure 13 shows the actual waveforms generated in this mode of operation.
When Reset is not used, it should be tied high to avoid any possibility of unwanted
triggering.
9/20
Page 10
Application informationNE555 - SA555 - SE555
CAPACITOR VOLTAGE = 2.0V/div
t = 0.1 ms / div
INPUT = 2.0V/div
OUTPUT VOLTAGE = 5.0V/div
R1 = 9.1kΩ, C1 = 0.01μF, R = 1kΩ
L
C
(μF)
10
1.0
0.1
0.01
0.001
101001.01010010(t )
d
μsμs
msmsmss
10M
Ω
1M
Ω
1
00
k
Ω
10k
Ω
R1
=
1k
Ω
Figure 13. Waveforms in monostable operation
Figure 14. Pulse duration versus R1C1
4.2 Astable operation
When the circuit is connected as shown in Figure 15 (pin 2 and 6 connected) it triggers itself
and free runs as a multi-vibrator. The external capacitor charges through R
discharges through R
of these two resistors.
In the astable mode of oper ation, C
As in the triggered mode, the charge and discharge times and, therefore, frequency are
independent of the supply voltage.
10/20
and R2 and
only. Thus the duty cycle can be set accurately by adjusting the ratio
2
charges and discharges between 1/3 VCC and 2/3 VCC.
1
1
Page 11
NE555 - SA555 - SE555Application information
Figure 15. Typical schematics in astable operation
= 5 to 15V
V
CC
R1
4
8
Output
0.01μF
Control
Voltage
3
NE555
5
1
7
R2
6
2
C1
Figure 16 shows the actual waveforms generated in this mode of operation.
The charge time (output HIGH) is given by:
t1 = 0.693 (R
+ R2) C
1
1
and the discharge time (output LOW) by:
t2 = 0.693 (R
2
) C
1
Thus the total period T is given by:
T = t1 + t2 = 0.693 (R1 + 2R2) C1
The frequency of oscillation is then:
f =
1
---
T
1.44
-------------------------------------- -=
R1 2R2+()C1
It can easily be found from Figure 17.
The duty cycle is given by:
------------------------- -=
R1 2R2+
R2
D
11/20
Page 12
Application informationNE555 - SA555 - SE555
t = 0.5 ms / div
OUTPUT VOLTAGE = 5.0V/div
CAPACITOR VOLTAGE = 1.0V/div
R1 = R2 = 4.8kΩ, C1= 0.1μF, R = 1kΩ
L
C
(μF)
10
1.0
0.1
0.01
0.001
0.11101001k10k f (Hz)
o
1
M
Ω
R
1
+
R
2
=
1
0
M
Ω
1
0
0
k
Ω
1
0
k
Ω
1
k
Ω
Figure 16. Waveforms in astable operation
Figure 17. Free running frequency versus R
, R2 and C
1
1
12/20
Page 13
NE555 - SA555 - SE555Application information
Trigger
Output
C
NE555
2
4
3
1
5
6
7
8
E
V
CC
0.01μF
R2
R1
R
2N4250
or equiv.
4.3 Pulse width modulator
When the timer is connected in the monostab le mode a nd triggered with a cont inuous pulse
train, the output pulse width can be m odulated by a signal applied to pin 5. Figure 18 shows
the circuit.
Figure 18. Pulse width modulator
V
CC
R
A
4
8
Trigger
Output
4.4 Linear ramp
When the pull-up resistor, RA, in the monostable circuit is replaced by a constant current
source, a linear ramp is generated. Figure 19 shows a circuit configuration that will perform
this function.
Figure 19. Linear ramp
2
NE555
3
1
7
6
Modulation
Input
5
C
13/20
Page 14
Application informationNE555 - SA555 - SE555
Figure 20 shows the waveforms generator by the linear ramp.
For a 50% duty cycle, the resistors RA and RE can be connected as in figure 19. The time
period for the output hi gh is th e sam e a s for astable operation (see Section 4.2 on page 10):
t1 = 0.693 R
For the output low it is
Thus the frequency of oscillation is:
C
A
t2[(R. RB)/(RA+RB)].C.Ln
=
Top trace: input 3V/DIV
Middle trace: output 5V/DIV
Bottom trace: output 5V/DIV
Bottom trace: capacitor voltage 1V/DIV
RB 2RA–
-------------------------- -
2RB RA–
1
f
---------------- -=
t1 t2+
14/20
Page 15
NE555 - SA555 - SE555Application information
Figure 21. 50% duty cycle oscillator
V
CC
4
2
8
R
7
B
22kΩ
R
A
51kΩ
V
CC
Out
3
Note that this circuit will not oscillate if R
and R
cannot bring pin 2 down to 1/3 VCC and trigger the lower comparator.
B
4.6 Additional information
Adequate power supply by passing is necessary to protect associated circuitry. The
minimum recommended is 0.1µF in parallel with 1µF electrolytic.
NE55
1
is greater than 1/2 RA because the junction of RA
B
6
5
0.01μF
C
0.01μF
15/20
Page 16
Package informationNE555 - SA555 - SE555
5 Package information
In order to meet environmental requirements, STMicroelectronics offers these devices in
ECOPACK
category of second level interconnect is marke d on the pa ckage and on the inner box label,
in compliance with JEDEC Standard JESD97. The maximum ratings related t o soldering
conditions are also marked on the inner box label. ECOPACK is an STMicroelectronics
trademark. ECOPACK specifications are available at: www.st.com
®
packages. These packages have a lead-free second level interconnect. The
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
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