Datasheet SDA9415-B13 Datasheet (Micronas Intermetall)

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PRELIMINARY DATA SHEET

SDA 9415-B13 DAEDALUS

Display Processor and Scan Rate Converter using Embedded DRAM Technology Units

Edition Feb. 28, 2001 6251-560-1PD

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SDA 9415 - B13 Revision History: 2000-05 (V 1.0)

Previous Versions: 1999-04-01

Changes to the previous issue Version 00, Edition 04.99, are marked with a change bar

05.2000 editorial changes only (no change of content)

We Listen to Your Comments

Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to:

docservice@micronas.com

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1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Pin Diagram: P-MQFP-144-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5 System description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

5.2 Input sync controller (ISCM/ISCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

5.3 Input format conversion (IFCM/IFCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

5.4 Input signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

5.4.1 Adjustable delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

5.4.2 Vertical and horizontal compression (VHCOMM/VHCOMS) . . . . . . . . . .36

5.4.2.1 Vertical compression and peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

5.4.2.2 Horizontal compression/expansion and panorama mode . . . . . . . . . .40

5.4.3 Noise reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

5.4.3.1 Spatial noise reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

5.4.3.2 Motion adaptive temporal noise reduction . . . . . . . . . . . . . . . . . . . . . .45

5.4.4 Noise measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

5.4.5 Letter box detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

5.5 Clock concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

5.6 Application modes and memory concept . . . . . . . . . . . . . . . . . . . . . . . . . . .57

5.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

5.6.2 Configuration controlling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

5.6.3 SRC mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

5.6.4 SSC and MUP mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

5.6.5 Configuration switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

5.6.6 Joint line free display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

5.6.7 Master slave switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

5.6.8 Refresh and still picture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

5.6.9 Memory management and animation controlling . . . . . . . . . . . . . . . . . . .74

5.7 Output sync controller (OSCM/S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

5.7.1 HOUT generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

5.7.2 VOUT generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

5.7.3 Switching from H-and-V-freerunning to H-and-V-locked mode . . . . . . . .87

5.7.4 Operation mode generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

5.8 Motion estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

5.9 Motion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

5.10 Global motion, film mode and phase detection . . . . . . . . . . . . . . . . . . . . .108

5.11 Vertical expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111

5.12 Display processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

5.12.1 Peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

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5.12.2 Digital luminance transition improvement . . . . . . . . . . . . . . . . . . . . . . . 115

5.12.3 Digital colour transition improvement . . . . . . . . . . . . . . . . . . . . . . . . . .117

5.12.4 Output format conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

5.12.5 Insertion facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

5.12.6 Coarse delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121

5.12.7 Digital-to-Analog conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122

5.13 I²C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

5.13.1 I²C Bus slave address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

5.13.2 I²C Bus format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123

5.13.3 I²C Bus commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

5.13.4 Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

6.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

6.2 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

6.3 Characteristics (Under operating range conditions) . . . . . . . . . . . . . . . . .179

7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181

8 Wave forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

8.1 I²C Bus timing START/STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

8.2 I²C Bus timing DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182

8.3 Timing diagram clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

8.4 Clock circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183

9 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184

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Figure 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 2 Block diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 3 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 4 Principles of SRC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 5 Principles of SSC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 6 Principles of MUP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 7 Input I²C Bus parameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 8 Field detection and VINM delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 9 Explanation of 656 format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 10 SYNCENM/SYNCENS signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 11 Input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 12 Block diagram of input processing blocks . . . . . . . . . . . . . . . . . . . . . . .34

Figure 13 Block diagram of VHCOMM/VHCOMS . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 14 Principles of panorama mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 15 Block diagram of noise reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 16 Block diagram of motion detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 17 LUT for motion detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 18 Example of noise measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 19 Principle of letter box detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 20 Block diagram of letter box detection. . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 21 Histogram and line type decision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 22 Visibility of letter box detection I²C Bus parameters . . . . . . . . . . . . . . .53

Figure 23 Clock concept of SDA 9415 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 24 Application for SDA 9415 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 25 Supported data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 26 Switching from SRC-PIP mode to SSC mode . . . . . . . . . . . . . . . . . . . .67

Figure 27 Changing picture sizes to get a double window display. . . . . . . . . . . . .68

Figure 28 Completing the operations to a master slave exchange . . . . . . . . . . . .69

Figure 29 Example for animation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Figure 30 Equation of the position of the left upper picture corner . . . . . . . . . . . .75

Figure 31 Explanation of memory management I . . . . . . . . . . . . . . . . . . . . . . . . .76

Figure 32 Explanation of memory management II . . . . . . . . . . . . . . . . . . . . . . . . .77

Figure 33 Explanation of memory management III . . . . . . . . . . . . . . . . . . . . . . . .78

Figure 34 Block diagram of OSCM/S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Figure 35 Output I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Figure 36 Output write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Figure 37 Ingenious configurations of the HOUT and VOUT generator . . . . . . . .84

Figure 38 VOUT generation depending on I²C Bus parameter RMODE . . . . . . . .86

Figure 39 Explanation of field and display line-scanning pattern . . . . . . . . . . . . . .88

Figure 40 Explanation of operation mode timing . . . . . . . . . . . . . . . . . . . . . . . . . .89

Figure 41 Principle of block matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Figure 42 Block diagram of motion estimation and compensation. . . . . . . . . . . .101

Figure 43 Block diagram of motion estimation . . . . . . . . . . . . . . . . . . . . . . . . . . .102

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Figure 44 Relative positions of the spatial predictors . . . . . . . . . . . . . . . . . . . . . 102

Figure 45 Timing of 100 Hz scan rate conversion . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 46 Principles of motion compensation . . . . . . . . . . . . . . . . . . . . . . . . . . .104

Figure 47 Principles of motion compensation for the b field (FILSEL=0). . . . . . .105

Figure 48 Output sequence generation: Camera mode. . . . . . . . . . . . . . . . . . . . 106

Figure 49 Output sequence generation: PAL film mode . . . . . . . . . . . . . . . . . . . 107

Figure 50 Output sequence generation: NTSC film mode . . . . . . . . . . . . . . . . . . 107

Figure 51 Calculation of maximum VPAN value . . . . . . . . . . . . . . . . . . . . . . . . . 112

Figure 52 Block diagram of display processing . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Figure 53 Block diagram peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Figure 54 Principles of DCTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Figure 55 Application for SDA 9415. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

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Table 1 Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 2 Input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 3 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Table 4 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 5 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 6 Input read I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 7 Input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 8 Input data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 9 Input sync formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 10 DELM/DELS I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 11 Examples of vertical filter adjustment . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 12 Conversion table between dezV and DEZVM / DEZVS. . . . . . . . . . . . 38

Table 13 Input write I²C Bus parameter YPEAKM/YPEAKS/CPEAKM/CPEAKS 39

Table 14 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Table 15 Examples of horizontal filter adjustment . . . . . . . . . . . . . . . . . . . . . . . 41

Table 16 Conversion table between dezH and DEZHM/DEZMS . . . . . . . . . . . . 41

Table 17 Input write I²C Bus parameter CHFILM/CHFILS . . . . . . . . . . . . . . . . . 42

Table 18 Filter I²C Bus parameter in case of PANAON=1 . . . . . . . . . . . . . . . . . 42

Table 19 I²C Bus parameter PANAST in case of PANAON=1 . . . . . . . . . . . . . . 43

Table 20 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Table 21 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 22 I²C Bus parameter TNRVAY/C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 23 I²C Bus parameter TNRHOY/C and TNRKOY/C . . . . . . . . . . . . . . . . . 47

Table 24 I²C Bus parameter TNRCLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 25 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Table 26 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 27 Input read I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 28 Line Type Decision of LBD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 29 Evaluation of the reliability signal RELY . . . . . . . . . . . . . . . . . . . . . . . 52

Table 30 Correction of “start/end-line decision filter” block . . . . . . . . . . . . . . . . . 53

Table 31 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 32 Input read I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 33 Input signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 34 Output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 35 Clock concept switching matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 36 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 37 Definition of MEMOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 38 Definition of CHRFORM/CHRFORS . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Table 39 Definition of ORGMEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 40 Definition of ORGMEMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 41 Definition of VERRESM/VERRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Table 42 Programmable data configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 43 Applications of different data configurations . . . . . . . . . . . . . . . . . . . . 62

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Table 44 Maximum picture sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 45 Definition of MEMWRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 46 Definition of MEMWRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Table 47 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Table 48 Definition of WRFLDM/WRFLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 49 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Table 50 Definition of ORGMEMM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 51 Definition of ORGMEMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 52 Definition of MEMRDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 53 Definition of MEMRDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Table 54 Definition of MEMWRM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 55 Definition of MEMWRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Table 56 Switching from SRC PIP mode to SSC mode . . . . . . . . . . . . . . . . . . . 68

Table 57 Changing the picture sizes to double window format. . . . . . . . . . . . . . 69

Table 58 Performing a master slave exchange . . . . . . . . . . . . . . . . . . . . . . . . . 70

Table 59 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 60 Output read I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Table 61 Supported data formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 62 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Table 63 Output read I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table 64 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Table 65 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table 66 Input write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table 67 Output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table 68 Output write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table 69 Output write I²C Bus parameter INTMODE . . . . . . . . . . . . . . . . . . . . . 86

Table 70 Output write I²C Bus parameter INTMODE . . . . . . . . . . . . . . . . . . . . . 86

Table 71 Static operation modes (only valid for ADOPMOM=0, RMODE=0) . . . 90 Table 72 Static operation modes (only valid for ADOPMOM=0, RMODE=1) . . . 91

Table 73 Special combinations of STOPMOM and ADOPMOM . . . . . . . . . . . . 92

Table 74 Display line-scanning pattern sequence . . . . . . . . . . . . . . . . . . . . . . . 93

Table 75 Static operation modes slave. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Table 76 Adaptive operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 77 Output write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Table 78 Key I²C Bus parameters of the 3-D RS motion estimation. . . . . . . . . 100

Table 79 Output write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Table 80 Output write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 81 Principles of global motion and film mode detection . . . . . . . . . . . . . 109

Table 82 Definition of scmin/scmax depending on SFMINTH/SFMAXTH . . . . 109

Table 83 Output write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 84 Output read I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Table 85 Output write I²C Bus parameter VERINT . . . . . . . . . . . . . . . . . . . . . . 111

Table 86 Examples of reachable expansion factors . . . . . . . . . . . . . . . . . . . . . 112

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Table 87 Output write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 88 Output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Table 89 Conversion table BCOF/HCOF to gain_bp/gain_hp . . . . . . . . . . . . . 115

Table 90 Output write I²C Bus parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Table 91 I²C Bus parameter THRESY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 92 I²C Bus parameter THRESY_UP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table 93 I²C Bus parameter ASCENTLTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 94 Output write I²C Bus parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Table 95 I²C Bus parameter THRESC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Table 96 I²C Bus parameter ASCENTCTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 97 Output write I²C Bus parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Table 98 Output write parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Table 99 Output write parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 100 Output write I²C Bus parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Table 101 Output write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 102 Output write I²C Bus parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

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SDA 9415 - B13 Preliminary Data Sheet

Introduction

1 Introduction

The SDA 9415 is a new component of the Micronas MEGAVISION® IC set, which enables the system to reduce large area and line flickering of interlaced TV standards.

The scan rate conversion to 100/120 Hz interlaced or 50/60 Hz progressive scan is motion vector based. For the 100/120 Hz (50/60 Hz) conversion the SDA 9415 really calculates 100/120 Hz (50/60 Hz) fields with continuous motion phases to avoid double contour effects in the motion display. In the special case of movie sources, which have a non-continuous motion phase, the SDA 9415 generates at the output an appropriate sequence with a continuous motion phase („True Motion“).

Due to the frame based signal processing, the noise reduction has been greatly improved. Furthermore different motion detectors for luminance and chrominance have been implemented. For automatic controlling of the noise reduction parameters a noise measurement algorithm is included, which measures the noise level in the picture or in the blanking period. In addition a spatial noise reduction is implemented, which reduces the noise even in the case of motion.

The SDA 9415 has two input channels, which can be used for different features like Picture-in-Picture (maximum approximately 1/9 picture) and “Double-window/Splitscreen”. The two input signals can be scaled horizontally and vertically with variable factors. Panorama modes will be supported.

Besides that an algorithm for the detection of letter box pictures is included. The SDA 9415 delivers the start and the end line of the active picture part of the input signal to an external µC. the full screen

Picture sharpness can be greatly improved by a LTI (luminance transition improvement) or/and peaking and a CTI (colour transition improvement) algorithm. The resolution of the output signals is 9 bit. The SDA 9415 has analog output signals.

The µC calculates the zoom factors for displaying the active picture part on

and sends this values back to the SDA 9415.

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SDA 9415 - B13 Preliminary Data Sheet

Features

2Features

• Different application modes

- SRC mode:

- High performance scan rate converter

- High performance scan rate converter plus high resolution frame based joint-linefree Picture-in-Picture (maximum approximately 1/9 picture)

- SSC mode:

- Split screen applications with two signal sources (e.g. double window)

- MUP mode:

- Multipicture display mode (e.g. tuner scan)

• 8 bit amplitude resolution of each input channel

- Two input channels

- Input frequency up to 27 MHz

- ITU-R 656 data format (8 wires data only and additional sync information or 8 wires including sync information)

- 4:2:2 luminance and chrominance parallel (2x8 wires)

• Two different representations of input chrominance data

- 2’s complement code

- Positive dual code

• Two flexible input sync controllers

• Vertical peaking of the input signal

• Flexible scaling of the input signal

- Flexible digital vertical compression of the input signal (1.0, ... [2 line resolution] ... , 1/32)

- Flexible horizontal compression and expansion of the input signal (2.0, ... [4 pixel resolution] ... ,1.0 , ... [4 pixel resolution] ... , 1/32)

- Panorama mode (programmable characteristic)

• Noise reduction

- Motion adaptive spatial and temporal noise reduction (3D-NR)

- Temporal noise reduction for luminance and chrominance, frame based or field

based

- Different motion detectors for luminance and chrominance or identical

- Flexible programming of the temporal noise reduction parameters

- Automatic measurement of the noise level (5 bit value, readable by I²C-bus)

• 3-D motion estimation

- High performance motion estimation based on block matching algorithm

- Film mode detector (PAL and NTSC), Global motion flag (readable by I²C bus)

• Automatic detection of letter box formats (readable by I²C bus)

• TV mode detection by counting line numbers (PAL, NTSC, readable by I²C bus)

• Embedded memory

- 6 Mbit embedded DRAM core for field memories

- 1,1 Mbit embedded DRAM core for line memories, vector memory, block-to-line

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SDA 9415 - B13 Preliminary Data Sheet

Features

converter

- 36 kbit SRAM for block matching, line-to-block converter

• Flexible clock and synchronization concept

- Decoupling of the input and output clock system possible

• Scan rate conversion

- Motion compensated 100/120 Hz interlaced scan conversion (Micronas VDU)

- Motion compensated 50/60 Hz progressive scan conversion (Micronas VDU)

- Simple interlaced modes: ABAB, AABB, AAAA, BBBB

- Simple progressive modes: AB, AA*, B*B

- True Motion: 50 Hz motion resolution even for 25 Hz PAL film sources

60 Hz motion resolution even for 30 Hz NTSC film sources

- Large area and line flicker reduction

• Flexible digital vertical expansion of the output signal (1.0, ... [1/64] ... , 2.0)

• Sharpness improvement

- Digital colour transition improvement (DCTI)

- Digital luminance transition improvement (DLTI)

- Peaking (luminance only)

• Flexible output sync controller

- Flexible positioning of the two output channels in all application modes

- Flexible height and width of the two output pictures

- Flexible programming of the output sync raster

• Signal manipulations

- Still frame or field

- Insertion of coloured background

- Insertion of a selection border

- Adjustable delay between Y and UV signal (+4,...[1]...,-3 input pixels) at the input

side

- Adjustable delay between Y and UV signal (+3,...[0.5]...,- 4 output pixels) at the

output side

• Three D/A converters

- 9 bit amplitude resolution for Y, -(R-Y), -(B-Y) output

- 60 MHz maximal clock frequency

- Two-fold oversampling

- Simplification of external analog post filtering and differential analog outputs

• I²C-bus control (400 kHz)

• P-MQFP-100 package

• 3.3 V ± 5% supply voltage

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SDA 9415 - B13 Preliminary Data Sheet

3 Block diagram

HINM VINM

SYNCENM

CLKM

YINM

UVINM

YINS

UVINS

CLKS

HINS VINS

SYNCENS

Input sync controller Master

clock

doubling

PLLM

conversion

clock

doubling

PLLS

Input sync controller Slave

IFCM Input

format

IFCS Input

format

ISCM

ISCS

Line memory

VHCOMM

Vertical and

horizontal

compression/

expansio n

VHCOMS

Vertical and

horizontal

compression/

expansio n

Line memory

TSNR

Temporal,

spatial

noise

reduction

RESETTEST

LBD

Letter

box

detection

eDRAM

Buffer

+ Voltage control

Test-

controller

Memory

Controller

Vector

memory

motion

estimation

Line

memory

SRCM

Scan rate

conversion

Master

Vertical

expansion

SRCS

clock

doubling

PLLD

M U X

X1/CLKD

OSCM/S

Output sync

controller

Master

DLTI DCTI

Peaking

Block diagram

OFC 4:4:4 8:8:8

Framing

Delay

SDA

DAC

I²C

SCL

CLKOUT

INTERLACED HOUT

VOUT

BLANK

YOUT

UVOUT

bd9415

Figure 1 Block diagram

The SDA 9415 contains the blocks, which will be briefly described below: ISCM/S - Flexible input sync controller IFCM/S - Input format conversion, Adjustable delay VHCOMM/S - Vertical and horizontal compression, horizontal expansion, panorama mode (only M) TSNR - Temporal and spatial noise reduction, noise measurement LBD - Letter box detection ME - Motion estimation, Film mode and phase detection MC - Memory controller OSCM/S - Flexible output sync controller OFC - Output format conversion, 4:4:4, 8:8:8 interpolation, Adjustable delay SRCM/S - Scan rate conversion, vertical expansion MUX - Combination of the two output channels DLTI/DCTI/Peaking - Luminance and chrominance transition improvement, luminance peaking

C - I²C bus interface PLLM/S/D - PLL for frequency doubling LM - Line memory core, VM - Vector memory core ED - eDRAM core

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SDA 9415 - B13 Preliminary Data Sheet

INPUT PROCESSING MASTER

YINM

UVINM

YINS

UVINS

HINM

VINM HINS

VINS

VERTICAL AND

HORIZONTAL

COMPRESSION/

HORIZONTAL

EXPANSION

VERT. PEAKING

INPUT PROCESSING

SLAVE

VERTICAL AND

HORIZONTAL

COMPRESSION/

HORIZONTAL

EXPANSION

VERT. PEAKING

INPUT SYNC

CONTROLL ER

SPATIO

TEM PO RA L

NOISE

REDUCTION

LETTER

BOX

DETECTION

eDRAM

MAIN

MEMORY

CONTROLLER

Figure 2 Block diagram 2

LINE TO

BLOCK

CONVERSION

OUTPUT PROCESSING SLAVE

SCAN RATE CONVERSION

MOTION

ESTIMATION

FILM MODE DETEC TION

SCAN RATE CONVERSION

VERTICAL ZOOM

OUTPUT PROCESSING MASTER

eDRAM

VECTOR

MEMORY

BLOCK TO

LINE

CONVERSION

OUTPUT SYNC

CONTROLL ER

MUX

Block diagram

DISPLAY PROCESSING

DLTI DCTI

PEAKING

8:8: 8

INTERP OLA TION

TRIP LE

DAC

YOUT

UVOUT

HOUT VOUT

BLANK

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SDA 9415 - B13 Preliminary Data Sheet

4 Pin Description

Pin Diagram: P-MQFP-144-2

(top view)

N.C.

SDA

VSSL6

N.C. N.C.

N.C. VINM HINM

SYNCENM

VSSP5 UVINM0 UVINM1 UVINM2 UVINM3

UVINM4 UVINM5

VDDP4 UVINM6 UVINM7

YINM 0 YINM 1 YINM 2 YINM 3

VSSP4

N.C. YINM 4 YINM 5 YINM 6

YINM 7

UVINS0 UVINS1 UVINS2

UVINS3 UVINS4

UVINS5

VDDP3

N.C. N.C. N.C.

VSSL7

SCL

103

105

104

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

001

002

003

004

005

006

N.C.

VSSP3

UVINS6

UVINS7

VDDP5

102

007

CLKS

VDDA3

101

008

009

VSSA2

VSSA3

100

VDDA2

CLKM

099

010

YINS0

N.C.

VSSP6

098

UVOUT0

097

VSSL8

095

096

VSSL9

UVOUT1

093

094

SDA 9415

013

011

012

014

015

016

N.C.

YINS1

N.C.

YINS4

YINS3

YINS2

Pin Description

VOUT

N.C.

VDDP6

084

025

YINS6

UVOUT5

083

026

YINS7

UVOUT6

VSSP7

081

082

027

028

VDDL4

YOUT7

UVOUT4

UVOUT3

VSSL2

VDDL2

N.C.

UVOUT2

VDDE2

091

090

092

017

018

019

N.C.

VDDE1

N.C.

085

086

088

087

089

021

020

022

023

024

N.C.

VDDP2

VSSP2

YINS5

VSSE1

VDDL1

INTERLACED

BLANK

VSSL3

VDDL3

077

078

079

080

031

032

030

029

VSSL4

YOUT6

YOUT5

073

074

075

076

033

HINS

072

HOUT

071

CLKOUT

X1/CLKD

070

069

068

UVOUT7

067

YOU T0

066

VSSP8

065

VDDP7

064

YOU T1 YOU T2

063

062

VSSA1

061

VDDA1

060

VSSA5

059

VDDA5

058

UREF_I

057

RREF_I

056

VSSA4

055

VDDV

054

IV _O

053

IV Q_O

052

VDDY

051

IY_O

050

IYQ_ O

049

VDDU

048

IU_ O

047

IUQ _O

046

TES T

045

RESET

044

YOU T3

043

VDDP1

042

VSSP1

041

YOU T4

040

VINS

039

N.C.

038

N.C.

037

N.C.

034

035

036

PIN49415

N.C.

SYNCENS

Figure 3 Pin configuration

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SDA 9415 - B13 Preliminary Data Sheet

Table 1 Pin definitions and functions

Symbol Pin

Num.

VSSLx *) 19, 29, 79,

89, 94, 96, 103, 104

VDDLx 20, 28, 80,

88, 90

VSSPx 6, 22, 42, 66,

82, 98, 115, 129

VDDPx 21, 43, 65,

84, 102, 122, 141

VSSE1 19 S Supply voltage for embedded DRAM ( V

VDDEx 18, 90 S Supply voltage for embedded DRAM ( V

VSSAx 8, 56, 60, 62,

100

Input

Function

Outp.

S Supply voltage for digital logic parts ( V

S Supply voltage for pads ( V

S Supply voltage for analog PLL and for analog parts DAC ( V

= 0 V )

= 3.3 V )

= 0 V )

= 3.3 V )

= 0 V )

= 3.3 V )

Pin Description

= 0 V )

VDDAx 9, 59, 61,

101

YINM 0...7 125,...,128;

131,...,134

UVINM 0...7 116,...,121;

123;124

YINS 0...7 10,...,12;14;

16;24,...,26

UVINS 0...7 135,...,140;

4;5

RESET 45 I/TTL System reset. The RESET input is low active. In order to ensure

HINM 113 I/TTL

VINM 112 I/TTL

SYNCENM 114 I/TTL Synchronization enable input master channel

HINS 33 I/TTL

S Supply voltage for analog PLL and for analog parts DAC

( V

= 3.3 V )

I/TTL Data input Y master channel

I/TTL PD Data input UV master channel

I/TTL PD Data input Y slave channel

I/TTL PD Data input UV slave channel

correct operation a "Power On Reset" must be performed. The RESET pulse must have a minimum duration of two clock periods of the master (CLKM) and slave clock (CLKS), respectively.

H-Sync input master channel

V-Sync input master channel

H-Sync input slave channel

VINS 40 I/TTL

SYNCENS 32 I/TTL Synchronization enable input slave channel

SDA 105 IO I

V-Sync input slave channel

C-Bus data line

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SDA 9415 - B13 Preliminary Data Sheet

Table 1 Pin definitions and functions (continued)

Symbol Pin

Num.

SCL 106 I I

BLANK 78 O/TTL Blanking signal

VOUT 76 O/TTL V-Sync output

HOUT 72 O/TTL H-Sync output

INTERLACED 77 O/TTL Interlace signal for AC coupled vertical deflection

CLKM 99 I/TTL System clock master channel

CLKS 7 I/TTL System clock slave channel

X1 / CLKD 70 I/TTL Crystal connection / System clock display channel

X2 69 O/ANA Crystal connection

CLKOUT 71 O/TTL System clock output

TEST 46 I/TTL Test input, connect to V

YOUT7...0 27;30;31;41;

44;63;64;67

Input

Function

Outp.

C-Bus clock line

O/TTL Digital luminance output

for normal operation

Pin Description

UVOUT7...0 68;81;83;85;

87;92;93;97

IY_O 51 O/ANA Analog luminance output Y

IYQ_O 50 O/ANA Differential analog Y output, connect to V

VDDY 52 S Supply voltage for analog parts DAC ( V

IU_O 48 O/ANA Analog luminance output U

IUQ_O 47 O/ANA Differential analog U output, connect to V

VDDU 49 S Supply voltage for analog parts DAC ( V

IV_O 54 O/ANA Analog luminance output V

IVQ_O 53 O/ANA Differential analog V output, connect to V

VDDV 55 S Supply voltage for analog parts DAC ( V

UREF_I 58 I/ANA Analog reference voltage for DACs

RREF_I 57 Reference resistor for DACs

N.C. 1,2,3,13,15,

17,23,34,35, 36,37,38,39, 73,74,75,86, 91,95,107, 108,109, 110,111, 130,142, 143,144

O/TTL Digital chrominance output

for normal operation

= 3.3 V )

for normal operation

= 3.3 V )

for normal operation

= 3.3 V )

S: supply, I: input, O: output, TTL: digital (TTL) ANA: analog PD: pull down (switched on or off depending on I²C bus parameter FORMATM, FORMATS or SLAVECON)

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SDA 9415 - B13 Preliminary Data Sheet

*) x - placeholder for number

Pin Description

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SDA 9415 - B13 Preliminary Data Sheet

Pin Description

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SDA 9415 - B13 Preliminary Data Sheet

System description

5 System description

5.1 Introduction

The SDA 9415 is the first single-chip Micronas MEGAVISION® feature box including scan rate conversion and the necessary field memories, a second input channel for split screen applications like picture-and-picture and digital-to-analog converters. The SDA 9415 has three application modes: the SRC (Scan Rate Conversion) mode, the SSC (Split SCreen) mode and the MUP (MUlti Picture) mode.

The two input channels of the SDA 9415 are not equivalent. One input channel is always the so called “master” channel and one input channel is always the so called “slave” channel. Both channels are combined of the output side of the SDA 9415 in the “MUX” block. The master channel is always the "synchronization" master of both channels.

In the SRC mode the SDA 9415 can be used as a high performance scan rate converter. Scan rate conversion is done by a motion compensated algorithm known as Micronas VDU (Vector Driven Up conversion). In addition a high resolution frame based joint-linefree picture-and-picture (maximum approximately 1/9 picture) can be displayed. The figure below shows an example of the SRC mode.

Figure 4 Principles of SRC mode

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SDA 9415 - B13 Preliminary Data Sheet

System description

For this usage the 6 Mbit eDRAM core is separated in two luminance fields and two chrominance fields (either 4:2:0 or 4:1:1) and a memory area for luminance and chrominance fields (4:1:1) [maximum circa 1/9 picture] for picture-in-picture applications. The vector based scan rate conversion is possible for the master channel only.

For the SSC mode the 6 Mbit eDRAM core is split in two 3 Mbit areas, which are able to contain a maximum of two luminance fields and two chrominance fields (either 4:2:0 or 4:1:1). The figure below shows different applications (“Double window”, “Zoom-in-zoom- out”). In this case only a simple scan rate conversion (e.g. field doubling for interlaced conversion: AABB) for both output channels is possible.

Figure 5 Principles of SSC mode

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SDA 9415 - B13 Preliminary Data Sheet

System description

The MUP mode allows the combination of one life picture and a configuration of still pictures. The figure below shows an application. In this case only a simple scan rate conversion (e.g. field doubling for interlaced conversion: AABB or AAAA) is possible.

Figure 6 Principles of MUP mode

The behaviour of the master and the slave channel does not differ in general. Therefore for further description of the master and the slave channel the figures are also valid for both unless it is pointed out.

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SDA 9415 - B13 Preliminary Data Sheet

System description

5.2 Input sync controller (ISCM/ISCS)

Signals Pin number Description

HINM 27 horizontal synchronization signal (polarity programmable, I²C Bus

parameter 11h HINPOLM, default: high active)

VINM 26 vertical synchronization signal (polarity programmable, I²C Bus

parameter 11h VINPOLM, default: high active)

SYNCENM 28 enable signal for HINM and VINM signal, low active ("Input format

conversion (IFCM/IFCS)" on page 30)

HINS 77 horizontal synchronization signal (polarity programmable, I²C Bus

parameter 33h HINPOLS, default: high active)

VINS 78 vertical synchronization signal (polarity programmable, I²C Bus

parameter 33h VINPOLS, default: high active)

SYNCENS 76 enable signal for HINS and VINS signal, low active ("Input format

conversion (IFCM/IFCS)" on page 30)

Table 2 Input signals

The input sync controller derives framing signals from the H- and V-Sync for the input data processing. The framing signals depend on different I²C Bus parameters and mark the active picture area.

HINM

pixels per line

VINM

lines

per

field

(NAPIPDLM*4 +

NAPIPPHM+PD)*

CLKM

(APPLIPM*8)*CLKM

PD - Processing Delay

NALIPM + PD

(ALPFIPM*2)

inpar01

Figure 7 Input I²C Bus parameter

The distance between the incoming H-syncs in system clocks of CLKM/CLKS must be even.

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SDA 9415 - B13 Preliminary Data Sheet

I²C Bus parameter [Default value]

NALIPM [20]

NALIPS [20]

ALPFIPM [144]

ALPFIPS [144]

NAPLIPM NAPIPDLM [0] NAPIPPHM [0]

NAPLIPS NAPIPDLS [0] NAPIPPHS [0]

System description

Sub address Description

12h Not Active Line InPut Master defines the number of lines from

the V-Sync to the first active line of the field

34h Not Active Line InPut Slave defines the number of lines from

the V-Sync to the first active line of the field

10h Active Lines Per Field InPut Master defines the number of

active lines

32h Active Lines Per Field InPut Slave defines the number of active

lines

03h, 0Ch Not Active Pixels Per Line InPut Master defines the number of

pixels from the H-Sync to the first active pixel of the line. The number of pixels is a combination of NAPIPDLM and NAPIPPHM.

2Dh, 2Eh Not Active Pixels Per Line InPut defines the number of pixels

from the H-Sync to the first active pixel of the line. The number of pixels is a combination of NAPIPDLS and NAPIPPHS.

APPLIPM [180]

APPLIPS [180]

0Fh Active Pixels Per Line InPut Master defines the number of

active pixels

31h Active Pixels Per Line InPut Slave defines the number of active

pixels

Table 3 Input write I²C Bus parameter

Inside of the SDA 9415 a field detection block is necessary for the detection of an odd (A) or even (B) field. Therefore the incoming H-Sync H1 (delayed HINM/HINS signal, delay depends on NAPIPDLM/NAPIPDLS and NAPIPPHM/NAPIPPHS) is doubled (H2 signal). Depending on the phase position of the rising edge of the VINM/VINS signal an A (rising edge between H1 and H2) or B (rising edge between H2 and H1) field is detected. For proper operation of the field detection block, the VINM/VINS must be delayed depending on the delay of the HINM/HINS signal (H1). The figure below explains the field detection process and the functionality of the VINDELM/VINDELS I²C Bus parameter (inside the SDA 9415 the delayed VINM/VINS signal is called Vd and the detected field signal is called Ffd).

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CLKM

VINM

Ffd

VINM

(VINDELM * 128 + 1) *

Tclkm

(VINDELM * 128 + 1) *

Tclkm

Figure 8 Field detection and VINM delay

System description

Field 1(A)

Field 2(B)Ffd

I²C Bus parameter [Default value]

VINDELM [0]

VINDELS [0]

FIEINVM 1 : Field A=1 [0]: Field A=0

FIEINVS 1 : Field A=1 [0]: Field A=0

VCRMODEM [1]: on 0 : off

VCRMODES [1]: on 0 : off

Sub address Description

11h Delay of the incoming V-Sync VINM (must be adjusted

depending on the delay of the HINM signal)

33h Delay of the incoming V-Sync VINS (must be adjusted

depending on the delay of the HINS signal)

0Bh Inversion of the internal field polarity master

2Dh Inversion of the internal field polarity slave

0Bh In case of non standard interlaced signals (VCR, Play-

Stations) a filtering of the internal field signal has to be done (should also be used for normal TV signals)

2Dh In case of non standard interlaced signals (VCR, Play-

Stations) a filtering of the internal field signal has to be done (should also be used for normal TV signals)

Table 4 Input write I²C Bus parameter

In case of non-standard signals the field order is indeterminate (e.g. AAA... , BBB... , AAABAAAB..., etc.). Therefore a special filtering algorithm is implemented, which can be switched on by the I²C Bus parameter VCRMODEM/VCRMODES. It is recommended to set the I²C Bus parameter VCRMODEM=1. In other case (VCRMODEM=0) an additional

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System description

internal signal VTSEQM is generated. This signal level is high (VTSEQM=1), if at least the last to fields were identical. Due to the fixed storage places of the fields in the internal memory block, this information is necessary for the scan rate conversion processing ("Output sync controller (OSCM/S)" on page 81, it is recommended in case of VCRMODEM=0 to choose an adaptive operation mode).

The OPDELM I²C Bus parameter is used to adjust the outgoing V-Sync VOUT in relation to the incoming delayed V-Sync VINM. In case of SSC and MUP mode the recommended default value should not be changed.

I²C Bus parameter [Default value]

OPDELM [170]

Sub address Description

1Bh Delay (in number of lines) of the internal V-Sync (delayed

VINM) to the outgoing V-Sync (VOUT)

Table 5 Input write I²C Bus parameter

The internal line counter is used to determine the information about the standard of the incoming signal.

I²C Bus parameter Sub address Description

TVMODEM 7Bh TV standard of the incoming signal master:

1: NTSC 0: PAL

TVMODES 7Dh TV standard of the incoming signal slave:

1: NTSC 0: PAL

Table 6 Input read I²C Bus parameter

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System description

5.3 Input format conversion (IFCM/IFCS)

Signals Pin number Description

YINM0...7 39,40,41,42,44,45,46,47 luminance input master

UVINM0...7 30,31,32,33,34,35,37.38 chrominance input master

YINS0...7 61,62,63,64,65,71,72,73 luminance input slave

UVINS0...7 48,49,50,51,52,53,55,56 chrominance input slave

Table 7 Input signals

The SDA 9415 accepts at the input side the sample frequency relations

of Y : (B-Y) : (R-Y): 4:2:2 and CCIR 656.

Data Pin

CCIR 656 FORMATM = 1X

FORMATM = 01

4:2:2 Parallel

FORMATM = 00

YINM7 U

YINM6 U

YINM5 U

YINM4 U

YINM3 U

YINM2 U

YINM1 U

YINM0 U

UVINM7 U

UVINM6 U

UVINM5 U

UVINM4 U

UVINM3 U

UVINM2 U

UVINM1 U

UVINM0 U

Table 8 Input data formats

: X: signal component a: sample number b: bit number

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System description

In case of CCIR 656 three modes are supported (FORMATM/FORMATS=11 means full CCIR 656 support, including H-, V-Sync and Field signal, FORMATM/FORMATS=01 means only data processing, H- and V-Sync have to be added separately according PAL/NTSC norm, FORMATM/FORMATS=10 means only data processing, H- and Vsync have to be added separately according CCIR656-PAL/NTSC norm). The representation of the samples of the chrominance signal is programmable as positive dual code (unsigned, I²C Bus parameter TWOINM/TWOINS=0) or two's complement code (TWOINM/TWOINS=1, "I²C Bus" on page 123, I²C Bus parameter 0Bh,2Dh). Inside the SDA 9415 all algorithms assume positive dual code.

FORMATM/ FORMATS

00 PAL/NTSCPAL/NTSC4:2:2 4:2:2

01 (CCIR 656 only data)

10 CCIR 656 CCIR 656 CCIR 656 x

HINS/HINS VINM/VINS YINM/YINS UVINM/UVINS

PAL/NTSC PAL/NTSC CCIR 656 x

11 (full CCIR 656) x x CCIR 656 x

Table 9 Input sync formats

The amplitude resolution for each input signal component is 8 bit, the maximum clock frequency is 27 MHz. Consequently the SDA 9415 is dedicated for application in high quality digital video systems.

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System description

The Figure 9 shows the generation of the internal H- and V-syncs in case of full CCIR 656 mode. The H656 sync is generated after the EAV. The V656 and F656 signals change synchronously with the EAV timing reference code.

CLK1 (27 MHz)

CCIR 656 interface

YIN

CLK1 (27 MHz)

YIN

H656

V656 (e.g.)

F656 (e.g.)

SAVEAV

288 Tclk1(PAL)

276 Tclk1(NTSC)

1728 Tclk1(PAL)

1716 Tclk1(NTSC)

EAV x x EAVx xSAV x

u0 y0 v0 y1 u2 y3

EAV

11111111 00000000 00000000 1FV1P3P2P1P

MSB LSB

SAV

11111111 00000000 00000000 1FV0P3P2P1P

F = 0 during field 1(A) F = 1 during field 2(B)

V = 0 elsewhere

V = 1 during field blanking

Figure 9 Explanation of 656 format

The Figure 10 explains the functionality of the SYNCENM/SYNCENS signal. The SDA 9415 needs the SYNCENM/SYNCENS (synchronization enable) signal, which is used to gate the YINM/YINS, UVINM/UVINS as well as the HINM/HINS and the VINM/VINS signal. This is implemented for frontends which are working with 13.5 MHz and a large output delay time for YINM/YINS, UVINM/UVINS, HINM/HINS and VINM/VINS (e.g. Micronas VPC32XX, output delay: 35 ns). For this application the half system clock CLKM/CLKS (13.5 MHz) from the frontend should be provided at this pin. In case the frontend is working at 27.0 MHz with sync signals having delay times smaller than 25 ns, this input can be set to low level (SYNCENM/SYNCENS=

) (e.g. Micronas SDA 9206,

output delay: 25 ns). Thus the signals YINM/YINS, UVINM/UVINS, HINM/HINS and VINM/VINS are sampled with the CLKM/CLKS system clock when the SYNCENM/ SYNCENS input is low.

The Figure 10 shows the gated inputs signals YINMen, UVINMen, HINMen and VINMen.

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SYNCENM

YINM

UVINM

YINMen

UVINMen

HINM/VINM

HINMen/VINMen

CLKM

y0 y1 y2 y3

u0 v0 u2 v2

y0 y1 y2 y3

u0 v0 u2 v2

System description

Figure 10 SYNCENM/SYNCENS signal

The Figure 11 shows the input timing and the functionality of the NAPIPDLM/NAPIPDLS and NAPIPPHM/NAPIPPHS I²C Bus parameter in case of CCIR 656 and 4:2:2 parallel data input format for one example. The signals HINMint, YINMint and UVMint are the internal available sampled input signals.

CLKM

HINM

HINMint

CCIR 656 interface

YINM

(NAPIPDLM* 4 + NAPIPPHM + 7) * Tclkm

=(0 * 4 + 2 + 7) * Tclkm = 9 Tclkm (e.g.)

YINMint

UVINMint

4:2:2 interface

YINM

UVINM

YINMint

UVINMint

(NAPIPDLM* 4 + NAPIPPHM + 7) * Tclkm

=(0 * 4 + 3 + 7) * Tclkm = 10 Tclkm (e.g.)

Figure 11 Input timing

u0 y0 v0 y1 u2 y2 v2 y3xxx

y0 y1 y2 y3xxx

u0 v0 u2 v2xxx

u0 v0

u0 v0 u2 v2

y0 y1 y3 y4

u0 v0 u2 v2

u4 y4

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System description

5.4 Input signal processing

The Figure 12 shows a detailed block diagram of the input processing blocks. The input signal can be vertically and horizontally compressed or horizontally expanded by a large number of factors. Furthermore the input signal can be processed by different noise reduction algorithms to reduce the noise in the signal. The noise measurement block determines the noise level of the input signal. The letter box detection block finds the start and end line of letter box pictures. The information can be used by a µC to calculate zooming factors and to control the IC for resizing the picture for a full screen display on 16:9 tubes.

DELM

YINM

UVINM

Letter

box

detection

Delay

-3/+4

NMLINE, NMALG NOISEME

Noise measurement

Line

memories

MASTER

Vertical and

horizontal

compression/

expansion

SNRON

Spatial noise

reduction

NRON

Temporal

reduction

noise

YM from Memory

YM to Memory

CM to Memory

CM from Memory

YINS

UVINS

Delay

-3/+4

DELS

Line

memories

SLAVE

Vertical and

horizontal

compression/

expansion

bdldr01

YS to Memory

CS to Memory

Figure 12 Block diagram of input processing blocks

The different blocks and the corresponding I²C Bus parameters will be described now in more detail.

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System description

5.4.1 Adjustable delay

It is possible to adjust the luminance signal in relation to the chrominance signal in (CLKM/CLKS) steps. For further processing it is important, that the luminance signal and the chrominance signal are adjusted. Adjustment may be necessary, if the luminance and chrominance signal generated by the frontend processor are not adjusted.

DELM/DELS (04h,026h) Delay between luminance and chrominance data in

steps of 27.0 MHz (CLKM/CLKS)

0-3

1-2

2-1

4+1

5+2

6+3

7+4

Table 10 DELM/DELS I²C Bus parameter

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System description

5.4.2 Vertical and horizontal compression (VHCOMM/VHCOMS)

The Figure 13 shows the block diagram of the VHCOMM and VHCOMS block. The VHCOMM and VHCOMS block are able to compress the picture in horizontal and vertical direction continuously. The minimal step size in vertical direction is two lines, the minimal step size in horizontal direction is four pixels. The figure below shows also the functionality and the formula, which shows the relation between the number of input lines (pixels) and output lines (pixels). In horizontal direction an expansion is also possible. Panorama mode in horizontal direction will be supported.

YUVIN

INTVM, INTVS,

DEZVM, DEZVS,

CHFILM, CHFILS

Vertical

compression

4*APPLIPM

4*APPLIPS

pixels (CLKM/2)

YPEAKM, CPEAKM,

YPEAKS, CPEAKS

Vertical

peaking

4*APPLIPM

4*APPLIPS

pixels (CLKM/2)

INTHM, INTHS,

DEZHM, DEZHS

Horizontal

compression/

expansion

vhcombd

YUVOUT

4*APPLM 4*APPLS

pixels (CLKM/2)

2*ALPFIPM,

2*ALPFIPS

lines

Number of output lines = (Number of input lines) * 512 / (512+INTVM) * 1/(DEZVM) INTVM = 0, ..., 511;

Number of output lines = (Number of input lines) * 2 * 2048 / (INTHM) * 1/(DEZHM)

Figure 13 Block diagram of VHCOMM/VHCOMS

2*ALPFM 2*ALPFS

lines

DEZVM = {1, 2, 4, 8, 16}

INTHM = 2048, ... , 8191;

DEZHM = {1, 2, 4, 8, 16}

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System description

5.4.2.1 Vertical compression and peaking

The overall reduction of the vertical compression block can be calculated by the formula:

-------------------- ---------------------

512

512 INTVM+ΕΦ

The user must specify the vertical input picture size (defined by I²C Bus parameter ALPFIPM/ALPFIPS) and the vertical output picture size (defined by I²C Bus parameter APPLM/APPLS) as well as the I²C Bus parameter INTVM/INTVS (I²C Bus parameter, 09h,0Ah,2Bh,2Ch) and DEZVM/DEZVS (I²C Bus parameter, 0Ah,2Ch), which can be calculated with the algorithm listed below (C-code).

intV, dezV: variables

for( intV=2*ALPFM/S, dezV=1; intV<=2*ALPFIPM/S; intV*=2, dezV*=2 )

;

------------------- ---

DEZVM

intV = ((512*2*ALPFIPM/S*2+intV/2)/intV);

dezV/=2;

if(dezV>16)

{

intV=intV*dezV/16;

dezV=16;

}

INTVM/S=intV-512;

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Vertical line size 2*ALPFM/S (2*ALPFIPM/S=288)

288 0 1/1 largest size, bypass

216 171 1/1

192 256 1/1 Double window

145 505 1/1

144 0 2/4

96 256 2/4 PIP (1/3 picture)

73 497 2/4

72 0 4/5

36 0 8/6

INTVM/S dezV/DEZVM/S Comment

System description

recommended DEZVM/ DEZVS=0

18 0 16/7

10 409 16/7 smallest size

Table 11 Examples of vertical filter adjustment

dezV DEZVM / DEZVS

16 111

8 110

4 101

2 100

1 001

Table 12 Conversion table between dezV and DEZVM / DEZVS

The vertical compression block can be switched off by setting DEZVM/DEZVS equal “0” and INTVM/INTVS=0. In this case it is possible to switch on a low pass filter for the chrominance data path by the I²C Bus parameter CHFILM/CHFILS (I²C Bus parameter, 03h, 25h). If CHFILM/CHFILS is equal to “0” or “2” the vertical filter for the chrominance is switched off. If CHFILM/CHFILS is equal to “1” or “3” the vertical filter for the chrominance is switched on (Table 17 "Input write I²C Bus parameter CHFILM/ CHFILS" on page 42).

In addition a vertical peaking of the input signal is possible.

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I²C Bus parameter 0 (minimum value) 3 (maximum value)

YPEAKM/YPEAKS peaking off maximum peaking factor

CPEAKM/CPEAKS peaking off maximum peaking factor

System description

Table 13 Input write I²C Bus parameter YPEAKM/YPEAKS/CPEAKM/CPEAKS

I²C Bus parameter

INTVM 09h,0Ah Interpolation factor for vertical compression master

DEZVM 0Ah Decimation factor for vertical compression master

INTVS 2Bh,2Ch Interpolation factor for vertical compression slave

DEZVS 2Ch Decimation factor for vertical compression master

Sub address Description

YPEAKM 0Ah Vertical peaking factor for luminance signal master

CPEAKM 0Ah Vertical peaking factor for chrominance signal master

YPEAKS 2Ch Vertical peaking factor for luminance signal slave

CPEAKS 2Ch Vertical peaking factor for chrominance signal slave

ALPFM 0Dh Number of active lines per field after vertical compression

master

ALPFS 2Fh Number of active lines per field after vertical compression

slave

CHFILM 03h Chrominance filter master channel on/off

CHFILS 25h Chrominance filter slave channel on/off

Table 14 Input write I²C Bus parameter

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5.4.2.2 Horizontal compression/expansion and panorama mode

The overall reduction of the horizontal compression block can be calculated by the formula:

2048

--------------------

INTHM

The user must specify the horizontal input picture size (defined by the I²C Bus parameter APPLIPM/APPLIPS) and the horizontal output picture size (defined by the I²C Bus parameter APPLM/APPLS) as well as the I²C Bus parameter INTHM/INTHS (I²C Bus parameter, 07h, 08h, 29h, 2Ah) and DEZHM/DEZHS (I²C Bus parameter, 08h, 2Ah), which can be calculated with the algorithm listed below (C-code).

intV, dezV: variables

----------------------

DEZHM

System description

for( intH=4*APPLM/S, dezH=1; intH<=4*APPLIPM/S; intH*=2, dezH*=2 )

;

intH = ((2048*4*APPLIPM/S*2+intH/2)/intH);

if( dezH>16)

{

intH= intH*dezH/16;

dezH=16;

}

INTHM/S = intH

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Horizontal pixel size (related to CLKM/2) 4*APPLM (4*APPLIPM=720)

1440 2048 1/1 largest size, only 720 will be stored

724 4073 1/1 largest size, only 720 will be stored

720 2048 2/4 bypass recommended DEZHM/DEZHS=0

540 2731 2/4 4:3 picture on 16:9 tube

364 4050 2/4

360 2048 4/5 Double window

184 4007 4/5

180 2048 8/6

92 4007 8/6

90 2048 16/7

intH dezH/

DEZHM/S

Comment

System description

48 3840 16/7

24 7680 16/7 smallest size

Table 15 Examples of horizontal filter adjustment

dezH DEZHM/S

16 111

8110

4101

2100

1001

Table 16 Conversion table between dezH and DEZHM/DEZMS

The horizontal compression/expansion block can be switched off by setting DEZHM/ DEZHS equal “0” and INTHM/INTHS=2048. In this case it is possible to switch on a low pass filter for the chrominance data path by the I²C Bus parameter CHFILM/CHFILS (I²C Bus parameter, 03h,25h). If CHFILM/CHFILS is equal to “0” or “1” the horizontal filter for the chrominance is switched off. If CHFILM/CHFILS is equal to “2” or “3” the horizontal filter for the chrominance is switched on. The table below shows the different settings of CHFILM/S.

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CHFILM/CHFILMS Vertical low pass filter

(only valid for DEZVM/DEZVS=0)

11 Vertical filter on Horizontal filter on

10 Vertical filter off Horizontal filter on

01 Vertical filter on Horizontal filter off

00 Vertical filter off Horizontal filter off

Horizontal low pass filter (only valid for DEZHM/DEZHS=0)

System description

Table 17 Input write I²C Bus parameter CHFILM/CHFILS

In case of panorama mode the compression/expansion factor varies over one line. The figure below shows some examples.

Compr es s io n

PANAST+ 1

1.0

Expansion

Figure 14 Principles of panorama mode

Different settings of the I²C Bus parameters INTHM/INTHS and DEZHM/DEZHS are necessary. The table below defines the settings:

PANAON dezH intH

0 DEZHM/DEZHS INTHM

11 INTHM

(4096 recommended)

Table 18 Filter I²C Bus parameter in case of PANAON=1

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I²C Bus parameter 0 (minimum value) 15 (maximum value)

PANAST slight panorama strong panorama

System description

Table 19 I²C Bus parameter PANAST in case of PANAON=1

I²C Bus parameter Sub address Description

INTHM 07h,08h Interpolation factor for horizontal

compression/expansion master

DEZHM 08h Decimation factor for horizontal compression/

expansion master

INTHS 29h,2Ah Interpolation factor for horizontal

compression/expansion slave

DEZHS 2Ah Decimation factor for horizontal compression/

expansion slave

APPLM 0Eh Number of active pixels per line in the input

data stream after horizontal compression/ expansion master

APPLS 30h Number of active pixels per line in the input

data stream after horizontal compression/ expansion slave

PANAON 1Ah Horizontal panorama mode on/off

PANAST 1Ah Gradient of horizontal panorama mode

Table 20 Input write I²C Bus parameter

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System description

5.4.3 Noise reduction

The figure below shows a block diagram of the spatial and temporal motion adaptive noise reduction (first order IIR filter). The spatial noise reduction is only performed on the luminance signal. The structure of the temporal motion adaptive noise reduction is the same for the luminance as for the chrominance signal.

SNRON

YIN

TNRCLY, TNRHOY, TNRKOY, TNRVAY,

TNRFIY,

NRON

TNRC LC, TNRHOC, TNRKOC, TNRVAC,

TNRFIC,

NRON

UVIN

Spatial

noise

reduction

YS NR

Motio n

detector

Motio n

detector

DUV

UVS NR

KUV

TNRSEL

UV1

Field

delay

Frame

delay

Frame

delay

Field

delay

1 0

DTNRON

YOU T

UVOUT

0 1

DTNRON

nr01

Figure 15 Block diagram of noise reduction

5.4.3.1 Spatial noise reduction

Normally a spatial noise reduction reduces the resolution due to the low pass characteristic of the used filter. Therefore the spatial noise reduction of the SDA 9415 works adaptive on the picture content. The low pas filter process is only executed on a homogeneous area.

I²C Bus parameter Sub address Description

SNRON 1: on 0: off

Table 21 Input write I²C Bus parameter

44 Micronas

1Ah Spatial noise reduction of luminance signal

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SDA 9415 - B13 Preliminary Data Sheet

System description

5.4.3.2 Motion adaptive temporal noise reduction

The equation below describes the behaviour of the temporal motion adaptive noise reduction filter. The same equation is valid for the chrominance signal. Depending on the motion in the input signal, the K-factor Ky (Kuv) can be adjusted between 0 (no motion) and 15 (motion) by the motion detector. The K-factor for the chrominance filter can be either Ky (output of the luminance motion detector, TNRSEL=0) or Kuv (output of the chrominance motion detector, TNRSEL=1). For the luminance and chrominance signal the delay of the feed back path can be either a field delay (DTNRON=1) or a frame delay (DTNRON=0) (block diagram of noise reduction).

Equation for temporal noise reduction (luminance signal)

1Ky+

YOUT



-----------------

YSNR YR–ΕΦYR+=

Equation for temporal noise reduction (chrominance signal)

1K+



UVOUT

-------------

UVSNR UV1–ΕΦUV1 K;+ Ky Kuv;ΕΦ==

(compare "Block diagram of noise reduction" on page 44)

The Figure 16 shows the motion detector in more detail. Temporal noise reduction can be switched off by NRON (NRON=0). The I²C Bus parameter TNRFIY/C switches between a fixed noise reduction K-factor TNRVAY/C (TNRFIY/C=0) or a motion adaptive noise reduction K-factor (TNRFIY/C=1).

DY/UV

Motion

detection

TNRCLY/C+1

Motion

TNRKOY/C+1

LUT

TNRHOY/C

TNRFIY/C

TNRVAY/C

MUX

NRON

MUX

Ky/uv

nr01

Figure 16 Block diagram of motion detector

In case of adaptive noise reduction the K-factor depends on the detected “Motion” (see Figure 16). The “Motion”-Ky/Kuv characteristic curve (LUT) is fixed inside the SDA 9415, but the characteristic curve can be changed by two I²C Bus parameters: TNRHOY/ C and TNRKOY/C. TNRHOY/C shifts the curve horizontally and TNRKOY/C shifts the

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System description

curve vertically. For a fixed characteristic curve, the sensitivity of the motion detector is adjustable by TNRCLY/C.

TNRKOY/C=7

Ky/Kuv

TNRKOY/C

TNRHOY/C=0

TNRKOY/C=-1 TNRHOY/C=0

TNRKOY/C=-8 TNRHOY/C=0

Ky/Kuv

Motion

51015202530

nr02

TNRKOY/C=-1

TNRHOY/C=15

TNRKOY/C=-1 TNRHOY/C=0

TNRHOY/C

TNRKOY/C=-1

TNRHOY/C=-15

Motion

nr03

51015202530

Figure 17 LUT for motion detection

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I²C Bus parameter

TNRVAY/C strong noise reduction

0 (minimum value) 15 (maximum value)

no noise reduction

(not motion adaptive, Ky/Kuv=0)

(not motion adaptive, Ky/Kuv=15)

Table 22 I²C Bus parameter TNRVAY/C

I²C Bus parameter Range

TNRHOY/C -32, ... , 31

TNRKOY/C -8, ..., 7

Table 23 I²C Bus parameter TNRHOY/C and TNRKOY/C

System description

I²C Bus parameter

TNRCLY/C maximum sensitivity for motion

0 (minimum value) 15 (maximum value)

-> strong noise reduction

Table 24 I²C Bus parameter TNRCLY

minimum sensitivity for motion

-> weak noise reduction

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I²C Bus parameter Sub address Description

NRON 1: on 0: off

TNRSEL 1: separate 0: luminance motion detector

DTNRON 1: field 0: frame

TNRFIY/C 1: off 0: on

TNRVAY/C 17h Fixed K-factor for temporal noise reduction of

TNRHOY/C 18h/19h Horizontal shift of the motion detector characteristic

1Ah Temporal Noise Reduction of Luminance and

Chrominance On (SRC-Mode)

18h Switch for motion detection of temporal noise

reduction of chrominance signal

1Ah Delay for temporal noise reduction of luminance and

chrominance signal

18h/19h Switch for fixed K-factor value defined by TNRVAY/C

luminance/chrominance

System description

TNRKOY/C 16h Vertical shift of the motion detector characteristic

TNRCLY/C 15h Classification of temporal noise reduction

Table 25 Input write I²C Bus parameter

5.4.4 Noise measurement

The noise measurement algorithm can be used to change the I²C Bus parameters of the temporal noise reduction processing depending on the actual noise level of the input signal. This is done by the I²C Bus controller which reads the NOISEME value, and sends depending on this value different I²C Bus parameter sets to the temporal noise reduction registers of the SDA 9415. The NOISEME value can be interpreted as a linear curve from no noise (0) to strong noise (30). Value 31 indicates an overflow status and can be handled in different ways: strong noise or measurement failed.

Two measurement algorithms are included, which can be chosen by the I²C Bus parameter NMALG. In case NMALG=1 the noise is measured during the vertical blanking period in the line defined by NMLINE. For NMALG=0 the noise is measured during the first active line. In the latter case the delay of the noise reduction algorithm must be set to the frame difference value (DTNRON=0, I²C Bus sub address 1Ah). In both cases the value is determined by averaging over several fields.

The Figure 18 shows an example for the noise measurement. The NMLINE I²C Bus parameter determines the line, which is used in the SDA 9415 for the measurement. In case of VINDEL=0 and NMLINE=0 line 3 of the field A and line 316 of the field B is

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System description

chosen. In case of VINDEL=0 and NMLINE=3 line 6 of the field A and line 319 of the field B is chosen.

Field1 (A)

625624623

H-sync

V-sync

VINDEL=0

NMLINE=0

NMLINE=3

123456

Measure

Field2 (B)

313-1 314-2 315-3 316-4 317-5 318-6 319-7312311310

H-sync

V-sync

VINDEL=0

NMLINE=0

NMLINE=3

PAL

Figure 18 Example of noise measurement

I²C Bus parameter

NMALG 14h Noise measurement algorithm

Sub address Description

1: measurement during vertical blanking period (measure line can be defined by NMLINE) 0: measurement in the first active line

Measure

NM01

NMLINE 14h Line for noise measurement (only valid for NMALG=1)

Table 26 Input write I²C Bus parameter

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I²C Bus parameter Sub address Description

NOISEME 7Ah Noise level of the input signal: 0 (no noise), ... , 30 (strong

noise) [31 (strong noise or measurement failed)]

NMSTATUS 7Ch Signals a new value for NOISEME

1: a new value can be read 0: current noise measurement has not been updated ("I²C Bus" on page 123)

System description

Table 27 Input read I²C Bus parameter

5.4.5 Letter box detection

The Figure 19 shows the display of a 4:3 letter box source on 16:9 tube. Black bars on the top and bottom as well as on the right and on the left are visible. It is possible by vertical and horizontal expansion to display the picture on the whole tube. Therefore only the first line (Start Line of Active Area - SLAA) and the last line (End Line of Active Area

- ELAA) of the active area must be known. The letter box detection algorithm detects SLAA and ELAA. Both I²C Bus parameters can be read out via I²C Bus. The µC of the TV chassis can use both values to calculate the corresponding zoom factor for the vertical expansion.

SLAA

Vertical and horizontal

expansion

ELAA

lbd

Figure 19 Principle of letter box detection

The Figure 20 shows the block diagram of the letter box detection. The letter box algorithm processes only the luminance data. Each incoming field is processed. The default value of SLAA is NALPFIPM+PD and of ELAA is 2*ALPFIPM+NALPFIPM+PD-1 (PD - Processing Delay), which means no letter box format source material.

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TH_AA TH_LB

TH_DN_BN

YINM

Histogram

Line

Type

Decision

Processing

Start/End-

line

Decision

Reliability

Evaluation

TH_MUNSL, TH_AUNS

TH_ALB, TH_MA_AA

System description

SLAA

Status_SLAA

ELAA

Status_ELAA

RELY

lbdbd

Figure 20 Block diagram of letter box detection

Each line of the input picture will be assigned to one of three line types (LT) by the “Histogram” and “Line Type decision” block. The figure below shows in detail the functionality of both blocks. The “Histogram” block counts the amount of pixels (BC), which are larger or equal 2*TH_DN_BN (I²C Bus parameter, 1Ch). Depending on the counter value the line is assigned to one of the three line types by the “Line Type Decision” block. The I²C parameter TH_AA and TH_LB can be used to influence the result of the “Line Type Decision” block.

Line Type (LT) Priority BC

AA 1 >= 4 * TH_AA

LB 2 < 4 * TH_LB

UNS 3 < 4 * TH_AA and >= 4 * TH_LB

Table 28 Line Type Decision of LBD

The line type AA marks lines which belong to an active area, the line type LB marks lines which belong to a letter box area (maybe including logos, subtitles) and the line type UNS marks lines which could not assigned with security to one of both line types mentioned before.

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Pixel

Value

2 *

TH_DN_BN

Histogram

. . . . . . . . .

. . .

TH_DN_BN (I²C bus parameter)

line

Amount of Pixels

> 2*TH_DN_BN

Line Type Decision

APPLI PM*4

4 * TH_AA

4 * TH_LB

lbdHLD

System description

UNS

Figure 21 Histogram and line type decision

Based on the line types the first line of the active area (SLAA, I²C parameter 78h) and the last line of the active area (ELAA, I²C parameter 79h) is determined. Furthermore the information about reliability of the SLAA and ELAA value is determined. The reliability information is readable by I²C Bus of the parameters STATUS_SLAA and STATUS_ELAA. If STATUS_SLAA/STATUS_ELAA is equal “1” the SLAA/ELAA value is reliable, otherwise the SLAA/ELAA value is not reliable.

In addition a global reliability signal RELY exists, which is also readable by I²C Bus. The results of the letter box detection are reliable, if the RELY signal is read as “1”. The “Reliability evaluation” block determines the RELY signal, which can be influenced by the I²C Bus parameter TH_MUNSL, TH_AUNS and TH_ALB. The table below explains the generation of the RELY signal. The thresholds TH_MUNSL, TH_AUNS and TH_ALB are compared with internal counter values UNSLENGTH, UNSAMOUNT and LBAMOUNT, respectively. If one of the three conditions is true, the RELY signal is set to not reliable. UNSLENGTH contains the maximum length of consecutive lines with the line type UNS. UNSAMOUNT contains the amount of lines with the line type UNS and LBAMOUNT contains the amount of lines with the line type LB.

RELY

0 (not reliable) UNSLENGTH > 16 * TH_MUNSL or UNSAMOUNT > 16 * TH_AUNS or

LBAMOUNT > 16 *TH_ALB

1 (reliable) otherwise

Table 29 Evaluation of the reliability signal RELY

The I²C Bus parameter TH_MA_AA can be used to force the SLAA and ELAA value to their default values. Therefore the amount of active area line types AA is counted in the

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System description

upper half of the input picture (AAFH) and the lower half of the input picture (AASH). If one of both counter values is greater as 2*TH_MA_AA + 112, the SLAA and ELAA I²C Bus parameters are set to their default values.

Output signals

SLAA=NALPIPM+PD

(AAFH or AASH) >= 2 * TH_MA_AA + 112 ELAA=2*ALPFIPM+SLAA-1 Status_SLAA=TRUE Status_ELAA=TRUE

no change of the values otherwise

Table 30 Correction of “start/end-line decision filter” block

It is possible to make the results of the letter box detection visible on screen in real time to optimize the I²C Bus parameters. The figure below explains the different possibilities. The I²C Bus parameter VOLBD can be used to switch on (VOLBD=1) or off (VOLBD=0) the visibility function.

PANATV

this is a

letter box

PANATV

this is a

letter box

SLAA,

Status_SLAA=FALSE

RELY=FALSE

ELAA,

Status_ELAA=FALSE

SLAA,

Status_SLAA=FALSE

RELY=TRUE

ELAA,

Status_ELAA=FALSE

PANATV

this is a

letter box

PANATV

this is a

letter box

Figure 22 Visibility of letter box detection I²C Bus parameters

SLAA,

Status_SLAA=TRUE

RELY=FALSE

ELAA,

Status_ELAA=TRUE

SLAA,

Status_SLAA=TRUE

RELY=TRUE

ELAA,

Status_ELAA=TRUE

lbdvis

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I²C Bus parameter [default]

TH_DN_BN [15]

TH_LB [12]

TH_ALB [6]

TH_AA [50]

TH_MUNSL [5]

TH_AUNS [7]

TH_MA_AA [14]

System description

Sub address Description

1Ch Darkness Brightness threshold

1Ch,1Dh Letter box threshold

1Dh Amount of letter box threshold

1Eh Active area threshold

1Fh Maximum length of insecure threshold

1Fh Amount of letter box and insecure threshold

20h Maximum amount of active area threshold

VOLBD [0]

20h Makes result of letter box detection visible on screen

1: on 0: off

Table 31 Input write I²C Bus parameter

I²C Bus parameter

SLAA 78h First line of active area = 2 * SLAA

ELAA 79h Last line of active area = 2 * ELAA

STATUS_SLAA 7Bh Status of SLAA

STATUS_ELAA 7Bh Status of SLAA

RELY 7Bh Reliability signal:

LBDSTATUS 7Ch Signals new values for letter box detection

Sub address Description

1: SLAA is reliable 0: SLAA is not reliable

1: ELAA is reliable 0: ELAA is not reliable

1: All values of letter box detection are reliable 0: All values of letter box detection are not reliable

1: new values can be read 0: current letter box detection measurement not finalized ("I²C Bus" on page 123)

Table 32 Input read I²C Bus parameter

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5.5 Clock concept

Signals Pin number Description

CLKM 18 System clock input master channel

CLKS 58 System clock input slave channel

X1/CLKD 2 System clock input display channel

Table 33 Input signals

Signals Pin number Description

CLKOUT 3 Clock output

Table 34 Output signals

System description

The SDA 9415 supports different clock concepts. The Figure 24 shows a typical application of the SDA 9415. The frontend clock is connected to CLKM input. The second frontend clock is connected to CLKS input. The CLKOUT pin is connected to the backend and the X1/CLKD input is connected to a crystal oscillator. The Figure 23 explains the clock switch, which may be used for the separate modes (see also Table 37 "Ingenious configurations of the HOUT and VOUT generator" on page 84).

CLKS

CLKM

X1/CLKD

CLKMDEN

PLLS

PLLM

PLLD

CLKS_pll

CLKM_pll

CLKD_pll

clock3

CLKOUT

Figure 23 Clock concept of SDA 9415

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CVBS

Analog

colour

decoder

Analog

colour

decoder

SYNC

SDA 9206

ABAC US

SDA

9206

ABACUS

YUV IN M

HINM

VINM

CLKM =

YUV IN S

HINS

VINS

CLKS =

27 MHz

SDA

9415

DAEDALUS

VOUT

HOUT

CLKOUT

System description

SDA 9380

Deflection

controller

RGB

processing

APPLIK01

H-Drive

V-Drive

E/W

Figure 24 Application for SDA 9415

CLKMDEN (5Fh) PLLD input

0CLKM

1X1/CLKD

Clock Used in block

CLKM_pll ISCM, IFCM, VHCOMM, TSNR, LBD, LM, I²C

CLKS_pll ISCS, IFCS, VHCOMS, LM, I²C

CLKD_pll OSCM/S, ME, SRCM, SRCS, ED, MC, LM, DLTI, DCTI, Peaking, DAC, I²C

Table 35 Clock concept switching matrix

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I²C Bus parameter

PLLMOFF 1: off 0: on

PLLMRA 00h PLLM range, only for test purpose

PLLSOFF 1: off 0: on

PLLSRA 22h PLLS range

PLLDOFF 1: off 0: on

PLLDRA 5Fh PLLD range

CLKOUTON 1: enabled 0: disabled

Sub address Description

00h PLLM master channel on or off, only for test purpose

22h PLLS slave channel on or off, only for test purpose

5Fh PLLD display channel on or off, only for test purpose

5Fh Output of system clock CLKOUT

System description

CLKMDEN 1: X1/CLKD 0: CLKM

5Fh Input clock for PLLD

Table 36 Input write I²C Bus parameter

5.6 Application modes and memory concept

5.6.1 Introduction

The Main Memory of the SDA 9415 has an overall capacity of 6 Mbit. It is divided into two identical and independent 3 Mbit parts.

The Main Memory has 2 completely independent data inputs (master and slave channel) to enable a multitude of PIP features. In general the channels are asynchronous having 2 separate clock PLLs (CLKM, CLKS). Reading of master and slave data for display is performed using a third asynchronous clock (CLKD). In this way a decoupling of input and output clocks is achieved.

The Main Memory supports different operation modes of the SDA 9415 by adapted data configurations. The different modes are defined by the I²C Bus parameter MEMOP (I²C Bus sub address 53h).

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MEMOP Memory operation mode

00 SRC-Mode (Sample Rate Conversion)

01 SSC-Mode (Split screen)

10 MUP-Mode (Multi picture)

11 not defined

System description

Table 37 Definition of MEMOP

In SRC operation mode the capacity to store 2 fields of the luminance and chrominance components of the master channel is supplied (4:1:1 or 4:2:0 format, I²C Bus parameter CHRFORM/CHRFORS, 12h/34h).

CHRFORM Data format

00 4:1:1

01 4:2:0

1X reserved

CHRFORS Data format

04:1:1

14:2:0

Table 38 Definition of CHRFORM/CHRFORS

The Figure 25 shows the differences between the 4:1:1, 4:2:2 and 4:2:0 data format.

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4:2:2

1. line

2. line

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

U0 U2 U4 U6

V0 V2 V4 V6

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

U0 U2 U4 U6

V0 V2 V4 V6

3. line

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

U0 U2 U4 U6

V0 V2 V4 V6

4:1:1

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

U0 U4

V0 V4

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

U0 U4

V0 V4

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

U0 U4

V0 V4

Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

System description

4:2:0

U0 U2 U4 U6

V0 V2 V4 V6

U0 U2 U4 U6

V0 V2 V4 V6

dataform

Figure 25 Supported data formats

Additionally 3 fields of a decimated picture of the slave channel with the size of up to 1/ 9 of the original format can be stored (4:1:1 or 4:2:0 format). In this mode motion estimation and compensation (Micronas VDU algorithm) for the master channel is supported (up to 30 MHz clock frequency). In parallel it is possible to insert the slave channel at any display position using frame mode and without joint lines. Noise reduction algorithm by recursive filtering is supported only for the master channel in SRC-Mode.

In SSC-Mode the data configuration of master and slave channel can be different. Depending on the picture size it is possible to store only 1 field of luminance and chrominance data or 2 fields. The data configuration can be defined by the I²C Bus parameters ORGMEMM and ORGMEMS, respectively.

ORGMEMM Data configuration of the memory

1 2 fields (limited picture size in SSC- and MUP-Mode)

01 field

Table 39 Definition of ORGMEM

ORGMEMS Data configuration of the memory

1 3 fields PIP (SRC-Mode),

2 fields (restricted picture size, SSC and MUP Mode)

0 Slave channel blocked (SRC-Mode and ORGMEMM=1)

1 field (SSC- and MUP-Mode; SRC-Mode and ORGMEMM=0)

Table 40 Definition of ORGMEMS

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Having 2 fields available for the master channel joint line free display can be activated. Storing 2 fields for both channels a complete joint line free display is possible. In both cases a suitable shift of the output raster phase is necessary (especially for ’Double Window’ / ’Split Screen’ / ’Picture And Picture’ / ’Side by Side’). In SSC mode field repetition (Simple 100Hz AABB; Field repetition AAAA or BBBB) is used for interlaced scan (100/120 Hz) rate conversion, ABAB modes are not supported. For progressive scan conversion also only field based algorithms are possible (Simple 50Hz AA*, B*B; Field repetition AA*, B*B). For the definition of the different scan rate conversion algorithms compare "Operation mode generator" on page 87.

Positioning of the pictures on the display is done externally by specifying the start of reading for both channels.

In MUP-Mode the configurations and functions for both channels are programmable independently. Two fields of the master channel can be stored to achieve a joint line free display of one decimated live picture. Applying smaller decimation factors only one field can be stored and joint line free display is not possible any more. These 2 modes correspond to SSC configuration for the master channel, AABB mode is supported.

For the second channel or for both channels any number of decimated fields can be stored step by step. The horizontal positions of the pictures are adjustable in steps of 4 pixel, the vertical positions are also variable and have a step size of 2 lines. The width and the height of a decimated picture depend on the corresponding decimation factors. A maximum of 1 picture per channel can be live. Only field repetition (AAAA, BBBB) is supported in this mode. Other display modes cause raster artefacts in live pictures. Joint lines are also not removed in live pictures.

A special MUP-Mode based on SSC memory configuration enables storing of 2 fields of a decimated still picture. The fields are calculated using only one input field for decimation. The generated lines are interpreted alternating as A- and B-lines. The described method improves vertical resolution of still pictures clearly without causing motion artefacts. The limited memory capacity does not allow to fill the complete display with decimated pictures created with the described method using only one channel. The different configuration can be selected by the I²C Bus parameter VERRESM and VERRESS, respectively.

VERRESM/VERRESS Vertical resolution in MUP-Mode

(ORGMEMM/ORGMEMS=1 and WRFLDM/WRFLDS=1)

1frame resolution

0 field resolution

Table 41 Definition of VERRESM/VERRESS

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System description

5.6.2 Configuration controlling

The following Table 42 and Table 43 summarize all possible combinations of memory data configurations for the master and slave channel and the corresponding applications. The main configurations are no. 1 for motion compensated up conversion and PIP insertion, no. 5 for joint line free Split Screen display and no. 9 for high quality Multi Picture including one live channel.

Table 44 shows the possible picture sizes. The data formats can be always 4:2:0 or 4:1:1. In SSC and MUP mode the picture sizes are influenced by the I²C Bus parameters MEMWRM and MEMWRS.

Config. MEMOP ORGMEMM ORGMEMS Master Channel Slave Channel

Fields Fields

YCY C

1 00 1 1 223 3

2 00 1 0 2 2 not available

3 00 0 1 11323

4 00 0 0 111 1

5 01 1 1 222 2

6 01 1 0 221 1

7 01 0 1 112 2

8 01 0 0 111 1

9 10 1 1 222 2

10 10 1 0 2 2 1 1

11 10 0 1 1 1 2 2

12 10 0 0 1 1 1 1

Table 42 Programmable data configurations

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Config. Mode Application

1 SRC motion compensated up conversion (4:1:1 or 4:2:0) + PIP (ABAB, frame based)

2 SRC motion compensated up conversion with enlarged picture size, no PIP facility

3 SRC AABB conversion for master and slave channel, slave data is written twice (PIP-

and SSC-configuration) used during switching from configuration 1 to configuration 7 without artefacts

4 SRC 2 independent not synchronized full size channels, AABB conversion

5 SSC joint line free ’Double Window’ / ’Split Screen’ / ’PAP’ display, AABB conversion

6 SSC display of 2 live channels, AABB conversion

slave channel exceeds the maximum double window size

7 SSC display of 2 live channels, AABB conversion

master channel exceeds the maximum double window size

8 SSC 2 independent not synchronized full size channels, AABB conversion

9 MUP high resolution Multi Picture for master and slave channel (one live picture possible)

AABB conversion

System description

10 MUP high resolution Multi Picture for master channel,

reduced resolution Multi Picture for slave channel, AABB conversion

11 MUP reduced resolution Multi Picture for master channel,

high resolution Multi Picture for slave channel, AABB conversion

12 MUP reduced resolution Multi Picture for master and slave channel, AABB conversion

Table 43 Applications of different data configurations

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Config. Master Channel Slave Channel

Size [Pixel X Lines] Size [Pixel X Lines]

MEMWRM=0 MEMWRM=1 MEMWRS=0 MEMWRS=1

1 768 X 288 256 X 104

2 768 X 341 not available

3 768 X 288 256 X 104 / 512 X 176

4 768 X 341 768 X 341

5 512 X 256 768 X 170 512 X 256 768 X 170

6 512 X 256 768 X 170 512 X 512 768 X 341

7 512 X 512 768 X 341 512 X 256 768 X 170

8 512 X 512 768 X 341 512 X 512 768 X 341

9 512 X 256 768 X 170 512 X 256 768 X 170

10 512 X 256 768 X 170 512 X 512 768 X 341

11 512 X 512 768 X 341 512 X 256 768 X 170

System description

12 512 X 512 768 X 341 512 X 512 768 X 341

Table 44 Maximum picture sizes

MEMWRS Memory write mode slave channel

1 max. 768 pixel/line

0 max. 512 pixel/line

Table 45 Definition of MEMWRS

MEMWRM Memory write mode master channel

(ORGMEM=01 or 10, SSC or MUP Mode)

1 max. 768 pixel/line

0 max. 512 pixel/line

Table 46 Definition of MEMWRM

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I²C Bus parameter [Default]

CHRFORM [0)

CHRFORS [0]

ORGMEMM [1]

ORGMEMS [1]

MEMOP [00]

VERRESM [0]

VERRESS [0]

System description

Sub address Description

12h Chrominance data format master channel

34h Chrominance data format slave channel

58h Data configuration of the memory master channel

57h Data configuration of the memory slave channel

53h Memory operation mode

58h Vertical resolution master channel

57h Vertical resolution slave channel

MEMWRM [0]

MEMWRS [0]

58h Memory write mode master channel

57h Memory write mode slave channel

Table 47 Input write I²C Bus parameter

5.6.3 SRC mode configuration

Conditions:MEMOP=00, ORGMEMM=1, ORGMEMS=1

The described data configuration is typical for normal SRC mode with motion compensated 100 Hz ABAB conversion and joint line free frame based PIP insertion.

maximum picture size (master Channel) : 768 pixel X 288 lines

maximum picture size (slave channel) : 256 pixel X 104 lines

5.6.4 SSC and MUP mode configuration

Conditions: MEMOP=01 or 10, ORGMEMM=1, ORGMEMS=1

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This is the typical configuration needed for joint line free ’Split Screen’ / ’Double Window’ or ’PAP’ display in 4:1:1 or 4:2:0 format using AABB conversion. The same configuration can be used for Multi Picture mode displaying a joint line free live picture and multiple high resolution still pictures.

maximum picture size (master and slave) : 512 (768) pixel X 256 (170) lines

In MUP-Mode it is possible to write only A fields into the memory. Therefore the I²C Bus parameters

WRFLDM and WRFLDS can be used.

WRFLDM / WRFLDS

1 only A fields are written

Write field (MUP-Mode, MEMOP=10)

0 all fields are written corresponding to the actual mode

Table 48 Definition of WRFLDM/WRFLDS

I²C Bus parameter [Default]

WRFLDM [0]

WRFLDS [0]

Sub address Description

58h Write field master channel (MUP-Mode)

57h Write field slave channel (MUP-Mode)

Table 49 Input write I²C Bus parameter

5.6.5 Configuration switch

This chapter deals with the switching between the different operation modes without causing visible picture artifacts. The typical application concerns the transition from SRC-PIP mode to SSC double window mode (see figure 26 on page 67 and figure 27

on page 68) and furthermore to an exchange of master and slave channel (see figure 28 on page 69).

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ORGMEMM Data configuration of the memory (Master Channel)

0 SRC mode, ORGMEMM=1: no slave channel available

SRC mode, ORGMEMM=0, SSC- and MUP-mode: 1 field is stored

1 SRC-mode: 3 fields are stored for PIP

SSC- and MUP-mode: 2 fields are stored

Table 50 Definition of ORGMEMM

ORGMEMS Data configuration of the memory (Slave Channel)

0 SRC mode, ORGMEMM=1: no slave channel available

SRC mode, ORGMEMM=0, SSC- and MUP-mode: 1 field is stored

1 SRC-mode: 3 fields are stored for PIP

SSC- and MUP-mode: 2 fields are stored

System description

Table 51 Definition of ORGMEMS

MEMRDM Memory read mode master channel

(SRC-Mode, MEMOP=00)

1 Reading only field memory area for AABB conversion

0 Reading both field memory areas for ABAB conversion

Table 52 Definition of MEMRDM

MEMRDS Memory read mode slave channel

(SRC-Mode, MEMOP=00)

1 Reading data in PIP-configuration (joint line free, ABAB)

0 Reading data in SSC-configuration, 1 or 2 decimated fields, AABB

Table 53 Definition of MEMRDS

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MEMWRM Memory read mode master channel

(only for SSC- and MUP-mode)

0 512 pixel / line

1 768 pixel / line

Table 54 Definition of MEMWRM

MEMWRS Memory read mode slave channel

0 SRC-mode: writing data in PIP configuration

SSC- and MUP-mode: 512 pixel / line

1 SRC-mode: writing data in PIP- and

SSC- and MUP-mode: 768 pixel / line

in SSC configuration

System description

Table 55 Definition of MEMWRS

A typical animated transition to a double window display can be divided into two parts: changing the operation mode from SRC to SSC (figure 26 on page 67) and changing the picture sizes and positions continuously according to a double window display (figure 27 on page 68). In SSC mode no vector driven up conversion modes are possible. Only field based algorithms are supported. The corresponding I²C commands are summarized in Table 56 and Table 57.

SRC-PIP Mode, ABAB (A+B)

SSC-Mode, AABB (A+B)

JLC.vsd/10

Figure 26 Switching from SRC-PIP mode to SSC mode

SwMode1.WMF

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SSC-Mode, AABB (A+B):

-master picure becomes smaller

-slave picture becomes larger

SSC-Mode: Double Window, AABB (A+B)

System description

JLC.vsd/10

Figure 27 Changing picture sizes to get a double window display

Steps MEM-OPORG-

MEMM

1 00 1 1 0 0 0 0 SRC mode with 1/9 PIP insertion

ORGMEMS

MEMWRM

MEMWRS

MEMRDS

MEMRDM

Operation

SwMode2.WMF

2 00 1 1 0 0 0 0 a field based up conversion mode

must be programmed by STOPMOM and STOPMOS

2a* 00 1 1 0 0 0 1 only one field is read for master

channel (reduced vertical resolution)

3 00 0 1 0 1 0 X memory capacity of master

channel is reduced to 1 field memory organization of slave channel is prepared for SSC configuration

4 00 0 1 0 1 1 X slave channel reading is switched

to SSC memory configuration

5 01 0 1 1 0 X X SSC mode: full size master

picture, 1/9 size of slave picture

Table 56 Switching from SRC PIP mode to SSC mode

* Step 2a may be left out

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Steps MEM-OPORG-

MEMM

6 01 0 1 1 0 X changing picture sizes of master and slave by

7 01 1 1 0 0 X reducing the width below 512 pixel for the

ORGMEMS

MEMWRM

MEMWRS

MEMRDS

Operation

programming the corresponding decimation I²C Bus parameters

master picture two fields can be stored

System description

Table 57 Changing the picture sizes to double window format

Starting in SRC mode with a PIP insertion (step 1) at first a field based up conversion mode must be chosen for both channels, e.g. AABB conversion for interlaced modes and intrafield interpolation for progressive modes (step 2). Now the capacity for the master channel can be reduced to 1 field (step 3). The free memory capacity is used to write the slave data at two address areas in parallel corresponding to SRC-PIP configuration and SSC configuration. In step 4 the reading of the slave channel data is switched to SSC configuration. In the last step also the master channel is switched to SSC mode. In this configuration we can store 1 field of the master channel and 2 fields of the slave channel. The Joint Line Controller can be activated and joint line free display is possible.

Reducing the size of the master picture and enlarging the slave picture size is performed in step 6 in table . During this phase we can get problems with joint line free display of the master picture until the horizontal width is below 512 pixel. Now also the master channel is enabled to store 2 fields and joint line free display is possible again (step 7). In this configuration double window display is performed.

During all steps positioning of both pictures is free programmable to enable multiple variations of the animation.

SSC-Mode, AABB (A+B):

-master picure becomes smaller

-slave picture becomes larger

SRC-PIP Mode, ABAB (A+B)

JLC.vsd/11

SwMode3.WMF

Figure 28 Completing the operations to a master slave exchange

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Steps MEM-OPORG-

MEMM

8 01 1 1 0 0 X changing picture sizes of master and slave by

9 01 1 0 0 1 X exceeding a width of 512 pixel for the slave

10 01 1 0 0 1 X further changes of picture sizes until full size

11 01 0 1 1 0 X switching synchronization to slave channel and

12000 1 011switching to SRC mode using still field based up

13000 1 010slave channel reading is switched to SRC

ORGMEMS

MEMWRM

MEMWRS

MEMRDS

Operation

programming the corresponding decimation I²C Bus parameters

picture only one field can be stored

slave picture and 1/9 size master picture is displayed

exchanging the inputs

conversion

memory configuration

System description

14001 1 000also the master channel works frame based

15001 1 000programming STOPMOM and STOPMOS to

frame based up conversion

Table 58 Performing a master slave exchange

Starting with the double window configuration (figure 27 on page 68) the procedure is continued with an animation to perform an exchange of the master and slave sources to get a display like it is shown in figure 28 on page 69.

In step 8 the picture size of the master channel is decreased and the size of the slave picture is increased continuously. When the width of the slave picture exceeds 512 pixel only one field can be stored (step 9). Joint line free display of the slave channel is not always possible in this configuration. When full size slave picture format and 1/9 master picture size is reached (step 10) an exchange of master and slave channel is possible. Unstable picture phases can be avoided when the display raster phase is adapted to the slave channel before the hardware exchange of both sources is done. For display phase raster shifting see "Master slave switch" on page 72.

Now we can activate the SRC mode again. At first we just change the mode maintaining the field based conversions (step 12). Then the slave data configuration of the memory is changed to SRC configuration (step 13) and at last the master channel memory capacity is enlarged to 2 fields (step 14) and frame based up conversion modes are enabled (step 15).

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System description

5.6.6 Joint line free display

This chapter describes the I²C Bus parameters to get a joint line free display in SSC mode.

I²C Bus parameter [Default]

RSHFTM [0]

RSHFTS [0]

SHFTSTEP [0100]

Sub address Description

55h Joint line free display of master channel by shifting the output raster

phase (SSC-Mode) 1: enabled 0: disabled

55h Joint line free display of master and slave channel by shifting the

output raster phase (SSC-Mode, RSHFTM=1) 1: enabled 0: disabled

55h Increment for raster phase shift per output frame (lines)

PROG_THRES [0111100]

56h Threshold to display progressive PIP without joint lines

Table 59 Input write I²C Bus parameter

I²C Bus parameter

SHIFTACT indicates active shifting process of the display raster phase

Description

0: display phase shifting not active 1: display phase shift active

Table 60 Output read I²C Bus parameter

A special circuit is implemented to achieve a joint line free display in SSC mode (e.g. Double Window Display). This circuit synchronizes the two input sources and removes the joint lines by automatic controlled shifting of the display raster phase. This procedure enlarges the value of OPDELM resulting in an delayed start of the output processing.

The I²C Bus parameters RSHFTM and RSHFTS enable joint line free display for master and slave channel, separately. SHFTSTEP fixes the amount of lines which is added to OPDELM with each output frame. The readable I²C Bus parameter SHIFTACT signalizes the progressing shifting operation.

It is recommended to enable the registers RSHFTM and RSHFTS in all application modes.

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Mode Input

Master Channel

SRC 625/50i 625/50i 625/100i

SRC 525/60i 525/60i 525/120i

SRC 625/50i 525/60i 625/100i

SRC 525/60i 625/50i 525/120i

SSC/ MUP

625/50i 625/50i 625/100i

525/60i 525/60i 525/120i

625/50i 525/60i 625/100i

Input Slave Channel

Output Display Channel

625/50p

525/60p

625/50p

525/60p

625/50p

525/60p

625/50p

System description

Comment

Motion compensation for master channel possible

joint line free display for slave channel possible (NEW)

No motion compensation possible

No motion compensation possible, no joint line free display for slave channel possible

SSC/ MUP

525/60i 625/50i 525/120i

525/60p

No motion compensation possible, no joint line free display for slave channel possible

Table 61 Supported data formats

5.6.7 Master slave switch

This chapter describes the I²C Bus parameters used to execute a master and slave exchange.

I²C Bus parameter [Default]

MASTSLA [0]

MASLSHFT [0]

Sub address Description

55h Master / Slave shift:

1: Master and slave input signals are exchanged, reset of display raster shift 0: Display raster is synchronized to input master channel (vertical sync)

56h Master / Slave shift:

1: Display raster is shifted slave phase to prepare a master/slave switch 0: Display raster is synchronized to input master channel (vertical sync)

Table 62 Input write I²C Bus parameter

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I²C Bus parameter [Default]

SHIFTACT 7Fh Shifting of display raster phase active

Sub address Description

1: phase shift in progress 0: phase shift not active

System description

Table 63 Output read I²C Bus parameter

Master slave exchange means an animated exchange of the master and slave picture source without visible synchronization problems of the deflection PLL compared with a hard switch between both sources. To avoid this synchronization problem the display raster phase is slowly shifted to a position that fits to the slave channel sync pulses. Then the exchange can be done without visible artefacts. For the animation see "Configuration switch" on page 65.

What to do to perform a master slave switch:

1.I²C Parameter MASLSHFT must be set. Shift process is started.

2.The I²C output signal SHIFTACT must be observed. After setting MASLSHFT is becomes ’1’ and signalizes that the shift process is active. When it becomes ’0’ the shift process is finished and the desired phase of the display raster is obtained.

3.At the same time exchanging of master and slave inputs and setting of I²C parameter MASTSLA must be performed. Now the chip is synchronized to the former slave channel that now has become the master.

4.At last the I²C Bus parameters MASLSHFT and MASTSLA should be reset.

5.6.8 Refresh and still picture mode

The master and the slave channel picture can be frozen by the I²C Bus parameter FREEZEM and FREEZES, respectively. The I²C Bus parameters REFRON and REFRPER may be used to activate a memory refresh for the internal memory.

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I²C Bus parameter [Default]

FREEZEM [0]

FREEZES [0]

REFRPER [00]

REFRON [0]

System description

Sub address Description

58h Freeze picture master

1: freezed (no writing of master channel) 0: live

57h Freeze picture slave

1: freezed (no writing of slave channel) 0: live

53h Refresh period of the memory (REFRON=1; 50 Hz, 625 lines

standard) 00: ~ 10ms 01: ~ 7ms 10: ~ 5.5ms 11: ~ 4ms

55h Refresh of internal memory

1: memory refresh activated 0: no memory refresh

Table 64 Input write I²C Bus parameter

5.6.9 Memory management and animation controlling

The "Example for animation" on page 75 shows a possible application of the SDA

9415. 11 still pictures plus one life picture (cup of coffee) are located around a second life (boat) picture (see picture number 1). The still pictures plus one life picture (cup of coffee) are located in the slave memory and the life picture (boat) in the master memory. The user wants to switch now between the cup of coffee and the boat channel. A possible animation could look like this. The boat will be compressed and disappears (number 2 and number 3). Due to the fact, that only background colour should be visible, the parts of the life picture, which disappear after compression, will be overwritten with the back ground colour. Afterwards the new channel is expanded and overwrites the border colour (cup of coffee, number 4 and number 5).

To support this and other features several I²C Bus parameters exists, which will be described in more detail afterwards.

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Still picture

Life picture

System description

Life picture

vhcomba2

Figure 29 Example for animation

The I²C Bus parameters IPOSXM and IPOSYM or IPOSXS and IPOSYS, respectively, specify the position of the left upper corner of a stored picture. The figure below explains the functionality of the I²C Bus parameters. The whole memory is organized as blocks, which have a width of 32 pixels. The position (x,y) defined by the I²C Bus parameters is defined by the equation below:

IPOSXM

xy,ΕΦ 32



· 4 IPOSXM modulo 8ΦΕ·+ IPOSYM,

------------ ------------8

Figure 30 Equation of the position of the left upper picture corner

The IPOSYM and IPOSYS I²C Bus parameter specify the vertical position with a resolution of one line for 4:1:1 format and 2 lines for 4:2:0 format for the master and slave channel, respectively. The 5 MSBs of the IPOSXM and IPOSXS defines the horizontal position with a resolution of 32 pixels (block resolution). The 3 LSBs of IPOSXM and IPOSXS are used for fine positioning of the picture in a block with a resolution of 4 pixels. Due to the fact, that only blocks can be written to the memory, the pixels left of the fine positioning are filled up with border values (border values are defined by YBORDERM/ YBORDERS, UBORDERM/UBORDERS, VBORDERM/VBORDERS). If the number of pixels is smaller as 32 pixels (block size), the missing pixels of a block are also filled up with border values.

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32 * (IPOSXM)/8

IPOSYM

0 1 2 3 4

y/lines

x/pixels

04 8 322824

4 * (IPOSXM modulo 8)

System description

block

Figure 31 Explanation of memory management I

The Figure 32 shows a picture (boat, number 1), which is located with the left upper corner at the position (x1,y1). The picture will be compressed in vertical and horizontal direction and stored at the position (x2,y2). The vertical and horizontal compression mechanism of the input signal was explained before (compare "Vertical and horizontal compression (VHCOMM/VHCOMS)" on page 36). This result could look like as showed in the picture number 2b. Parts of the original boat are still visible. Therefore in addition the I²C Bus parameters LEBORDM/LEBORDS, RIBORDM/RIBORDS, UPBORDM/UPBORDS and LWBORDM/LWBORDS exist. These I²C Bus parameters specify the amount of pixels at the left side and the right side and the amount of lines at the top and the bottom which has to be written in addition into the memory with coloured border values (I²C Bus parameters YBORDERM, YBORDERS, UBORDERM, UBORDERS, VBORDERM, VBORDERS). Then the result could look like as showed in the picture number 2a (white border colour). The amount of pixels at the left side can be defined by the I²C Bus parameters LEBORDM/LEBORDS (amount of border pixels = 4 * LEBORDM/LEBORDS) and the amount of pixels at the right side can be defined by the I²C Bus parameter RIBORDM/RIBORDS (amount of border pixels = 4 * RIBORDM/ RIBORDS). The maximum amount of pixels, which can be written in addition, is 28 pixels on each side. The I²C Bus parameters UPBORDM/S and LWBORDM/S specify the amount of lines which has to be written in addition into the memory at the upper and lower edge of the picture with coloured border values. The maximum amount of lines, which can be written in addition, is 15 on each side. But there is a limitation that the sum of UPBORDM/UPBORDS + LWBORDM/LWBORDS should not exceed 20 (PAL) lines. In horizontal direction as mentioned before only blocks (32 pixels) can be written into the memory. That means for instance if the LEBORDM parameter has a value bigger as zero and the 3 LSBs of IPOSXM parameter are zero (start position at a begin of a block), that the complete block on the left side of the block specified by IPOSXM will be filled with border colour.

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(X1,Y1)

(X2,Y2)

LEBORDM

x = 32 * IPOSXM/8 + 4 * (IPOSXM modulo 8)

Figure 32 Explanation of memory management II

System description

UPBORDM

RIBORDM

LWBORDM

So the animation shown in the Figure 32 can be done in the following way. The picture (boat) has at the beginning a defined size (defined by the I²C Bus parameters APPLM1, ALPFM1, INTHM1, DEZHM1, INTVM1, DEZVM1) and the left upper corner of the picture is located at the position (x1,y1) (defined by IPOSXM1, IPOSYM1). Specify the new picture size. Set the corresponding I²C Bus parameters (APPLM2, ALPFM2, INTHM2, DEZHM2, INTVM2, DEZVM2) to get the new picture size. Specify the new vertical and horizontal position (x2,y2) (defined by IPOSXM2, IPOSYM2). Specify in addition the amount of lines at the upper and lower edge, which has to be overwritten with border values. In addition the amount of pixels at the left and right edge, which has to be overwritten with border values (LWBORDM, UPBORDM, LEBORDM, RIBORDM). Send the new values to the I²C interface. Remember that the reduction of the picture is limited in horizontal and vertical direction, if the border should be overwritten with border colour.

The Figure 33 shows in detail what happens by means of a horizontal bar, which is horizontally reduced. The width of the bar is 84 pixels (compare Figure 33). The position x1, defined by IPOSX1 is for instance,

IPOSXM1=00001100b=12 => x1 = 32 * 1 + 4 * 4 = 48

The I²C Bus parameters LEBORDM and RIBORDM are both equal 0. The first block and the last block are filled up with border values (black colour - background value).

The bar is compressed horizontally and the new width of the bar is 44 pixels. The new position defined by IPOSX2 after the reduction step may be

IPOSXM2=00010001b=17=>x2 = 32 * 2 + 4 * 1 = 68.

That means the actual picture size is reduced for 40 pixels, 20 pixels at the left side (Left Side = 68 - 48 = 20) and 20 pixels at the right side (Right Side = 132 - 20). Therefore the

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System description

I²C Bus parameter LEBORDM has to be set to LEBORDM=5 (amount of pixels = 4*LEBORDM = 4*5 = 20), if the pixels remaining in the memory should be overwritten with border values. In addition the I²C Bus parameter RIBORDM has to be set to RIBORDM=5 (amount of pixels = 4*RIBORDM = 4*5 = 20), if the pixels remaining in the memory should be overwritten with border values. The new position of the left edge is 68 and begin of the block is 64, thus the difference between the begin of the bar and the actual block is 68-64=4. That means that from the additional 20 pixels, which have to be written left of the bar, at least 16 pixels belong to the block which begins at the position

32. That means, that the complete block (begin at position 32) is filled up with border values. The same argumentation is valid for the right edge of the bar.

IPOSYM

0 1

32 * (IPOSXM)/8

128

132

pixels

IPOSYM

0 1

32 * (IPOSXM)/8

112

128

pixels

Reduction

lines

APPLM1 = 21 -> 8*21/2 = 84 pixel

IPOSX1 = 00001100=12

x1= 32*1 + 4*4 = 48

LEBORD1 = 0

RIBORD1 = 0 RIBORD2 = 5

Reduction

40 pixels

lines

APPLM2 = 11 -> 8*11/2 = 44 pixel

IPOSX2 = 00010001

x2 = 32*2 + 4*1 = 68

LEBORD2 = 5

Figure 33 Explanation of memory management III

Repeating the procedure described above must be used for an animation as explained in Figure 29.

vhcomba3

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I²C Bus parameter [Default]

UPBORDM [0]

LWBORDM [0]

LEBORDM [0]

RIBORDM [0]

UPBORDS [0]

LWBORDS [0]

LEBORDS [0]

System description

Sub address Description

06h Amount of upper border lines by vertical compression master

06h Amount of lower border lines by vertical compression master

03h Amount of left border pixels by horizontal compression master

03h Amount of right border pixels by horizontal compression master

28h Amount of upper border lines by vertical compression slave

28h Amount of lower border lines by vertical compression slave

25h Amount of left border pixels by horizontal compression slave

RIBORDS [0]

IPOSXM [0]

IPOSXS [0]

IPOSYM [0]

IPOSYS [0]

25h Amount of right border pixels by horizontal compression slave

02h Horizontal picture position in the memory for master

24h Horizontal picture position in the memory for slave

01h Vertical Picture Position in the Memory for master

23h Vertical Picture Position in the Memory for slave

Table 65 Input write I²C Bus parameter

It is possible to write border colours instead of the master or slave channel in different areas. Therefore the I²C parameters FORCOLM and FORCOLS can be used.

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I²C Bus parameter [Default]

YBORDERM [0001]

UBORDERM [1000]

VBORDERM [1000]

YBORDERS [0001]

UBORDERS [1000]

System description

Sub address Description

04h Y border value (Yborder(3) Yborder(2) Yborder(1) Yborder(0) 0 0

0 0 = 00010000 = 16), YBORDERM defines the 4 MSB’s of a 8 bit value

05h U border value (Uborder(3) Uborder(2) Uborder(1) Uborder(0) 0 0

0 0 = 10000000 = 128), UBORDERM defines the 4 MSB’s of a 8 bit value

05h V border value (Vborder(3) Vborder(2) Vborder(1) Vborder(0) 0 0

0 0 = 10000000 = 128), VBORDERM defines the 4 MSB’s of a 8 bit value

26h Y border value (Yborder(3) Yborder(2) Yborder(1) Yborder(0) 0 0

0 0 = 00010000 = 16), YBORDERS defines the 4 MSB’s of a 8 bit value

27h U border value (Uborder(3) Uborder(2) Uborder(1) Uborder(0) 0 0

0 0 = 10000000 = 128), UBORDERS defines the 4 MSB’s of a 8 bit value

VBORDERS [1000]

FORCOLM [0]

FORCOLS [0]

27h V border value (Vborder(3) Vborder(2) Vborder(1) Vborder(0) 0 0

0 0 = 10000000 = 128), VBORDERS defines the 4 MSB’s of a 8 bit value

04h Force colour master channel

1: on 0: off

26h Force colour slave channel

1: on 0: off

Table 66 Input write I²C Bus parameter

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5.7 Output sync controller (OSCM/S)

Signals Pin number Description

HOUT 4 horizontal synchronization signal (polarity programmable, I²C Bus

parameter 4Ah HOUTPOL, default: high active)

VOUT 5 vertical synchronization signal (polarity programmable, I²C Bus

parameter 4Ah VOUTPOL, default: high active)

BLANK 7 free programmable horizontal blanking signal (polarity

programmable, I²C Bus parameter 49h BLANKPOL, default: high active)

INTERLACED 6 interlaced signal (can be used for AC coupled deflection circuits)

Table 67 Output signals

The output sync controller generates horizontal and vertical synchronization signals for the scan rate converted output signal. The figure below shows the block diagram of the OSCM/S and the existing I²C Bus parameters.

HOUTPOL, HOUTFR, APPLOPD,

NAPOPD, BLANLEN, PPLOP, RMODE,

BLANDEL, HORPOSM, HORPOSS,

HORWIDTHM, HORWIDTHS, HOUTDEL

HIN

VIN

GMOTION,

MOVMO,

MOVPH,

MOVTYP

STOPMOM, STOPMOS,

OPERATION

ADOPMOM

HOUT

generator

VOUT

generator

mode

generator

VOUTPOL, VOUTFR,

NALOPD, ALPFOPD,

LPFOP, VERPOSM,

VERPOSS, VERWIDTHM,

VERWIDTHS, INTMODE

HOUT

BLANK

VOUT INTERLACED

osc01

Figure 34 Block diagram of OSCM/S

Furthermore the output sync controller derives framing signals from the generated HOUT and VOUT for the output data processing. The framing signals depend on different I²C Bus parameters. The whole output picture is a combination of three channels:

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1: Background channel

2: Output channel master

3: Output channel slave

The background channel has always the lowest priority. The priority between output channel master and slave is defined by an I²C Bus parameter PRIORMS. The figure below shows an example for the combination of the three channels. The background colour black has lowest priority. The picture content of master channel is a phone and the picture content of slave channel is a airplane. In this case the slave channel has the highest priority. To enable or disable the display of the master or slave channel the I²C parameters MASTERON and SLAVEON can be used.

HOUT

VOUT

4*LPFOP+1

(HORPOSM*4)*CLKD

(NAPOPD*4)*CLKD

BLANK

((6 MSBs of BLANDEL)*8 + (2

LSBs of BLANDEL))*CLKD

(PPLOP*2)*CLKD

(HORWIDTHM*8)*CLKD

(HORPOSS*4)*CLKD

(HORWIDTHS*4)*CLKD

(APPLOPD*8)*CLKD

(BLANLEN*8)*CLKD

VERPOSM

VERWIDTHM*8

outpar01

VERPOSS

VERWIDTHS*4

(NALOPD+1)*2

ALPFOPD*8

Figure 35 Output I²C Bus parameter

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I²C Bus parameter [Default value]

NALOPD [22]

ALPFOPD [144]

VERPOSM [0]

VERWIDTHM [72]

VERPOSS [0]

VERWIDTHS [144]

LPFOP [156]

NAPOPD [0]

APPLOPD [90]

Sub address Description

36h Not Active Line OutPut Display defines the number of lines

from the V-Sync to the first active line of the output frame

37h Active Lines Per Field OutPut Display defines the number of

active lines per output frame

3Ch VERtical POSition Master defines the number of lines from the

first active line of the background channel to the first active line of the master channel

40h VERtical WIDTH Master defines the number of active lines of

the master channel per output frame

3Dh VERtical POSition Slave defines the number of lines from the

first active line of the background channel to the first active line of the slave channel

41h VERtical WIDTH Slave defines the number of active lines of

the slave channel per output frame

38h Lines Per Frame OutPut defines the number of lines per output

frame (only valid for VOUTFR=1)

39h Not Active Pixel OutPut Display defines the number of pixels

from the H-Sync to the first active pixel

43h Active Pixels Per Line OutPut Display defines the number of

pixels per line (background, master and slave channel)

HORPOSM [0]

HORWIDTHM [90]

HORPOSS [0]

HORWIDTHS [180]

PPLOP [432]

BLANDEL [0]

BLANLEN [180]

HOUTDEL [0]

PRIORMS [1]

3Ah HORizontal POSition Master defines the number of pixels from

the first active pixel of the background channel to the first active pixel of the master channel

3Eh HORizontal WIDTH Master defines the number of active pixels

of the master channel

3Bh HORizontal POSition Slave defines the number of pixels from

the first active pixel of the background channel to the first active pixel of the slave channel

3Fh HORizontal WIDTH Slave defines the number of active pixels

of the slave channel

45h, 46h Pixel Per Line OutPut defines the number of pixels between

two consecutive H-Syncs (only valid for HOUTFR=1)

42h BLANk DELay defines the distance from the H-Sync to the

active edge of the BLANK signal in number of CLKD clocks

44h BLANk LENgth defines the length of the BLANK signal in

number of CLKD clocks

35h Horizontal delay of HOUT and VOUT signal in clocks of CLKD

43h Priority of master or slave channel:

1: master channel priority 0: slave channel priority (SFCPR should be fixed to V

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I²C Bus parameter [Default value]

MASTERON [1]

SLAVEON [0]

Sub address Description

53h Display of master channel:

1: enabled 0: disabled

53h Display of slave channel:

1: enabled 0: disabled

Figure 36 Output write I²C Bus parameter

The next paragraphs describe the HOUT and VOUT generator in more detail. Both generators have a so called “locked-mode” and “freerunning-mode”. Not all combinations of the modi make sense. The table below shows ingenious configurations.

Mode HOUTFR VOUTFR CLKMDEN

“H-and-V-locked” 000

“H-freerunning-V-locked” 101

“H-and-V-freerunning” 111

Figure 37 Ingenious configurations of the HOUT and VOUT generator

5.7.1 HOUT generator

The HOUT generator has two operation modes, which can be selected by the I²C Bus parameter HOUTFR. The HOUT signal is active high (HOUTPOL=0) for 64 clock cycles (X1/CLKD). In the freerunning-mode the HOUT signal is generated depending on the PPLOP I²C Bus parameter. In the locked-mode the HOUT signal is locked on the incoming H-Sync signal HIN. The polarity of the HOUT signal is programmable by the I²C Bus parameter HOUTPOL. The BLANK signal can be used to mark the active part of a line. To avoid transition artifacts of digital filters the number of active pixels can be symmetrically reduced using the CAPPM and CAPPS I²C Bus parameter.

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I²C Bus parameter

HOUTFR 1: free run 0: locked mode

CAPPM 00: k = 0 01: k = 8 10: k = 16 11: k = 24

CAPPS 00: k = 0 01: k = 8 10: k = 16 11: k = 24

Sub address Description

4Ah HOUT generator mode select

46h Reducing factor for the HORizontal WIDTH Master value of the

master channel Number of active pixels per line = 8 * HORWIDTHM - 2*k

46h Reducing factor for the HORizontal WIDTH Slave value of the master

channel Number of active pixels per line = 8 * HORWIDTHM - 2*k

Table 68 Output write I²C Bus parameter

5.7.2 VOUT generator

The VOUT generator has two operation modes, which can be selected by the I²C Bus parameter VOUTFR. The VOUT signal is active high (VOUTPOL=0) for two output lines. In the freerunning-mode the VOUT signal is generated depending on the LPFOP I²C Bus parameter.

In the locked-mode the VOUT signal is synchronized by the incoming V-Sync signal VIN (means the internal VIN delayed by the I²C Bus parameter OPDELM, compare "Input sync controller (ISCM/ISCS)" on page 26). The RMODE I²C Bus parameter (line- scanning pattern mode 1: progressive, 0: interlaced) determines the scan rate conversion mode. If RMODE=1, then for each incoming V-sync signal VIN an outgoing V-sync signal VOUT has to be generated (e.g. 50 Hz interlaced to 50 Hz progressive scan rate conversion). If RMODE=0, then during one incoming V-Sync signal, two VOUT pulses have to be generated (e.g. 50 Hz interlaced to 100 Hz interlaced scan rate conversion).

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VIN

RMODE=1

VOUT

RMODE=0

VOUT

Figure 38 VOUT generation depending on I²C Bus parameter RMODE

The polarity of the VOUT signal is programmable by the I²C Bus parameter VOUTPOL.

The VOUT signal has a delay of two CLKOUT clocks to the HOUT signal or in case of interlaced a delay of a half line plus two CLKOUT clocks.

The INTERLACED signal can be used for AC-coupled deflections. Depending on the I²C Bus parameter INTMODE the value of this signal will be generated. The Table 69 shows the definition of this signal (compare "Operation mode generator" on page 87).

conv

output field phase 0output field phase 1output field phase

2/0

INTMODE INTMODE(0) INTMODE(1) INTMODE(2) INTMODE(3)

output field phase 3/1

Table 69 Output write I²C Bus parameter INTMODE

I²C Bus parameter

VOUTFR 1: free run 0: locked mode

RMODE 1: progressive 0: interlaced

INTMODE 49h Free programmable INTERLACED signal for AC-coupled

Sub address Description

4Ah VOUT generator mode select

48h line-scanning pattern mode

deflection stages

Table 70 Output write I²C Bus parameter INTMODE

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5.7.3 Switching from H-and-V-freerunning to H-and-V-locked mode

In H-and-V-freerunning mode, generally, the phase of the generated synchronization line-scanning pattern has no correlation to the input line-scanning pattern. A hard switch from the H-and-V-freerunning mode to the H-and-V-locked mode therefore would cause visible synchronization artefacts. To avoid these problems the SDA 9415 enlarges the line and the field lengths of the output sync signals HOUT and VOUT in a defined procedure to enable an invisible synchronization of the freerunning output to the input.

For vertical synchronization the maximum synchronization time is 260 ms for interlaced and 520 ms for progressive display modes. Horizontal synchronization is performed in a maximum time of 50 ms. To get the best performance it is recommended to change at first the vertical and after the mentioned delay times the horizontal mode from free running to locked.

5.7.4 Operation mode generator

The VOUT generator determines the VOUT signal. For proper operation of the VOUT generator information about the line-scanning pattern sequence is necessary. The I²C Bus parameters STOPMOM (STatic OPeration MOde Master), STOPMOS (STatic OPeration MOde Slave) and the I²C Bus parameter ADOPMOM (ADaptive OPeration MOde Master) define the line-scanning pattern sequence and the scan rate conversion algorithms.

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FRAME/FIELD

FRAME

Content of picture

DISPLAY LINE-SCANNING PATTERN

Display raster

odd lines

even lines

FIELD A

odd lines

FIELD B

even lines

Di spla y li ne- sc anning

pattern

∼

Di spla y li ne- sc anning

pattern

fiel dras01

Tube, Display raster

Figure 39 Explanation of field and display line-scanning pattern

The interlaced input signal (e.g. 50 Hz PAL or 60 Hz NTSC) is composed of a field A (odd lines) and a field B (even lines).

- Input signal, field A at time n,

- Input signal, field B at time n

The field information describes the picture content. The output signal, which could contain different picture contents (e.g. field A, field B) can be displayed with the display line-scanning pattern

,∼) - Output signal, field A at time n, displayed as line-scanning pattern ∼Ι

∼ or ϒ.

(An,ϒ) - Output signal, field A at time n, displayed as line-scanning pattern ϒΙ

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((A*)n,ϒ) - Output signal, field A line-scanning pattern interpolated into field B at time n, displayed as line-scanning pattern

(An B

n-1

,∼+ϒΦ=ϑ=Output signal, frame AB at time n, progressive

The table below describes the different scan rate conversion algorithms and the corresponding line-scanning pattern sequences. The delay between the input field and the corresponding output fields depends on the OPDELM parameter and the default value for the delay is an half input field.

, B

n-1

, A

n-1

Phase 2/0

Phase 3/1

n-1

Input fields

time

Fields available in

the internal field stores

Output fields

n-1

OPDELM lines

Figure 40 Explanation of operation mode timing

osc02

An, B

Phase 0

Phase 1

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Input field A

STOPMOM

Scan rate conversion algorithm Output

field an phase 0

0000 VDU, camera mode p(c)*

Output field bn phase 1

)

Ι=∼ p(d)Ι=ϒ p(a)Ι=∼ p(b)Ι=ϒ

Input field B

Output field cn phase 2/0

Output field dn phase 3/1

0001 VDU, film mode, phase 0, PAL p(mc)Ι=∼ p(md)Ι=ϒ p(ma)Ι=∼ p(mb)Ι=ϒ

0010 VDU, film mode, phase 1, PAL p(ma)Ι=∼ p(mb)Ι=ϒ p(mc)Ι=∼ p(md)Ι=ϒ

0011 Frame repetition, ABAB A

0100 FRAME repetition, BABA B

0101 Simple 100, AABB A

0110 Simple 100, BBAA B

0111 Field repetition, AAAA I A

1000 Field repetition, AAAA II A

1001 Field repetition, BBBB I B

1010 Field repetition, BBBB II B

1100 Simple 100, AA*B*B A

1101 Simple 100, BB*A*A B

Ι=∼ B

n-1

Ι=ϒ AnΙ=∼ BnΙ=ϒ AnΙ=∼

Ι=∼ AnΙ=∼ BnΙ=ϒ BnΙ=ϒ

n-1

Ι=ϒ B

Ι=∼ =AnΙ=ϒ AnΙ=∼ AnΙ=ϒ

Ι=∼ AnΙ=∼ AnΙ=∼ AnΙ=∼

n-1

Ι=∼ B

n-1

Ι=ϒ B

Ι=∼ (A*)nΙ=ϒ (B*)nΙ=∼ BnΙ=ϒ

n-1

Ι=ϒ (B*)

n-1

Ι=ϒ AnΙ=∼ BnΙ=ϒ

n-1

Ι=ϒ AnΙ=∼ AnΙ=∼

n-1

Ι=ϒ BnΙ=∼ BnΙ=ϒ

n-1

Ι=ϒ BnΙ=ϒ BnΙ=ϒ

n-1

Ι=∼ (A*)nΙ=ϒ AnΙ=∼

1110 VDU, film mode, phase 0, NTSC p(ma)Ι=∼ p(mb)Ι=ϒ p(ma)Ι=∼ p(mb)Ι=ϒ

1111 VDU, film mode, phase 1, NTSC p(mc)Ι=∼ p(md)Ι=ϒ p(mnc)Ι=∼ p(mnd)Ι=ϒ

Table 71 Static operation modes (only valid for ADOPMOM=0, RMODE=0)

)

p(a): a field - motion compensated; p(b): b field - motion compensated

p(c): c field - motion compensated; p(d): d field - motion compensated

p(ma): a field - motion compensated film mode; p(mb): b field - motion compensated film mode

p(mc): c field - motion compensated film mode; p(md): d field - motion compensated film mode

p(mnc): c field - motion compensated film mode for NTSC

p(mnd): d field - motion compensated film mode for NTSC

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Input field A Input field B

STOPMOM Scan rate conversion algorithm Output field

phase 0

0000 VDU, camera mode p(cd)*

0001 VDU, film mode, phase 0, PAL p(mcd)Ι=∼Ηϒ p(mab)Ι=∼Ηϒ

0010 VDU, film mode, phase 1, PAL p(mab)Ι=∼Ηϒ p(mcd)Ι=∼Ηϒ

0011 Frame repetition, AB (A

0100 Frame repetition, AB median (A

0101 Simple 50, AA*, B*B (A

1100 Field repetition, AA* (A

1101 Field repetion, BB* ((B*)

1110 VDU, film mode, phase 0, NTSC p(mab)Ι=∼Ηϒ p(mab)Ι=∼Ηϒ

1111 VDU, film mode, phase 1, NTSC p(mcd)Ι=∼Ηϒ p(mnc)Ι=∼Ηϒ

)

Ι=∼Ηϒ p(ab)Ι=∼Ηϒ

n Bn-1

ΦΙ=∼Ηϒ (An BnΦΙ=∼Ηϒ

n-1

(B*)

ΦΙ=

∼Ηϒ

(A*)nΦΙ=

∼Ηϒ

(A*)nΦΙ=

∼Ηϒ

n-1 Bn-1

ΦΙ=

∼Ηϒ

Output field phase 2/0

((A*)n BnΦΙ=

∼Ηϒ

((B*)n BnΦΙ=

∼Ηϒ

(An (A*)nΦΙ=

∼Ηϒ

n-1 Bn-1

((B*)

∼Ηϒ

ΦΙ=

Table 72 Static operation modes (only valid for ADOPMOM=0, RMODE=1)

)

p(ab): a+b field - motion compensated

p(cd): c+d field - motion compensated

p(mab): a+b field - motion compensated film mode

p(mcd): c+d field - motion compensated film mode

p(mnc): c field - motion compensated film mode for NTSC

For STOPMOM=0000 (Micronas VDU) the high performance motion compensation algorithm is used for scan rate conversion which results in a high performance line flicker reduction, double contour elimination and perfect motion display.

The table Table 73 "Special combinations of STOPMOM and ADOPMOM" on page 92 explains some important combinations of both registers. It is possible to force some modes like VDU CAMERA, VDU PAL film mode and VDU NTSC film mode with manual or automatic phase detection in case of film mode.

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STOPMOM ADOPMOM Description

0000 000 force VDU CAMERA mode

0001 000 force VDU PAL film mode Phase 0

0010 000 force VDU PAL film mode Phase 1

0001 100 force VDU PAL with automatic phase detection; PAL film mode is set

only once, if it is detected; after that it will be fixed until another mode is selected from the user; STOPMOM 0001 or 0010 is selected automatically

0010 100 same as STOPMOM 0001 and ADOPMOM 100

1110 100 force VDU NTSC film mode with automatic phase detection; NTSC film

mode is set only once, if it is detected; after that it will be fixed until another mode is selected from the user; STOPMOM 1110 and STOPMOM 1111 is selected automatically

1111 100 same as STOPMOM 1110 and ADOPMOM 100

0001 101 force VDU PAL with automatic phase detection; PAL film mode is set

only once, if it is detected; after that it will be fixed until another mode is selected from the user; in addition STOPMOM 0011 will be selected if GMOTION is zero; STOPMOM 0001 or 0010 or 0011 is selected automatically

0010 101 same as STOPMOM 0001 and ADOPMOM 101

1110 101 force VDU NTSC film mode with automatic phase detection; NTSC film

mode is set only once, if it is detected; after that it will be fixed until another mode is selected from the user; in addition STOPMOM 0011 will be selected if GMOTION is zero;STOPMOM 1110 or STOPMOM 1111 or STOPMOM 0011 is selected automatically

1111 101 same as STOPMOM 1110 and ADOPMOM 101

Table 73 Special combinations of STOPMOM and ADOPMOM

The table Table 74 "Display line-scanning pattern sequence" on page 93 shows all possible display line-scanning pattern sequences for the different static operation modes and the lines per field value between two consecutive output V-Syncs. It is assumed, that in case of freerunning-mode LPFOP=156 and in locked-mode the number of lines of the incoming field is 312.5.

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Display line-scanning pattern sequence

∼∼∼∼ 312 313 312 313

∼ϒ∼ϒ 312.5 312.5 312.5 312.5

ϒϒϒϒ 313 312 313 312

ϒ∼ϒ∼ 312.5 312.5 312.5 312.5

∼∼ϒϒ 312 312.5 313 312.5

ϒϒ∼∼ 313 312.5 312 312.5

1. to 2. 2. to 3. 3. to 4. 4. to 5.(1.)

Table 74 Display line-scanning pattern sequence

The table below defines the static operation modes for the slave channel. The slave channel is synchronized to the master channel. Therefore only modes with the same output line-scanning pattern as the chosen master channel mode are allowed. Several modes depend on the I²C Bus parameter MEMOP.

STOPMOS Scan rate conversion algorithm allowed for

RMODE

allowed output line-scanning pattern

allowed MEMOP

000 Median, ABAB 0 ∼ϒ∼ϒΙ=ϒ∼ϒ∼ 00 SRC

001 Frame repetition, ABAB 0 ∼ϒ∼ϒΙ=ϒ∼ϒ∼ 00 SRC

010 Simple 100, AABB 0 ∼∼ϒϒΙ=ϒϒ∼∼ all

011 Field repetition, AAAA I 0 ∼ϒ∼ϒΙ=ϒ∼ϒ∼ all

100 Field repetition, AAAA II 0 ∼∼∼∼Ι=ϒϒϒϒ all

101 Field repetition, BBBB I 0 ∼ϒ∼ϒΙ=ϒ∼ϒ∼ all

110 Field repetition, BBBB II 0 ∼∼∼∼Ι=ϒϒϒϒ all

111 not defined 0

000 Median, AB 1 ∼Ηϒ 00 SRC

001 Frame repetition, AB 1 ∼Ηϒ 00 SRC

010 Line doubling, AB 1 ∼Ηϒ all

011 Line doubling, AA 1 ∼Ηϒ all

100 Intra field interpolation A+A* 1 ∼Ηϒ 01 SSC

101 Line doubling, BB 1 ∼Ηϒ all

110 not defined 1

111 Intra field interpolation A+A*, B*+B 1 ∼Ηϒ 01 SSC

Table 75 Static operation modes slave

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The adaptive operation modes (ADOPMOM) define a dynamic switch between different static operation modes controlled by several internal signals. The start point of all modes is the actual chosen STOPMOM as described before. The tables below shows the different adaptive operation modes. The internal used control signals are GMOTION, MOVTYP, MOVMO and MOVPH (compare "Global motion, film mode and phase detection" on page 108). Furthermore the internal control signal VTSEQ exists. In case of I²C Bus parameter VCRMODEM=1, VTSEQ is still zero. If VCRMODEM=0, VTSEQ can be equal one (compare "Input sync controller (ISCM/ISCS)" on page 26). In this cases the scan rate conversion is forced to a simple field based scan rate conversion algorithm. All internal control signals GMOTION, MOVTYP, MOVMO and MOVPH are also readable by the I²C Bus interface.

Basic adaptive operation modes (RMODE = 0 (interlaced)):

off: ADOPMOM=000/001

MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOSint

x x x x x STOPMOM STOPMOS

VCRMODE off: ADOPMOM=010

MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOSint

x x x 0 x STOPMOM STOPMOS

x x x 1 x Simple 100,

AABB, 0101

Still picture mode: ADOPMOM=011

MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOSint

x x x 0 0 Frame repetition,

ABAB, 0011

x x x 0 1 STOPMOM STOPMOS

x x x 1 x Simple 100,

AABB, 0101

Simple 100, AABB, 010

STOPMOS

Simple 100, AABB, 010

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Film mode I; ADOPMOM=100

MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOSint

0 x x 0 x STOPMOM STOPMOS

1000x VDU, film mode,

phase 0, PAL, 0001

1100x VDU, film mode,

phase 1, PAL, 0010

1010x VDU, film mode,

phase 0, NTSC, 1110

1110x VDU, film mode,

phase 1, NTSC, 1111

x x x 1 x Simple 100,

AABB, 0101

Film mode II: ADOPMOM=101

MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOSint

x x x 0 0 Frame repetition,

ABAB, 0011

0 x x 0 1 STOPMOM STOPMOS

STOPMOS

Simple 100, AABB, 010

STOPMOS

1 0 0 0 1 VDU, film mode,

phase 0, PAL, 0001

1 1 0 0 1 VDU, film mode,

phase 1, PAL, 0010

1 0 1 0 1 VDU, film mode,

phase 0, NTSC, 1110

1 1 1 0 1 VDU, film mode,

phase 1, NTSC, 1111

x x x 1 x Simple 100,

AABB, 0101

STOPMOS

Simple 100, AABB, 010

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Film mode III: ADOPMOM=110

MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOSint

0 x x 0 x STOPMOM STOPMOS

1 0 x 0 x VDU, film mode,

phase 0, PAL, 0001

1 1 x 0 x VDU, film mode,

phase 1, PAL, 0010

x x x 1 x Simple 100,

AABB, 0101

Film mode IV: ADOPMOM=111

MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOSint

x x x 0 0 Frame repetition,

ABAB, 0011

0 x x 0 1 STOPMOM STOPMOS

1 0 x 0 1 VDU, film mode,

phase 0, PAL, 0001

1 1 x 0 1 VDU, film mode,

phase 1, PAL, 0010

STOPMOS

Simple 100, AABB, 010

STOPMOS

x x x 1 x Simple 100,

AABB, 0101

Simple 100, AABB, 010

Adaptive operation mode (RMODE = 1 (progressive)):

off: ADOPMOM=000/001

MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOSint

x x x x x STOPMOM STOPMOS

VCRMODE off: ADOPMOM=010

MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOSint

x x x 0 x STOPMOM STOPMOS

x x x 1 x Simple 50, 0101 Line doubling, AB,

010

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Still picture mode: ADOPMOM=011

MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOSint

x x x 0 0 Frame repetition,

ABAB, 0011

x x x 0 1 STOPMOM STOPMOS

x x x 1 x Simple 50, 0101 Line doubling, AB,

Film mode I: ADOPMOM=100

MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOSint

0 x x 0 x STOPMOM STOPMOS

1 0 0 0 x VDU, film mode,

phase 0, PAL, 0001

1 1 0 0 x VDU, film mode,

phase 1, PAL, 0010

1 0 1 0 x VDU, film mode,

phase 0, NTSC, 1110

1 1 1 0 x VDU, film mode,

phase 1, NTSC, 1111

STOPMOS

010

STOPMOS

x x x 1 x Simple 50, 0101 Line doubling, AB,

010

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Film mode II: ADOPMOM=101

MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOSint

x x x 0 0 Frame repetition,

ABAB, 0011

0 x x 0 1 STOPMOM STOPMOS

1 0 0 0 1 VDU, film mode,

phase 0, PAL, 0001

1 1 0 0 1 VDU, film mode,

phase 1, PAL, 0010

1 0 1 0 1 VDU, film mode,

phase 0, NTSC, 1110

1 1 1 0 1 VDU, film mode,

phase 1, NTSC, 1111

x x x 1 x Simple 50, 0101 Line doubling, AB,

Film mode III: ADOPMOM=110

MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOSint

STOPMOS

010

0 x x 0 x STOPMOM STOPMOS

1 0 x 0 x VDU, film mode,

phase 0, PAL, 0001

1 1 x 0 x VDU, film mode,

phase 1, PAL, 0010

x x x 1 x Simple 50, 0101 Line doubling, AB,

STOPMOS

010

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Film mode IV: ADOPMOM=111

MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOSint

x x x 0 0 Frame repetition,

ABAB, 0011

0 x x 0 1 STOPMOM STOPMOS

1 0 x 0 1 VDU, film mode,

phase 0, PAL, 0001

1 1 x 0 1 VDU, film mode,

phase 1, PAL, 0010

x x x 1 x Simple 50, 0101 Line doubling, AB,

STOPMOS

010

Table 76 Adaptive operation modes

Example for explanation of the adaptive operation modes:

ADOPMOM = 4: Film mode I, RMODE=0

In this case the scan rate conversion algorithm is controlled by the signal MOVMO, MOVTYP and MOVPH. If MOVMO is equal 0 the scan rate conversion mode is defined by STOPMOM and STOPMOS (e.g. Micronas VDU). If MOVMO is equal 1 and MOVTYP is equal 0 the scan rate conversion algorithm is changed depending on the MOVPH signal to Micronas VDU, Film mode, PAL, phase 0 or 1. If MOVMO is equal 1 and MOVTYP is equal 1 the scan rate conversion algorithm is changed depending on the MOVPH signal to Micronas VDU, Film mode, NTSC, phase 0 or 1. In case of film mode PAL, the MOVPH signal is constant for the applied material. In case of Film mode NTSC, the MOVPH signal changes each 2

or 3th field, respectively.

I²C Bus

Sub address Description

parameter

STOPMOM 48h STatic OPeration MOdes Master

STOPMOS 4Ah STatic OPeration MOdes Slave

ADOPMOM 49h ADaptive OPeration MOdes Master

Table 77 Output write I²C Bus parameter

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5.8 Motion estimation

The 3-D Recursive Search Block-Matching algorithm was introduced as a high performance low-cost motion estimation algorithm suitable for demanding scan rate conversion applications. The figure below explains the principle of the block matching algorithm. The result is a best matching vector, which contains information about velocity and direction of a block at position (x,y).

(x,y)

(vx,vy)

(x,y)

time T-1

me01

time T

Figure 41 Principle of block matching

The main characteristics of the motion estimator inside of the SDA 9415 are listed in the table below.

I²C Bus parameter

Horizontal range +/-32 pels

Vertical range +/-24 lines

Block size 8x8 (HxV) pels (frame grid)

Accuracy +/- 1 pels

Candidates 8 (2x3 + 2)

Amount of blocks 90*72 (HXV)

Table 78 Key I²C Bus parameters of the 3-D RS motion estimation

100 Micronas

Datasheet SDA9415-B13 Datasheet (Micronas Intermetall)

Specifications and Main Features

Frequently Asked Questions

User Manual