Datasheet SDA9380-B21 Datasheet (Micronas Intermetall)

PRELIMINARY DATA SHEET

SDA 9380-B21
EDDC
Enhanced Deflection
Controller and
RGB Processor

Edition Feb. 28, 2001
6251-549-1PD

SDA 9380 - B21 Preliminary Data Sheet

Document Change Note

1

DS

Date Page Changes compared to previous issue

2 31.03.98 Version 02

3 17.07.98 Document state 03 corresponds to silicon version A11

23.07.98 3 block diagram changed

23.07.98 46 bandwidth of YUV increased (new value 30 MHz)

27.07.98 27 Vertical component of SCP changed (not equals internal signal VBL!)

07.08.98 4, 5, 6 Pin configuration changed

09.09.98 14, 17, 20 Description of PMW byte changed

14.09.98 43 SCP output level changed (supply voltage for SCP is V

DD(MC)

16.09.98 14,15 Sequence of I²C control items changed, new items added

16.09.98 24 Bit SLBLKS added to RGB control byte 1

16.09.98 20 Detailed description of the I²C item PWM control byte

16.09.98 25, 26 Detailed description of the items Average beam current limit character­istics, Peak drive limit, Soft clipping

16.09.98 34 Explanation of the items Peak dark detection top border, bottom border,
left border, right border

18.09.98 21 I²C bit KILLZIP deleted, KILLZIP function remains implemented

18.09.98 10, 21, 39 I²C bit HSWID deleted

18.09.98 10, 21, 39 I²C bit HSWMI added

18.09.98 10, 39 Positive and negative polarity of HSYNC allowed (int. normalization)

20.10.98 1, 3, 10, 39 18.75 kHz line frequency added

27.10.98 14, 31, 32 End of V-blanking also programmable by VBE if JMP=0

12.11.98 31 Specification of end of V-blanking component of SCP changed

19.11.98 21 3 MSBs of PLL control byte 1 must be 0 instead of don’t care

24.11.98 4 Pin configuration changed

02.12.98 40 HSAFE input voltage at 31.25 kHz and 38 kHz specified

04.12.98 40 VREFP, VREFH, VREFL are internal reference voltages

04.12.98 39 Input BSOIN, delay t

changed from 30 lines to 42 lines

D2

04.12.98 15 Default value of saturation control changed form 0 to -12

18.01.99 19 I²C bus bits NR, NL2...NL0 of Vertical sync byte control deleted

21.01.99 1, 7, 11 Text changed because the vertical noise reduction has been removed

21.01.99 11 Remark for switching to external clock mode added

22.01.99 5, 6 Pin description changed

05.02.99 7, 8 Description of Black Switch Off (BSO) changed

26.02.99 37 VSS, SUBST total voltage differentials added

15.03.99 2, 14, 46 Higher resolution of D/A output (6 bit -> 8 bit), INL changed (1 -> 2 LSB)

15.03.99 15, 43 Contrast setting with resolution of 8 bit instead of 6 bit

15.03.99 15, 44 Brightness setting with resolution of 8 bit instead of 6 bit

16.03.99 43 NTSC/US matrix changed

Micronas i 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

1

DS

Date Page Changes compared to previous issue

24.03.99 46 DAC output D/A: DNL changed from +-0.5 LSB to +-1 LSB

29.03.99 22 IIC bus: ABLTCS1, 0 added

29.03.99 25 IIC bus: GAIN2 added, MODE changed

30.03.99 26 IIC bus: Peak drive limit, bit 3 added (hidden bit for Black stretch)

07.04.99 38 Input BSOIN: hysteresis added

12.04.99 22, 25, 15 IIC bus: ABLTCS1, 0 deleted, MODE default field frequent, Tdown
independent of MODE, default value for IIC reg. 27h set to -64

13.04.99 12 18.75kHz only possible with internal clock generation

19.04.99 45, 46 I²C bus specification completed

19.04.99 48 Hysteresis of H35K, H38K adjusted

19.04.99 19 PWMC data corrected in case of PWM output is used as switch output

20.04.99 53 Power-on reset thresholds added

20.04.99 17, 28, 29, 39default range of input IBEAM changed

20.04.99 17, 42 I²C bit RDCI added for switching of DCI input range

28.04.99 24, 50 Delay from SVM to RGB outputs reduced

28.04.99 49 Min. Bandwidth of RGB outputs specified

29.04.99 39 Pins for reference voltages VREFP, VREFL deleted

29.04.99 3,4,5,27,46 New output pin PROTON added

29.04.99 3,4,6,30,46 New output pin VBLO added

11.05.99 51, 52 Application information added

21.05.99 15, 43 Nominal saturation changed to -11

31.05.99 9 Delay of BG-pulse to HSYNC in internal clock mode changed

08.06.99 24, 40, 41 Differential input for RGB/YUV 1 removed

10.06.99 30 V-blanking component of SCP corresponds with internal blanking VBL

24.06.99 1, 2 RGB 1 input changed to RGB/YUV1, COR feature added

24.06.99 5 Test pins changed

24.06.99 12, 54, 55 Reset modes of IIC-Registers changed, POR delay changed to 32768

24.06.99 6,12,38,39,

VREFP and VREFL removed, VREFH and VREFC changed

42, 46, 47,

48, 54, 55

24.06.99 40, 51, 52 External capacitances of the quartz oscillator changed to 15pF

24.06.99 40, 41 YUV and RGB inputs bias voltages added

24.06.99 43 Nominal value of saturation changed

24.06.99 46, 47 DAC outputs (E/W, D/A, VD+, VD-) changed

24.06.99 50 SVM output: black level added

24.06.99 54 POR levels changed

28.06.99 12, 58 Text RGB processing, diagrams black stretch and soft clipping added

29.06.99 8 Second paragraph changed (protection circuit)

30.06.99 29 Equations of Vertical EHT compensation changed

Micronas ii 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

1

DS

Date Page Changes compared to previous issue

30.06.99 30 Equations of Horizontal and AFC EHT compensation changed

09.07.99 38, 39 Minimum ambient temperature at operating changed from -20 to 0 °C

09.07.99 21 Bit position 6 of PLL control byte 0 must be set to 0

19.07.99 55 diagrams of BSO modes added

16.08.99 20 PWM control: amplitude of V-parabola reduced

4 29.09.99 Document state 04 corresponds to silicon version B11

29.09.99 41 YUV input levels for HDTV added

29.09.99 23, 41 Low level Y0 input added

26.10.99 46 High level input voltage of I²C bus changed to 0.75*V

15.11.99 42 Second value of V

18.11.99 7, 38, 49,

HD output changed to open drain

clampY

in case of differential input deleted

DD(D)

52, 53

19.11.99 50 Tolerances for black levels added (offset regulation)

19.11.99 39 Tolerances for supply voltages decreased

22.11.99 16, 26, 27 IIC bit YLL moved to reg. 22h, SW and RDCI moved to reg. 29h

22.11.99 23 IIC bits IN1NOM and IN2NOM added

06.12.99 1, 13, 15,

16, 55, 56

Control item Extreme corner pin correction at subaddress 0Eh added,
item D/A moved to subaddress 30h

06.12.99 47 Input leakage current of all inputs specified

13.12.99 26 ABL: Time constants changed

17.12.99 26 ABL: Up time constants changed

21.01.00 4, 5, 52 Pin X1 and X2 exchanged

26.01.00 47 SCP output High level and blanking level changed

11.02.00 7 Last paragraph regarding soft start adapted

11.02.00 22 Warning 4 of previous edition deleted, warning 5 changed (now no. 4)

11.02.00 39 Any rise time of the supply voltages is allowed

10.03.00 49 Minimum value of maximum RGB output voltage changed

29.03.00 20 PWM control byte: specification of V-parabola amplitude changed

5 29.05.00 Document state 05 corresponds to silicon version B12

29.05.00 3 block delay moved between the blocks brightness and blue stretch

29.05.00 43 Min./Max. values of matrices removed

29.05.00 44 Min./Max. values of black level stretch changed

29.05.00 47 Output LOW and output HIGH value of D/A changed

29.05.00 1, 7, 13, 21 Specified H-frequency range of 15 to 19kHz added

05.07.00 52 Circuit at DCI input changed

05.07.00 34 Explanation of average beam current limit added

6 25.08.00 Document state 06 corresponds to silicon version B21

18.08.00 39 Positive-going of BSOIN upper threshold increased by 50mV

25.08.00 44 Brightness control range changed, nom. brightness removed

Micronas iii 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

1

DS

Date Page Changes compared to previous issue

25.08.00 49 Nominal brightness and measurement levels changed

28.08.00 44 Black stretch level shift changed

28.08.00 50 Foot note 1) added

04.10.00 38 Absolute maximum rating of VDD(MC) = 9V

04.10.00 38 Absolute maximum rating of total power dissipation = 1.28W

04.10.00 46 Supply currents and total power dissipation specified

04.10.00 47 DAC output D/A: LOW and HIGH value changed

04.10.00 47 DAC output E/W: LOW and HIGH value changed

04.10.00 48 DAC output VD+, VD-: LOW and HIGH value changed

04.10.00 50 SVM output signal amplitude changed from 2V to 1.9V nom.

10.10.00 51 System overview Dig. TV 100 Hz changed

16.10.00 38...40 Pin schematic inserted

23.10.00 36 Equations for cut-off and white-drive currents added

25.10.00 29 Equations for Vertical EHT compensation modified

25.10.00 30 Equations for Horizontal EHT compensation modified

22.11.00 45 Max. input capacitance of YUV and RGB inputs specified

22.11.00 50 Standby current specified

22.11.00 50 Total power dissipation changed from max. 1.25W to max. 1.28W

29.01.01 all Infineon logo changed to Micronas

1)... DS = Document state

Micronas iv 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Data Classification

Maximum Ratings

Maximum ratings are absolute ratings; exceeding only one of these values may cause irre­versible damage to the integrated circuit.

Recommended Operating Conditions

Under this conditions the functions given in the circuit description are fulfilled. Nominal con­ditions specify mean values expected over the production spread and are the proposed val­ues for interface and application. If not stated otherwise, nominal values will apply at
TA=25°C and the nominal supply voltage

Characteristics

The listed characteristics are ensured over the operating range of the integrated circuit.

Micronas v 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Contents

1 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.1 Deflection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2.2 RGB Video . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

4 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4.1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

5 System description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5.1 Functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5.1.1 Deflection controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

5.1.2 RGB processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

5.2 Circuit description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5.3 Reset modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.4 Frequency ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.5 I²C-Bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.5.1 I²C-Bus address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5.5.2 I²C-Bus format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5.5.3 I²C-Bus commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

5.5.4 Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5.5.5 Explanation of some control items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

6 Pin schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

7 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

8 Recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9 Characteristics (assuming recommended operating conditions). . . . . . . . . . . . 50

10 Application information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

10.1 System overview Dig. TV 100Hz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

10.2 System overview multisysnc deflection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

10.3 Application circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11.1 Timing diagram of H35K and H38K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11.2 Black Switch-Off diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

11.3 Power On/Off diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

11.4 Standby mode, RESN diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

11.5 Function of H,V protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

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SDA 9380 - B21 Preliminary Data Sheet

11.6 Black Stretch diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

11.7 Soft Clipping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

12 Package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Micronas vii 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

General description

1 General description

The SDA 9380 is a highly integrated deflection controller and RGB video processor for CTV receiv­ers with 15 to 19kHz or 31 to 38kHz line fr equencies . The deflect ion component co ntrols amo ng oth­ers an horizontal drive2001-01-29r circuit for a flyback line output stage, a DC coupled vertical saw­tooth output stage and an East-West raster correction circuit. All adjustable output parameters are
I²C-Bus controlled. Inpu ts are HSYNC and VSYNC. The HSYNC signal is the re ference for the inter­nal clock system which includes the

The RGB processor has two YUV/RGB inputs and one RGB input. One YUV/RGB input and the
RGB input are for SVGA and text/OSD with fast blanking. The RGB output stage has two control
loops for cut off and white level with halt capability in vertical shrink modes. An overall Y output and
an adjustable dela y of the RGB outputs rel ated to thi s signal are suitable for a scan v e loc ity modula­tion circuit.

The supply voltages of the IC are 3.3V and 8V. It is mounted in a P-MQFP package with 64 pins.

=Φ1=and Φ2=control loops.

2 Features

2.1 Deflection

• =No external clock needed

• =Φ1=PLL and=Φ2=PLL on chip

•==Standard line frequencies for NTSC and PAL

•==18.75kHz line fr equency for 625 lines/60 Hz

•==Doubled line frequencies for NTSC and PAL, MUSE standard, DTV standard

• Also suitable for VGA, Macintosh (35kHz) and SVGA standard (38kHz, 800*600*60Hz)

• =Automati c s wi tchin g betw een 31 , 35 and 38 kHz in Mon itor mo de with 2 digital outpu ts f or

controlling B+ and 1 analog input to keep watch on it

• =I²C-Bus alignment of all deflection parameters

• =All EW-, V- and H- functions

• =Picture width and picture height EHT compensation

• =Dynamic PH EHT compensation (white bar)

• =Compensation of H-phase deviation (e.g. caused by white bar)

• =Upper/lower EW-corner correction separately adjustable

• =Extreme EW-corner correction (coefficient of sixth order) for super flat tubes

• =V-angle and V-bow correction

• =Two special control items for vertical zoom/shrink and scroll function with absolutely

correct tracking of the E/W and HD-output signals

• =No re-adjustment of E/W after changing vertical S-correction and linearity needed

• =H-frequent PWM output signal for generating an adjustable vertical frequent parabola or

a constant pulse width, selectable by I²C

• =H- and V-blanking time adjustable

• =Partial overscan adjustable to hide the cut off control measuring lines in the reduced

scan modes

• =Self adaptation of V-frequency / number of lines per field between 192 and 680 for
each possible line frequency

• =Selectable Black Switch-Off behaviour via I²C-Bus

Micronas 1-1 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Features

• =Protection against EHT run away (X-rays protection)

• =Protection against missing V-deflection (CRT-protection)

• =D/A ouput with 8 bit resolution for general purpose

• =Digital output for general purpose, co ntrolled by I2C-Bus

• =Selectable softstart of the H-output stage

2.2 RGB Video

• Two universal YUV/RGB inputs and one RGB input, one YUV/RGB and RGB input with
fast blanking capability

• One fast blank input with contrast reduction capability

• Switchable color difference matrix for PAL/SECAM, NTSC(U.S.), NTSC(Japan) and

HDTV

• Common saturation, brigh tness and contrast control for all three input channels possible

• Cut off and white level control loop

• Halt command for white level control loop to switch off the white level reference lines in

vertical shrink mode

• Black stretching of non-standard input signals

• Selectable blue stretch circuit shifting white towards light blue

• Peak drive limiter with soft clipping, adjustable per I²C

• Average beam current limiter, adjustable per I²C

• Lumi nance ou tput si gnal SVM f or scan v el ocity modu lation ; adju stable dela y f rom SVM to

the RGB outputs

Micronas 2-2 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Block diagram

3 Block diagram

φ2

SWITCH

D/A

VBLO

SCP

HPROT

VPROTSSD

PROTON

φ2

φ2φ2

R

VSYNC
HSYNC

HSAFE

G

B

SCL
SDA

BSOIN

RESN

TEST

FH1_2

CLEXT

CLKI

H35K
H38K

X1
X2

RGB 2

FBL 2
FBL 1

/

Y

U

V

I²C

CONTROL

PROTECTION

START UP

H-OUT

V-OUT

EW-OUT

HD

VD+
VD-

E/W

CLL

PWM

PLL

CLAMP

3

1

CLAMP

3

MATRIX

3

MATRIX

3

YUV

3

SWITCH

YUV

3

Y

UV

2

3

PW/PH-CORR

AVERAGE

BEAM LIMITER

BLACK

STRETCH

SATURATION

CONTROL

UV

Y

PWM

IBEAM

SVM

Y

U

V

R

G

/

B

VDD(A1..4)

VSS(A1..4)

VDD(D1..2)
VSS(D1..2)

VDD(MC)

VSS(MC)

SUBST

0

3

CLAMP

BRIGHTNESS

CONTROL

MATRIX

3

3

YUV

CONTRAST

CONTROL

3

RGB

MATRIX

3

MEASURE

PULSES

3

DELAY

CUT OFF +

WHITE POINT

DCI

3

BLUE STRETCH

PEAK DRIVE

3

LIMITER

3

VREFC

OUTPUT

BUFFER

VREFH

VREFN

ROUT
GOUT
BOUT

Micronas 3-3 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Pin configuration

4 Pin configuration

CLKI

X2
X1

CLEXT

TEST

SUBST

RESN

SCL

SDA

VDD(D)

VSS(D)

HD
H35K
H38K
PWM

VSS(D)

VDD(D)

SSD

SWITCH

64 63 62 61 60 59 58 57 56 55 54 53 5152 50 49

1

SVM

R2

G2

B2

VDD(MC)

ROUT

GOUT

BOUT

SCP

VSS(MC)

2
3
4
5
6
7
8
9

SDA 9380

10
11
12
13
14
15
16

17 18 19 20 21 22 23 24 25 26 27 28 3029 31 32

D/A

FH1_2

Φ=2

HSYNC

VSS(A1)

VDD(A1)

VDD(A2)

E/W

VSS(A2)

VD-

VD+

VPROT

VSS(A3)

VDD(A3)

FBL2

FBL1

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

HSAFE

HPROT

B/V 1
G/U 1
R/Y 1
VSS(A4)
V/B 0
U/G 0
Y/R 0
VDD(A4)
DCI
VREFC
VREFN
VBLO
VREFH
PROTON
IBEAM
BSOINVSYNC

Micronas 4-4 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Pin configuration

4.1 Pin description
Pin No. Name Type Description

1 CLKI I/TTL Input for external line locked clock *)
2X2QReference oscillator output, Crystal
3X1IReference oscillator input, Crystal
4 CLEXT I/TTL Switching between internal (L) and external clock (H) *)
5 TEST I/TTL Switching between normal operation (TEST=L) and test mode

(TEST=H: pins 4, 12, 13, 14, 15, 17, 49, 50, 63, 64 are additio­nal test pins)

6SUBSTSSubstrate pin, has to be connected to ground whenever a

power supply or signal is applied

7 RESN I/TTL Reset input, active Low
8SCLII²C Bus clock

9SDAIQI²C Bus data
10 VDD(D) S Digital supply
11 VSS(D) S Digital ground
12 HD Q Control signal output for H driver stage (open drain)
13 H35K Q/TTL Goes High when frequency of HSYNC is about 35kHz or more
14 H38K Q/TTL Goes High when frequency of HSYNC is about 38kHz
15 PWM Q/TTL Pulse width modulated control signal output
16 VSYNC I/TTL V-sync input
17 FH1_2 I/TTL Switching between 1f
18 HSYNC I HSYNC input (CLEXT=H: TTL; CLEXT=L: analog) *)
19 VDD(A1) S Analog supply
20 VSS(A1) S Analog ground
21 Φ2ILine flyback for H-delay compensation
22 VDD(A2) S Analog supply
23 VSS(A2) S Analog ground
24 E/W Q Control signal output for East-West raster correction
25 D/A Q Output of an I²C Bus controlled DC voltage
26 VD+ Q Control signal output for DC coupled V-output stage
27 VD- Q Like VD+
28 VDD(A3) S Analog supply
29 VSS(A3) S Analog ground
30 VPROT I Watching external V-output stage (input is the V -saw-tooth from

feedback resistor)

31 HPROT I Watching EHT (input is e.g. H-flyback)
32 HSAFE I Watching B+ when frequency of HD has to be decreased
33 BSOIN I Input for starting Black Switch-Off
34 IBEAM I Input for a beam current dependent signal for stabilization of

width, height and H-phase

35 PROTON Q/TTL Protection on (goes High after response of H- or V-protection)

mode (L) and 2fH mode (H)

H

Micronas 4-5 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Pin configuration

Pin No. Name Type Description

36 VREFH IQ Reference voltage
37 VBLO Q/TTL Vertical blanking output
38 VREFN IQ Ground for VREFH
39 VREFC I Reference current input
40 DCI I Dark current input for cut off and white level control
41 VDD(A4) S Analog supply
42 Y/R 0 I Luminance or R input
43 U/G 0 I U signal or G input
44 V/B 0 I V signal or B input
45 VSS(A4) S Analog ground
46 R/Y 1 I First R or Y input for insertion
47 G/U 1 I First G or U input for insertion
48 B/V 1 I First B or V input for insertion
49 FBL1 I Fast blanking input for RGB1
50 FBL2 I Fast blanking input for RGB2
51 R2 I Second R input for insertion
52 G2 I Second G input for insertion
53 B2 I Second B input for insertion
54 VDD(MC) S Analog supply for RGB output stage
55 ROUT Q R output
56 GOUT Q G output
57 BOUT Q B output
58 SCP Q Blanking signal with H- and color burst component

(V-component selectable by I²C Bus)

59 VSS(MC) S Analog ground for RGB output stage
60 SVM Q Luminance output for scan velocity modulation circuit
61 VDD(D) S Digital supply
62 VSS(D) S Digital ground
63 SSD I/TTL Disables softstart
64 SWITCH Q/TTL Output of an I²C Bus controlled switch (register 00, bit SW)

*) The external clock mode can not be used with 18.75, 33.75kHz, 35kHz and 38kHz l ine frequency.

Micronas 4-6 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

5 System description

5.1 Functional description

5.1.1 Deflection controller

The main input signals are HSYNC with a frequency range of about 31 to 38kHz and VSYNC with
vertical frequencies of 50 to 120 Hz. When connecting pin FH1_2 with Low level a line frequency of
15 to 19kHz is suitable.

For displaying computer signals horizontal f requencies up to 38 kHz can be processed.
In the selectable Monitor mode the adaptation to the input frequency in the range of 31.25 to 38kHz

is done automatically. Two outpu t pi ns (H35K and H38K) for controlling e.g. the supply voltage of the
line output stage indicate the frequency of HSYNC. When the H-frequency is increasing, these out­puts are stable until the frequency of HSYNC appears on the output HD (see 11.1). In case of
decreasing H-frequency they are changed immediately to flag the new detected frequency but
change of the PLL frequency will be not allowed until the supply voltage of the H-output stage (B+)
is decreased. Pin HSAFE is used to watch B+.

The output signals control the horizontal as well as the vertical deflection stages and the East-West
raster correction circuit.

The H-output signal HD (open drain output) compensates the delays of the line output stage and its
phase can be modulated vertical frequent to remove horizontal distortions of vertical raster lines (V­Bow, V-Angle). Time reference is the middle of the front and back edge of the line flyback pulse. A
positive HD pulse switches off the line output transistor. Maximal H-shift is about 2.25 µsec for

=31kHz.

f

H

Picture tubes with 4:3 or 16:9 aspect ratio can be used by adapting the raster to the aspect ratio of
the source signal.

The V-output saw-tooth signals VD- and VD+ controls a DC coupled output stage and can be dis­abled. Suitable blanking signals are delivered by the IC.

The East-West output signal E/W is a vertical frequent parabola of 6th order, enabling an extreme
corner correction for super flat tubes. The common corner correction realised with coefficients of
fourth order, is separately adjustable for the upper and lower part of the screen.

The pulse width modulated horizontal frequent output signal PWM has two options. A vertical fre­quent parabolic function or a constant pulse width in each line, selectable by I²C, is available. After
external integration the parabola may be used for vertical dynamic focusing rsp. the DC voltage for
adjustment of H-offset or rotation .

2

The output D/A delivers a variable DC signal and an I
general purpose.

The picture width and picture height compensation (PW/PH Comp) processes the beam current
dependent input signal IBEAM with effect to the outputs E/W and VD to keep width and height con­stant and independent of brightness.

The alignment parameter AFC EHT Compensation enables to adjust the influence of the input sig­nal IBEAM on the horizontal phase.

The selectable start up circuit controls the energy supply of the H-output stage during the receiver's
run up time by smooth decreasing the line output transistors switching frequency down to the nor­mal operating value (softstart). HD starts with about 1.7 times the line frequency and converges

Micronas 5-7 2001-01-29

C Bus controlled digital output is available for

SDA 9380 - B21 Preliminary Data Sheet

System description

within 85ms to its fi nal value. The high time is kept constant. The normal operating pulse ratio H/L is
either 45/55 or 40/60 (selectable by I²C). A watch dog function limits an increasing of the HD period
to max. +10%.

2

The implemented Black Switch-Off behaviour is defined by two I
enabled the signal at BSOIN (e.g. the supply voltage of the line output stage) is watched. If its level
does not come up to a defined threshold Black Swich-Off is started (see 11.2). At first the RGB out­puts are switched to conti n uous b l anking immedi ately and th e v e rtical output signals are changed to
about 115..120% overs can. After a delay of 42 lines the picture tube capacitance is discharged with
a current of some mA. From now the vertical overscan rate is calculated depending on the actual
voltage at BSOIN to get the desired deflec tion angle. Three relations are selectable by I
voltage at BSOIN is dropped down to about 20% of its initial value the output HD and the overscan
calculation may stop.

The protection circuit watches an EHT reference and the saw-tooth of the vertical output stage. If
the EHT succeeds a defined threshol d or if t he V-deflection fails (refer to 11.5) the relat ed bit is se t in
the status byte and the output PROTON goes High. The output HD is deactivated (H-level) immedi­ately independent of the selected Blac k Switch-Off function.

C bits (BSO1, BSO0). When

2

C. After the

HPROT: input V

< V2 continuous blanking

i

> V1 HD disabled

V

i

≤=V

V2

< V1 operating range

i

VPROT: vertical saw-tooth voltage

< V1 in first half of V-period

V

i

> V2 in second half : HD disabled

or V

i

The pin SCP delivers the composite blanking signal SCP. It contains burst (V

) and selectable V-blanking (control bit SSC). The phase and width of the H-blanking period

(V

HBL

can be varied by I

BD = 1 : T
BD = 0, BSE = 0 (default value) : T
BD = 0, BSE = 1(alignment range) : T

2

C-Bus. For the timing following settings are possible :

= 0

BL

= tf (H-flyback time)

HBL

= (4 * H_blanking-time + 1) / CLL

HBL

: T

= (H_shift + 4 * H_blanking_phase

DBL

), H-blanking HBL

b

- 2*H_blanking_time + 45) / CLL

SSC = 0 : TBL = T
SSC = 1 : T

is always T

BL

during V-blanking period

VBL

HBL

Micronas 5-8 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

BG-pulse width t
Delay to HSYNC t

b

db

54 / CLL
internal clock: (78-4*Internal_H-sync_phase)/ CLL
external clock: (38-4*Internal_H-sync_phase)/ CLL

Micronas 5-9 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

5.1.2 RGB processing

To provide an accurate biasing of the picture tube the offsets and gains of the RGB output stages
are continuously adjuste d b y a cut of f and white l e v el cont rol loop. Leakage, cut off and whi te current
are measured each frame during vertical flyback at the DCI input. The position of the measurement
lines is adjustable by IIC bus (see page 31). The reference currents for the cut off and white levels
are adjusted by IIC bus with a 6 bit parameter for each output and a common 3 bit gain parameter.
Because the video amplifiers are part of the control loops, the overall gain and offset is no more
adjustable in this stage. For proper dimensioning of the video amplifiers there is an IIC status bit
(CLOW), which is 0 when all offset and gain actuators of the RGB outputs are within 50% of its full
range. The control loops can be switched to halt mode to switch off the measurement lines in verti­cal shrink mode. When the TV screen is switched on brightness and contrast ramp up in a soft start
mode as soon as the cut off control loop is locked.

There are three circuits implemented for beam current limiting:

-First there is a circuit for accurate average beam current limiting. The beam current is measured at
the Ibeam input and limited by reducing first contrast and, after half contrast is reached, brightness
too. All par ameters (limit v alue , ga in, up time const ant and dow n time constant ) are adjustab l e by II C
bus.

-Second a peak drive limiter circuit is implemented for the hi gher frequency content of t he video sig­nal. It reduces contrast when a limit value is exceeded by the R, G or B video signals. Also all
parameters (limit value, up time constant and down time constant) are adjustable by IIC bus.

-Third there is a soft clipper for the very high frequency content of the video signal. It limits the R, G
or B video signals according to t he diagram at 11.7. Limit value and slope are adjust able by IIC bus.

The TV screen can be switched to blue by IIC bus when no video signal is a vailable.
When the blue stretch function is activated by IIC bus, the gain of the red and green output is

reduced by 17% for amplitudes more than 80% of the nominal amplitude. This shifts white towards
light blue.

A black stretch function (switchable by IIC bus) stretches video signals with a black level which is
higher than the clamping level towards black. Therefore the peak dark value of the video signal is
stored. The height of the peak dark value determines the amount of stretch (diagram at 11.6). The
screen area in which the peak dark detector is enab led i s prog r ammab le b y I IC b us. So it is possible
to screen black borders of the picture (e.g. letter box format) which otherwise prevent the desired
function of black stretch.

An overall luminance output is provided for supplying a circuit for scan velocity modulation. The
delay of the RGB outputs to the luminance output is adjustable by IIC bus. So a proper alignment of
the video signals and the current in the SVM coil is possible.

Micronas 5-10 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

5.2 Circuit description

The HSYNC is reference for a numeric PLL. This PLL generates a clock which is phase locked to
the incoming horizontal sync pulse and exactly 864 times faster than the horizontal frequency. The
polarity of the external horizontal sync pulses may be positive (see figure below) or negative. In
case of negative polarity the i ncoming HSYNC signal is automatically inverted for an easier appli ca­tion in VGA or SVGA mode.

V

HSmax

V

HSpp

V

HSmin

t

W

Incoming signal HSYNC (internal clock)

Pulse width tw for I2C-bus Bit ’HSWMI’=0:

1.5

µs ... 4.5µs (High or Low level) FH1_2 = High
µs ... 9.0µs (High or Low level) FH1_2 = Low

3.0

Pulse width t

(The specified pulse width depends on the I²C-bus bits INCR4...INCR0 rsp. PLL clock frequency.
The above values are valid for INCR = 6. For higher INCR values the allowed pulse width is
decreasing proportional to the increasing PLL clock frequency.)

The described input signal is first applied to an A/D converter. Conversion takes place with 7 bits
and a nominal frequency of 27 MHz. The digital PLL uses a low pass filter to obtaine defined slopes
for further measurements (PAL/NTSC applications). In addition the actual high and low level of the
signal as well as a threshold v alue i s e valuated and used to calculat e the phas e error bet wee n inter­nal clock and external horizontal sync pulse. By means of digital PI filtering an increment is gained
from this. The PI filter can be set by the I
optimal in relation to either the TV or VCR mode. Moreover it is possible to adapt the nominal fre­quency by means of 5 I
bus bit GENMOD offers the possibility to use the PLL as a frequency generator which frequency is
controlled by the INCR bits.

for I2C-bus Bit ’HSWMI’=1:

w

0.8

µs ... 4.5µs (High or Low level) FH1_2 = High
µs ... 9.0µs (High or Low level) FH1_2 = Low

1.7

2

C-bus bits (INCR4.. INCR0) to d if ferent horizontal f requenc ies . An additi onal

2

C-bus VCR bit so that the lock-in behaviour of the PLL is

Micronas 5-11 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

Once an increment has been obtained, either from the PI-filter or the I2C-bus, it can be used to
operate the D
portional to the increment. The sa w-tooth is converted into a sinusoidal clo ck signal by means of sin
ROM’s and D/A converters and applied to an analog PLL which multiplies the frequency by 4 (for
detailed explanation see pinning and I
ner the required line loc ked clock is pr ovided to operate the other functional parts of the circuit. If no
HSYNC is applied to pin 18 the system holds its momentary frequency for 2040 lines and following
resets the PLL to its nominal frequency. The status bit CON indicates the lock state of the PLL.
The system also provides a stable HS-pulse for internal use. The phase between this internal pulse
and the external HSYNC is adjustable via I
one TV line.
An external clock (CLKI) can be provided by pin selection (CLEXT = H) or I²C control (SCLIIC = H,
CLEXTIIC = H). This is recommended when using the SDA 9380 with a scan rate conversion sys­tem. The clock frequency has to be 864 · f

18.75, 33.75kHz, 35kHz and 38kHz line frequency. Therefore switching to external clock mode is
only possible when INCR = 6, b ut alw ays allow ed during operat in g without any danger for the H-out­put stage.

The input signal at VSYNC is the vertical time reference. It has to pass a window avoiding too short
or long V-periods in the case of distorted or missing VSYNC pulses. The window allows a VSYNC
pulse only after a minimum number of lines from its predecessor and sets an artificial one after a
maximum number of lines. The win dow size is progr ammable by I

igital Timing Oscillator. The DTO generates a saw-tooth with a frequency that is pro-

2

C-bus description) and minimizes residual jitter. In this man-

2

C bus bits HPHASE. It can be shifted over the range of

HSYNC.

The external clock mode can not be used with

2

C-bus.

V alues whi ch inf luence shape a nd ampli tude of t he output si gnals are t ran smit ted as redu ced binary
values to the SDA 9380 via I²C b us . A CPU which is d esig ned for speed reasons in a pipe li ne struc­ture calculates in c onsideration of feedback signals (e.g. IBEAM) values which exactly represent the
output signals. These values control after D/A conversion the external deflection and raster correc­tion circuits.

The CPU firmware is stored in an internal ROM.

Micronas 5-12 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

5.3 Reset modes

The circuit is only complet ely res et at pow er -on/ off (t iming di ag ram r ef. 11.3). If the pin RESN has L­lev el or during standb y operat ion some parts of the circuit are not aff ect ed (timing diag ram ref. 11.4):

Power-On-Reset

External Reset

(pin RESN=0)

Standby mod e

2

C bit STDBY=1)

(I

HD output High active active
H-protection inactive active active
V-protection inactive active

1)

active

1)

IIC-Interface (SDA, SCL) tristate ready ready
IIC-Register 01..1C set to default values set to default values set to default values
IIC-Register 00, 1D...30h set to default values not affected not affected
Status bit PONRES set to 1
VREFH

not affected not affected inactive

2)

set to 1 not affected

CPU inactive inactive inactive

1)

: inactive if HPROT < V2 (typ. 1.5V)

2)

: can only be read after Power-On-Reset is finished

Note: Power-On-Reset state is deactivated af ter ca. 32768 cycles of the X1/X2 oscillator clock.

RESN=Low and standby state ar e deactivated after ca. 42 cycles of the CLL clock.

5.4 Frequency ranges

HVn

15.625 kHz 50 Hz 625 I

15.75 kHz 60 Hz 525 I

18.75 kHz* 60 Hz 625 I

31.25 kHz 50 Hz
100 Hz

31.5 kHz 60 Hz
70 Hz

120 Hz

33.75 kHz* 60 Hz 1125 I
35 kHz* 66.7 Hz 525 NI
38 kHz* 60 Hz

72 Hz

*) only with internal clock generation

The allowed deviation of all input line frequencies is max.
n

: number of lines per frame

L

L

625 NI / 1250 I
625 I

525 NI / 1050 I
449 NI
525 I

632 NI
525 NI

±4.5%.

Micronas 5-13 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

I : interlaced
NI : non interlaced

If NSA = 0 (subaddr. 01/D5) number of lines per fiel d is selfadaptabl e betw een 192 a nd 680 for each
specified H-frequency.

5.5 I²C-Bus control

5.5.1 I²C-Bus address

1000110

5.5.2 I²C-Bus format

write:

S10001100A Subaddress A Data Byte A

read:

S10001101A Status byte A Data Byte n A

Reading starts at the last write address n. Specification of a sub addres s in readi ng mode is not pos­sible.

S: Start condition
A: Acknowledge
P: Stop condition
NA: Not Acknowledge

An automatically address increment function is implemented.
After switching on the IC, all bits are set to defined states.

*****

*****

AP

NA P

Micronas 5-14 2001-01-29

Micronas 5-15 2001-01-29

5.5.3 I²C-Bus commands

SDA 9380 - B21 Preliminary Data Sheet

Control item

(for deflection)

Deflection control 0
Deflection control 1
Vertical scroll *)
Vertical aspect *)
Vertical shift *)
Vertical size *)
Vertical linearity *)
Vertical S-correction *)
Vertical EHT compensation *)
Horizontal siz e
Pin phase
Pin amp
Upper corner pin correction
Lower corner pin correction
Extreme corner pin correction
Horizontal EHT compensation *)
Horizontal shift
Vertical angle
Vertical bow
AFC EHT compensation *)
Vertical blanking start*)
RGB Reference pulse position*)
Horizontal bl ank in g time
Horizontal bl ank in g phas e
Vertical blanking end*)
Guard band *)
Vertical sync control
Min. No. of lines / field *)
Max. No. of lines / field *)
PWM control
PLL control 0
PLL control 1
Internal H-sync phase

Sub-

addr.

00
01
02
03
04
05
06
07
08
09
0A

0B
0C
0D
0E
0F

10

11

12

13

14

14

15

16

17

17

18

19
1A
1B
1C
1D
1E

D7 D6 D5 D4 D3 D2 D1 D0

see below - - 0 - - -

see below - - 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B6 B5 B4 B3 B2 B1 B0 X -64..+63 -64..+63 0 - - 1/CLL
B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 - - ­B5 B4 B3 B2 B1 B0 X X -32..+31 -32..+31 0 - - ­B3 B2 B1 B0 X X X X 0..+15 0..+15 0 - - line
X X X X B3 B2 B1 B0 0..+15 0..+15 0 BSE = 0 4 line
X X B5 B4 B3 B2 B1 B0 0..+63 0..+63 0 BSE = 0 H-flyback 4/CLL
B5 B4 B3 B2 B1 B0 X X -32..+31 -32..+31 0 - - 4/CLL
B2 B1 B0 X X X X X 0..+7 0..+7 0 - 0 line
X X X B4 B3 B2 B1 B0 0..+31 0..+31 0 GBE = 0 3 half line

see below - - 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 0..+255 0..+255 0 - - 2 lines
B7 B6 B5 B4 B3 B2 B1 B0 0..+255 0..+255 0 - - 2 lines

see below - - 0 - - -

see below 0..+31 6..+21 s. below - - -

see below - - 0 - - ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -96..+119 0 - - 4/CLL

Allowed

range

Effective

range

Default

value

Disabled

by

Default
value if

disabled

Resolu-

tion

System description

Micronas 5-16 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Control item

(for RGB)

RGB control 0
RGB control 1
RGB control 2
Video input mode
Brightness
Contrast
Saturation
Average beam current limit *)
Average beam current limit characteristics
Peak drive limit
RGB control 3
Peak dark detection top border *)
Peak dark detection bottom border *)
Peak dark detection left border *)
Peak dark detection right border *)
White control R *)
White control G *)
White control B *)
D/A

*) see 5.5.5 Explanation of some control items

Sub-

addr.

1F

20
21
22
23
24
25
26
27
28

29
2A
2B
2C
2C
2D
2E
2F

30

D7 D6 D5 D4 D3 D2 D1 D0

see below - - 0 ­see below - - 0 ­see below - - 0 -

see below - - 128 ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 ­B5 B4 B3 B2 B1 B0 X X -32..+31 -32..+31 -11 ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 -

see below - - -64 -

see below - - 0 -

see below - - 0 ­B7 B6 B5 B4 B3 B2 B1 B0 0..+255 0..+255 16 2 lines
B7 B6 B5 B4 B3 B2 B1 B0 0..+255 0..+255 71 4 lines
B3 B2 B1 B0 X X X X 0..+15 0..+15 8 16 pixels
X X X X B3 B2 B1 B0 0..+15 0..+15 8 16 pixels
B5 B4 B3 B2 B1 B0 X X -32..+31 -32..+31 0 ­B5 B4 B3 B2 B1 B0 X X -32..+31 -32..+31 0 ­B5 B4 B3 B2 B1 B0 X X -32..+31 -32..+31 0 ­B7 B6 B5 B4 B3 B2 B1 B0 -128..+127 -128..+127 0 -

Allowed

range

Effective

range

Default

value

Resolution

System description

SDA 9380 - B21 Preliminary Data Sheet

System description

At power on most of the data are zero by default (if not otherwise specified) before transferring indi­vidual values via IIC-bus.
Allowed values out of the effective range are limited, e.g. Internal H-sync phase =127 is limited to

119.
There are two bits (BSE, GBE) in the deflection control byte 1 for disabling some control items. If
one of these bits is “0”, the value of the corresponding control item will be ignored and replaced by
the value “default value if disabled” in the table above.

Micronas 5-17 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

5.5.4 Detailed description

The Deflection control byte 0 includ es the followin g bits:

VOFF STDBY MON SCLIIC RIBM CLEXTIIC HDDC HDE

- VOFF: Vertical off
0: normal vertical output due to control items
1: vertical saw-tooth is switched off ,

vertical protection is disab led

- STDBY: Stand-by mode
0: normal operation
1: stand-by mode (all internal clocks ar e disabled)

- MON: Monitor mo de (G ENMOD bit must b e se t to 0)
0: line frequency must be defined by INCR4..0 (register 1D)
1: automatic detection of line frequency

- SCLIIC: Select clock by IIC
0: select clock by pin CLEXT
1: select clock by IIC bit CLEXTIIC

- RIBM: Input range of IBEAM
0: 0...2.7V
1: 1.8...2.7V

- CLEXTIIC:External clock selected by IIC (only effective if bit SCLIIC = 1)
0: internal clock selected by IIC
1: external clock select ed by IIC

- HDDC: HD duty cycle
0: duty cycle of output HD is 45%
1: duty cycle of output HD is 40%

- HDE: HD enable
0: line is switch ed off (HD disabled, that is H-level)

If BSO1 =1 or BSO0 = 1, no switch-off is possible.

1: line is switched on (HD enabled)
Default value depends on pin SSD

SSD=Low: 0
SSD=High: 1

Micronas 5-18 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

The Deflection control byte 1 includ es the followin g bits:

BSO1 BSO0 NSA NCLP GBE VDC JMP BSE

- BSO1..

BSO0 Black Switch-Off behavi our

00: no Black Switch-Off
01: Black Switch-Off mode 1 (see section 11.2)
10: Black Switch-Off mode 2 (see section 11.2)
11: Black Switch-Off mode 3 (see section 11.2)

- NSA: No self adaptation

0: self adaptation on
1: self adaptation off

- NCLP: No clipping of vertical and east/west drive signals

0: Clipping of vertical and east/west drive signals in vertical zoom mode

(vertical aspect > 0) to reduce power consumption

1: No clipping in vertical zoom mode (vertical aspect > 0)

- GBE: Guard band enable

0: control item for guard band is disabled
1: control item for guard band is enabled

- VDC: Vertical dynamic compensation

0: influence of the beam current input IB EAM on the

vertical saw-tooth is static (´zooming´ correction)

1: influence of the beam current input I BEAM on the

vertical saw-tooth is dynamic (´ripple´ correction)

- JMP: Jump of vertical drive up to overscan position in vertical shrink mode

0: complete reduction of the vertical drive in shrink mode (vertical aspect < 0)
1: no reduction of the vertical drive in shrink mode (vertical aspect < 0) during

RGB reference pulse lines

- BSE: Blanking select enable

0: control items for blanking times are disabled
1: control items for blanking times are enabled

Micronas 5-19 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

The Vertical sync control byte includes the following bits:

XXSSCXNIXXX

- SSC: Sandcastle without VBL

0: output SCP with VBL component
1: output SCP without VBL component

- NI: Non interlace

0: interlace depends on source
1: no interlace

The PWM control byte includes the following bits:

PWMC5 PWMC4 PWMC3 PWMC2 PWMC1 PWMC0 PWMS1 PWMS0

- PWMS1..

PWMS0: PWM select

x0: same duty cycle in each line selected (adjustable by PWMC)
01: positive V-parabola after external integration available (amplitude

adjustable by PWMC)

11: negative V-parabola after external integration available (amplitude

adjustable by PWMC)

- PWMC5..

PWMC0: PWM control

These bits control either the duty cycle or the parabola amplitude
depending on PWMS0 according to the foll owing table (if PWMS0 = 0
also PWMS1 defines the the duty cycle):

PWMC5...PWMC0 Duty cycle

(PWMS0 = 0)

100000 PWMS1/108
110000 (32+PWMS1)/108
000000 (64+PWMS1)/108
010000 (96+PWMS1)/108
011111 1

1)

VOH: PWM output High level, VOL: PWM output Low level

Amplitude of V-parabola

(ext. integration, PWMS0 = 1)

0.46 * (VOH -VOL)

0.58 * (VOH -VOL)

0.69 * (VOH -VOL)

0.81 * (VOH -VOL)

0.91 * (VOH -VOL)

1)

1)

1)

1)

1)

The PWM output may be used as swit ching output when PWMS0 = 0. If PWMC = 100000
and PWMS1 = 0 the output is Low. If PWMC = 011111 the output is continously High.

Micronas 5-20 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

The PLL control byte 0 includes the following bits:

0 0 X INCR4 INCR3 INCR2 INCR1 INCR0

-INCR4..0: Nominal PLL output frequency

INCR=INT((FH*55296)/FQ-64.625)
(for typical values see table below)
specified range:6

≤INCR≤21

(FQ=24.576MHz)

Application FH[Hz] INCR FH1_2

PAL (50Hz) 15625
NTSC (60Hz) 15750
PAL (60Hz) 18750
PAL (100Hz) 31250
NTSC (120Hz) 31500
ATV 32400
MUSE 33750
Macintosh

(640*480*67Hz)
SVGA

(800*600*60Hz)

35000

38000

Internal default value: INCR = 6 if FH1_2 = High

INCR = 6 if FH1_2 = Low, SSD = Low
INCR = 20 if FH1_2 = Low, SSD = High

Default value read by IIC bus: INCR = 0

6Low
6Low

20 Low

6High
6High
8High

11 High
14 High

21 High

The PLL control byte 1 includes the following bits:

000GENMODVCR

-GENMOD: Clock generator mode
0: normal PLL mode
1: generator mode (fixed frequency output, cont rolled by INCR..)

-VCR: PLL filter optimized for
0: TV mode
1: VCR mode

Micronas 5-21 2001-01-29

NOISY

VCR

HSWMI TC_3RD

SDA 9380 - B21 Preliminary Data Sheet

System description

- NOISYVCR:Handling of noisy input signals in VCR mode
0: normal handling
1: improved handling

Note: this bit is don’t care if bit VCR = 0 (TV mode)

- HSWMI: Minimum width of HSYNC
0: 1.5µs
1: 0.8µs

- TC_3RD: Third time constant
0: slow VCR time constant
1: fast VCR time constant

Note: this bit is don’t care if bit VCR = 0 (TV mode)

Warnings/Notes:

1) A change of INCR causes changes of the generated clock frequency more than the
specified 4.5%.
Switching from PLL mode to Generator mode (GENMOD) with constant INCR values does not
result in exceeding the specified frequency deviation range.

2) If pin SSD has H-level the output signal HD starts immediately after power on. In this case the
starting horizontal frequency is 31.25kHz (if FH1_2 = High). Starting with other frequencies requires
L-lev el at SSD so that INCR can be changed before enab ling HD with HDE=1.

3) When SSD = High and FH1_2 = Low the horizontal frequency is fixed to 18.75 kHz (INCR = 20)
and cannot be changed via I²C bus . Other H-f requencie s in the ra nge of 15.6 kHz t o 19 kHz are pos­sible when SSD = Low.

4) The timing of the built-in soft start circuit (starting frequency, period, ending frequency) depends
on INCR. The starting frequency of the output HD is approx. 1.71* FH, the frequency stops at FH
defined by INCR (se e ta bl e on previous page) The tot al sof t sta rt takes a bout 2.66* 10³/FH. If t he f re­quency of the HSYNC input signal is outside the lock range of the PLL (+/- 4.5%), that means the
PLL cannot lock, the timing of the soft start may change max. +/- 4.5% due to the unlocked PLL.

Micronas 5-22 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

The RGB control byte 0 includes the following bits:

IN2NOM IN1NOM CONTB BD VINP2E FBL2E VINP1E FBL1E

- IN2NOM:Nominal saturation and contrast for video input 2

0: variable saturation and contrast for video input 2 (defined by reg. 24, 25)
1: fixed saturation and contrast for video input 2 (nominal values)

- IN1NOM:Nominal saturation and contrast for video input 1

0: variable saturation and contrast for video input 1 (defined by reg. 24, 25)
1: fixed saturation and contrast for video input 1 (nominal values)

- CONTB: Continuous blanking

0: off
1: on

- BD: Blanking disable

0: horizontal and vertical blanking enabled
1: horizontal and vertical blanking disabled

- VINP2E, FBLE2, VINP1E, FBL1E: Selection of input signals (see table below)

VINP2E FBL2E VINP1E FBL1E selected input signals

0000 YUV/RGB 0

0001

001X RGB/YUV 1

0100

0101

011X

RGB/YUV 1 when FBL1=High else

YUV/RGB 0

RGB2 when FBL2=High else

YUV/RGB 0

RGB2 when FBL2=High

else RGB/YUV 1 when FBL1=High

else YUV/RGB 0

RGB2 when FBL2=High else

RGB/YUV 1

1XXX RGB 2

Micronas 5-23 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

The RGB control byte 1 includes the following bits:

BLUES SLBLKS BLCKS CTLPD WHITD CATH2 CATH1 CATH0

- BLUES: Blue stretch

0: off
1: on

- SLBLKS: Slow Black stretch

0: short time constant
1: long time constant

- BLCKS: Black stretch

0: off
1: on

- CTLPD: Control loop disable

0: cut off and white level control loop are active
1: cut off and white level control loop are inactive (halt mode)

- WHITD: White level control loop disable

0: white level control loop is active
1: white level control loop is inactive (halt mode)

- CATH2..

CATH0: Cathode drive level (see 5.5.5 Explanation of some control items)

100: minmum level
..

011: +100% (maximum level)

The RGB control byte 2 includes the following bits:

BLUEB FBL2L COR1 COR0 DELOFF SVMOFF DEL1 DEL0

- BLUEB: Blue background

0: off
1: on

- FBL2L: FBL2 input switching level

0: high s witching levels
1: low switching levels

Micronas 5-24 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

- COR1..0:Contrast reduction of the channel 0 and 1 at FBL2

00: 0 %
01: 25 %
10: 50 %
11: 75 %

- DELOFF:Delay from SVM output to RGB output

0: delay on (see below)
1: delay off (basic delay = 15ns)

- SVMOFF:SVM output

0: active (Y signal at SVM output)
1: off (SVM output is high)

- DEL1..0: Delay from SVM output to RGB output

00: delay = 25ns

.. ..

11: delay = 55ns

The Video input mode includes the following bits:

RGBEN1 MAT11 MAT10 0 RGBEN0 MAT01 MAT00 YLL

- RGBEN1:RGB/YUV 1 input

0: YUV input
1: RGB input

- MAT11..0:RGB/YUV 1 input, YUV input standard

00: PAL/SECAM
01: NTSC/Jap.
10: NTSC/US
11: HDTV

- RGBEN0:YUV/RGB 0 input

0: YUV input
1: RGB input

- MAT01..0:YUV/RGB 0 input, YUV input standard

00: PAL/SECAM
01: NTSC/Jap.
10: NTSC/US
11: HDTV

Micronas 5-25 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

- YLL: Y0 input low level for PAL and NTSC matrices

0: 1 V (black-to-white value)
1: 0.7 V (black-to-white value)

The Avera ge beam current limit c hara ct eri st ics includes the following bits:

GAIN2 GAIN1 GAIN0 TUP1 TUP0 TDOWN1 TDOWN0 MODE

- GAIN2..0: Gain adjustment

100: 0.25
101: 0.375
110: 0.5 (default value)
111: 0.625
000: 0.875
001: 1.125
010: 1.5
011: 2

- TUP1..0: Time constant of increasing contrast/brightness (current contrast is lower

than the adjusted contrast by I²C, ABLIM is not exceeded)
10: approximately 0.25 sec ond
11: approximately 0.5 second
00: approximately 1 second
01: approximately 2 second

- TDOWN1..0:Time constant of decreasing contrast/brightness when ABLIM is exceeded

10: approximately 30 ms
11: approximately 60 ms
00: approximately 120 ms
01: approximately 240 ms

- MODE: Updating of contrast/brightness

0: with field frequency
1: with line frequency

Micronas 5-26 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

The Peak drive limit register includes the following bits:

PDLIM3 PDLIM2 PDLIM1 PDLIM0 0 PDLT1 PDLT0 PDLD

- PDLIM3..0: Peak drive limit

1000: minimum level
...
0000: default level
...
0111: maximum level

- PDLT1..0: Peak drive limiter time constant

10: faster
11: fast
00: normal (default)
01: slow

- PDLD: Peak driv e limiter disable

0: peak drive limiter is enabled
1: peak drive limiter is disabled

The RGB control byte 3 register includes the f oll owing bits:

SW 0 0 RDCI SCLEV1 SCLEV0 SCSLP1 SCSLP0

- SW: Setting of output SWITCH

0: output SWITCH has L-level
1: output SWITCH has H-level

- RDCI: Input range of DCI

0: 0...2.7V
1: 1.8..2.7V

- SCLEV1..0: Soft clip level relati ve to peak drive limit

10: 100%
11: 105%
00: 110% (default)
01: infinite

- SCSLP1..0: Soft clipping slope

10: 0.125
11: 0.375
00: 0.625
01: 0.875

Micronas 5-27 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

The Status byte includes the following bits:

HPON VPON CON H38K H35K CLOW - PONRES

- HPON: H-protection on

0: normal operation of the line output stage
1: upper threshold on input HPROT has been exceeded *)

- VPON: V-protection on

0: normal operation of the vertical output stage
1: incorrect signal on input VPROT has been detected *)

- CON: Coincidence not

0: H-coincidence detected
1: no H-coincidence detected

- H38K: 38 kHz line frequency

0: 38 kHz line frequency not detected
1: 38 kHz line frequency detected

- H35K: 35 kHz line frequency

0: 35 kHz line frequency not detected
1: 35 kHz line frequency detected

- CLOW: Control loop out of window

0: all control loops inside of window
1: one of the control loop out of window

- PONRES: Power On Reset

0: after bus master has read the status byte
1: after each detected reset

*) Also output PROTON (pin 35) goes Hi gh if HPON=1 or VPON=1.

Note! PONRES is reset after this byte has been read.

Micronas 5-28 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

5.5.5 Explanation of some control items

Vertical aspect, Two special control items are implemented for the user to adjust the
Vertical scroll: vertical height (control item: Vertical aspect) and the vertical position

(Vertical scroll). These items may be st ored for every display mode to
get an individual height and position if desired. Changing these para­meters automatically influences the outputs VD+, VD-, E/W, HD in such
a way that absol utely no raster distortion happens. There is no need
for the user to re-adj ust any geometry parameter .

The difference of the function of Vertical size and Vertical aspect is
the following: Varying Vertical size causes a linear stretching of the
saw-tooth to eliminat e the tol erance of linear components (e.g. feed­back resistor). But adj usting Vertical aspect takes into consideration
that more or less picture height needs very more or less S-correction
(no linear relation). Therefore Vertical aspect should be used for chan g-
ing the aspect ratio (e.g. 16:9 source on 4:3 CRT) or if an individual
picture height is desired f or the various PC graphic standards. Vertical
aspect = -128(minimum value) results in a vertical reduction to 37.5%.

Vertical size, The purpose of these control parameters is the alignment in the fa ctory
Vertical shift: and service to adapt the output signals VD+, VD- to the picture tube and

to eliminate tolerances of t he hardware and deflection yoke. Only one
set of these parameters is requi red for all display modes.

Vertical linearity, Changing the vertical linearity and S-correction has no influence on the
Vertical S-correction: E/W-geometry. That means, straight vertical lines remain straight. The

output signals E/W and HD are automatically changed so no re-adjust­ment of the related control items is needed. This feature saves time for
adjustment of the so called ’smart’ mode (4:3 source on 16:9 CRT)

Guard band: This control item is useful for optimizi ng self adaptation. Video signals

with different number of lines in consecutive fields (e.g. VCR search
mode) must not start the procedure of self adaptation. But switching
between different TV standards has to change the slope of the v ertical
saw-tooth getting always the same amplitude (self adaptation). To avoid
problems with flicker free TV systems which have alternating number of
lines per field an average value of four consecutive fields is calcula ted. If
the deviation of these average values (e.g. PAL : 312.5 lines or 625 half
lines) is less or equals Guard band, no adaptation takes place. When it
exceeds Guard band, the vertical slope will be changed.

Vertical EHT comp.: This item controls the influence of the beam current dependent input

signal IBEAM on the outputs VD+ and VD- according to the following
equation:

∆V

∆V

∆V

VDPP

VDPP

VDPP

∆V

=

∆V

=

IBEAM

IBEAM

------------------------------------------------------------------------------------ -

Vertical_EHT_compensation + 128

------------------------------------------------------------------------------------ -

1536

512

: variation of VD+ and VD-peak-to-peak voltage

(if RIBM=0)

0.59⋅⋅

(if RIBM=1)

0.59⋅⋅

Vertical _EHT_compensation + 128

Micronas 5-29 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

∆V

IBEAM

: variation of IBEAM input voltage

If Vertical EHT compensation = -128 the outputs VD+ and VD- are
independent of the input signal IBEAM.

Horizontal EHT comp.:This item controls the infl uence of the input signal IBEAM on the output

E/W according to the following equation:

∆V
∆V

∆V

∆V

EW
IBEAM

Horizontal_EHT_compensation + 128

EW

EW

∆V

∆V

IBEAM

IBEAM

------------------------------------------------------------------------------------------- -

Horizontal_EHT_compensation + 128

------------------------------------------------------------------------------------------- -

: variation of E/W output voltage
: variation of IBEAM input voltage

384

128

2.14⋅⋅=

2.14⋅⋅=

(if RIBM=0)

(if RIBM=1)

If Horizontal EHT compensation = -128 the output E/W is independent
of the input signal IBEAM.

AFC EHT comp.: Deviation of the horizontal phase caused by high beam current (e.g.white

bar) can be eliminated by this control item. The beam current dependent
input signal IBEAM is multiplied by AFC EHT compensation. Additional to
the control items Vertical angle, Vertical bow and Horizontal shift, this pro­duct influences the horizontal phase at the output HD according to the
follo w ing equation:

∆φ ∆V

=

∆

φ ∆V

=

IBEAM

IBEAM

AFC_EHT_compensation

-------------------------------------------------------------------- -

⋅⋅

AFC_EHT_compensation

-------------------------------------------------------------------- -

⋅⋅

192

64

58

----------- -

CLL

58

----------- -

CLL

∆φ : variation of horizontal phase at the output HD

(positive val ues: shift left, negatives values: shi ft right)

∆V

IBEAM

CLL :864 · f

: variation of IBEAM input voltage (units: Volt)

H

(if RIBM=0)

(if RIBM=1)

Micronas 5-30 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

Vertical blanki ng start (VBS), RGB ref. pulse pos. (RPP), Vertical blanking end (VBE):

The control item RPP defines the position of the three reference pulses for
R, G, B:

Red ref. pulse = RPP + 16; (odd field) (def. value 20)
Green ref. pulse = RPP + 17; (odd field) (def. value 21)
Blue ref. pulse = RPP + 18; (odd filed) (def. value 22)

If bit BSE (Blanking Select Enable) = 0 the control item RPP is replaced b y its
default v alue (=4). So the R, G, B ref . pulses are generated i n line 20, 21, 22 i n
the odd field rsp. li ne 21, 22 , 23 in the ev en fie ld (see diagram below).

VBS defines the start as well of the internal vertical blanking pulse VBL as of
the output signal VBLO. The end of the internal signal VBL is defined by RPP
and VBE. This also applies to the end of VBLO wi th one exception. There i s at
least one line between the cutof f/white l e v el measur ement line f o r bl ue and the
end of VBLO. The vertical component of the SCP signal is always identical
with the internal vertical blanking pulse VBL.

Both VBL as well as VBLO are sy nchro niz ed wi th t he l eading ed ge of HSYNC.
It always starts and stops at the beginning of line and never in the center.
Therefore the end and width of VBL is one line more in the even field than in
the odd field.

If the vertical drive signals VD+, VD- are clipped in zoom mode (vertical
aspect > 0) at the top and bottom of the screen the vertical blanking pulse is
extended to bl ank all lines in this area without any additional programming.

a) Description of VBL when JMP= 0

Start of VBL = VBS lines before the first complete line of the next field

(def. value 0)

if BSE = 0

end of VBL = end of line (VBE + 22) (odd field)
width of VBL = (VBS + VBE + 22) lines (odd field)(def. value 22)

After power on the control bit BSE is 0, also VBS = 0 and VBE = 0. Therefore
22 lines (odd field) will be blanked before any programming of the IC.

if BSE = 1

end of VBL = end of line (RPP + VBE + 18) (odd field)
width of VBL = (VBS + RPP + VBE + 18) lines (odd field)

The number of lines between the last ref. pulse and the end of VBL is defined
by VBE in the range of 0 (VBE = 0) to 7 (VBE = 7).

If VBS = 0 (minimum value) VBL starts (point A in fig. below) 0...0.5 line (new
odd field) or 0.5...1 line (new even f iel d) prior to the vertical flyback.

Micronas 5-31 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

A

HSYNC

VSYNC

1 line

151 2 16 17 18 19 20 21 22 23 24 25

VD-

VBL
(default:
BSE=0,
VBS=0,
VBE=0)

VBL
(BSE=0,
VBS=2,
VBE=0)

VBL
(BSE=1,
RPP=1,
VBS=0,
VBE =1)

start of even field

start of odd field

R G B

2lines

22 lines

R G B

R G B

24 lines

R G B

R G B

20 lines

R G B

odd field

even field

odd field

even field

odd field

even field

Interna l vertical blanking pulse VBL when JMP = 0 and number of lines per field = constant

b) Description of VBL when JMP= 1

Start of VBL = VBS lines before the first complete line of the next field

(def. value 0)

if BSE = 0

end of VBL = end of line (VBE + 29) (odd field)
width of VBL = (VBS + VBE + 29) lines (odd field)(def. value 29)

if BSE = 1

end of VBL = end of line (RPP + VBE + 25) (odd field)
width of VBL = (VBS + RPP + VBE + 25) lines (odd field)

Note! If JMP = 1 the number of lines between the last ref. pulse and the end of
VBL is defined by VBE in the range of 7 (VBE = 0) to 14 (VBE = 7).

Micronas 5-32 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

A

HSYNC

VSYNC

201 2 21 22 23 24 25 26 27 28 29 30

1 line

31 32

VD-

VBL
(default:
BSE=0,
VBS=0)

VBL
(BSE=0,
VBS=2)

VBL
(BSE=0,
VBS=0,
VBE=1)

start of even field

start of
odd field

R G B

2 lines

29 lines

R G B

R G B

31 lines

R G B

R G B

30 lines

R G B

odd field

even field

odd field

even field

odd field

even field

Internal vertical blanking pulse VBL when JMP = 1 and number of lines per field = constant

Micronas 5-33 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

Min. No. of li ne s / field:

It defines the minimum number of lines per field for the vertical synchroniza­tion. If the TV standard at the inputs VSYNC and HSYNC has less lines per
field than defined by Min. No. of lines / field no synchronization is possible.
The relationship between Min. No. of lines / field and the minimum number
of lines is given in the following table:

Max. No. of lines / field:

It defines the maximum number of lines per field for the vertical synchroniza­tion. If the TV standard at the inputs VSYNC and HSYNC has more lines per
field than defined by Max. No. of lines / field no synchronization is possible.
The relationship between Max. No. of lines / field and the maximum number
of lines is given in the following table:

Min. No. of lines /

field

0
1

...
127
128

...
254
255

Max. No. of lines /

field

minimum number

of lines per field

192
194

...
446
448

...
700
702

maxim um number
of lines per field

0
1
2

...
127
128

...
255

Average beam current limit:

Brightness and contrast is reduced when the average beam current limit level
is exceeded. The beam curre nt is measured at pin IBEAM. High v oltage at this
input indicates low beam current, low voltage high beam current. The limit
range of -128 to 127 c ompli es to a voltage at IBEAM of 2.5 t o 0. 84V at RIBM =
0 and 2.63 to 2.08V at RIBM = 1.

Micronas 5-34 2001-01-29

702
192
194

...
444
446

...
700

SDA 9380 - B21 Preliminary Data Sheet

System description

Peak dark detection (PDD) top border, bottom border, left border, right border:

These four contr ol items de fi ne the p ictur e ar ea insi des the peak dark dete ctor
is enabled. The peak dark detector is storing the lowest level of the luminance
signal. If this value is higher than the clamping level the luminance signal is
stretched towards clamping level (Black stretch function). Those parts of the
picture with a luminance signal less than 50% of nominal amplitude are get­ting more dark.

It is possible with these four control items to screen black borders of the pic­ture (e.g. letter box format) which otherwise prevent the desired function of
black stretch.

The follow ing figure and table show thei r definitions:

line=0

line

PDD top

border [7:0]

peak dark detection for

black stretch enabled

PDD bottom

border [7:0]

last line of

field

pixel=0 pixel=863

PDD left

border [3:0]

pixel

PDD

top border

vertical and horizontal blanking

PDD

bottom border

PDD

left border

PDD right

border [3:0]

PDD

right border

Width 8 bit (0...255) 8 bit (0...255) 4 bit (0...15) 4 bit (0...15)

Resolution 2 lines/bit 4 lines/bit 16 pixels/bit 1 6 pixels/bit

Range line 0...510 line 0...1020 pixel 64...304 pixel 576...816

Default value 16 (line 32) 71 (line 284) 8 (pixel 192) 8 (pixel 704)

Micronas 5-35 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

System description

White control R, white control G, white control B, CATH[2:0]:

These four control items define the nominal values of the cut-off and white­drive currents during the measurement lines. They can be calculated with the
following equations:

I

I

I

= 0.00325 * (White control x + 64) / R

cut-off

= 0.00108 * (White control x + 64) / R

cut-off

white-drive

= I

* (CATH[2:0] + 18) / 8

cut-off

DCI

DCI

(if RDCI=0)

(if RDCI=1)

White control x: White control register for R, G or B (range -32...+31)
R

: Resulting resistor to ground at DCI input

DCI

CATH[2:0]: Cathode drive level (range -4...+3) in register RGB control 1

Micronas 5-36 2001-01-29

Micronas 5-37 2001-01-29

Most important V-Deflection modes for 4:3 CRT

SDA 9380 - B21 Preliminary Data Sheet

Mode Description Characteristics Notes

normal mode

N0

(for 4:3 source, Letterbox)
with default settings

normal mode
(for 4:3 source, Letterbox)

N1

with user defined settings

VGA or SVGA mode
with user defined V-posi-

VGA

tion/V-size

shrink mode 75%
(for 16:9 source)

S0

with default settings

shrink mode 75%
(for 16:9 source)
with user defined settings

S1

RGB ref. pulse position = line 20... 22 (odd field)
end of V-blanking = line 22 (odd field)
guard band = 1.5 lines

RGB ref. pulse position = line (RPP + 16)
...(RPP + 18) (odd field)
end of V-blanking = line (RPP + 18) (odd field)
guard band = Guard band/2 [lines]

RGB ref. pulse position = line 20... 22 (odd field)
end of V-blanking = line 22 (odd field)
guard band = 1.5 lines

RGB ref. pulse position = line 20... 22 (odd field)
end of V-blanking = line 22 (odd field)
guard band = 1.5 lines

RGB ref. pulse position = line (RPP + 16)
...(RPP + 18) (odd field)
end of V-blanking = line (RPP + VBE + 25) (odd)
start of reduced V-ramp = line (RPP + 19) (odd)
guard band = Guard band/2 [lines]

mode after power on

RGB reference pulse position
adjustable,
guard band adjustable

Vertical scroll/Vertical aspect
for user defined V-position/V­size,
WHITD disables RGB white
level ref. pulses

Vertical aspect = -50
causes V-reduction to 75%,
JMP = 0 causes V-shrink incl.
flyback

RGB ref. pulse positon adjust.,
JMP = 1 causes V-shrink excl.
flyback,
WHITD disables RGB white
level ref. pulses
guard band adjustable

Vertical

scroll

variable variable 0 0 1 0

Vertical

aspect

0 00000

0 01100

0-500000

0-501111

BSE GBE WHITD JMP

System description

Micronas 5-38 2001-01-29

Most important V-Deflection modes for 16:9 CRT

SDA 9380 - B21 Preliminary Data Sheet

Mode Description Characteristics Notes

normal mode

N0

(for 16:9 or 4:3 source)
with default settings

normal mode
(for 16:9 or 4:3 source)

N1

with user defined settings

zoom mode
(for 4:3 source, Letterbox)

Z

scroll mode
(for 4:3 source, Letterbox

SC

with subtitles)

shrink mode 66%
(for two 4:3 sources)

S2

with default settings

shrink mode 66%
(for two 4:3 sources)
with user defined settings

S3

shrink mode 50%
(for two 16:9 sources)

S4

with default settings

RGB ref. pulse position = line 20... 22 (odd field)
end of V-blanking = line 22 (odd field)
guard band = 1.5 lines

RGB ref. pulse position = line (RPP + 16)
...(RPP + 18) (odd field)
end of V-blanking = line (RPP + 18) (odd field)
guard band = Guard band/2 [lines]

RGB ref. pulse position = line 20... 22 (odd field)
end of V-blanking = line 22 (odd field)
zoom factor ca. Vertical aspect/2 [%]
guard band = 1.5 lines

RGB ref. pulse position = line 20... 22 (odd field)
end of V-blanking = line 22 (odd field)
zoom factor ca. Vertical aspect/2 [%]
guard band = 1.5 lines

RGB ref. pulse position = line 20... 22 (odd field)
end of V-blanking = line 22 (odd field)
guard band =1.5 lines

RGB ref. pulse position = line (RPP + 16)
...(RPP + 18) (odd field)
end of V-blanking = line (RPP + VBE + 25) (odd)
start of reduced V-ramp = line (RPP + 19) (odd)
guard band = Guard band/2 [lines]

RGB ref. pulse position = line 20... 22 (odd field)
end of V-blanking = line 22 (odd field)
guard band = 1.5 lines

mode after power on

RGB reference pulse position
adjustable,
guard band adjustable

Vertical aspect controls
zoom factor,
clipping of VD+, VD-, E/W
when NCLP = 0

as above,
Vertical scroll can be additio­nally used for adjustment of
vertical position

Vertical aspect = -68
causes V-reduction to 66%,
JMP = 0 causes V-shrink incl.
flyback

RGB ref. pulse positon adjust.,
JMP = 1 causes V-shrink excl.
flyback,
WHITD disables RGB white
level ref. pulses
guard band adjustable

vertical aspect = -102
causes V-reduction to 50%,
JMP = 0 causes V-shrink incl.
flyback

Vertical

scroll

variable> 00000

Vertical

aspect

0 00000

0 01100

0 > 00000

0-680000

0-681111

0 -102 0 0 0 0

BSE GBE WHITD JMP

System description

SDA 9380 - B21 Preliminary Data Sheet

Pin schematic

6 Pin schematic

pin schematic remark

ROUT,
GOUT,
BOUT

PAD

bipolar
output stage,
supply
voltage:
V

ESD

protection

DD(MC)

SCP bipolar

PAD

output stage,
supply
voltage:

ESD

protection

V

DD(MC)

HD open drain

PAD

ESD protection

output

Micronas 6-39 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Pin schematic

pin schematic remark

X1, X2 crystal

ESD protection

PAD X2

PAD X1

oscillator
(X1: input,
X2: output)

SVM analog

CLKI,
CLEXT,
TEST,

ESD protection

PAD

ESD protection

PAD

output

digital input/
output

RESN, SCL,
SDA, H35K,
H38K, PW M,
VSYNC,
FH1_2,
HSYNC,
PHI2,
PROTON,
VBLO, FBL1,
FBL2,
SWITCH

Micronas 6-40 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Pin schematic

pin schematic remark

E/W, D/A,
VD+, VD-,
VPROT,
HPROT,
HSAFE,
BSOIN,
IBEAM,
VREFH,
VREFN,
VREFC, DCI,
Y/R0, U/G0,
V/B0, Y/R1,
U/G1, V/B1,
R2, G2, B2

PAD

ESD protection

ESD prot ection

analog input/
output

Micronas 6-41 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Absolute maximum ratings

7 Absolute maximum ratings

Parameter Symbol Min Max Unit Remark

Operating temperature T

A

070°C
Storage temperature -40 125 °C
Junction temperature 125 °C
Soldering temperature 260 °C
Input voltage V

Input voltage V
Output voltage V
Supply voltages V

Supply voltage V

DD(D)

V

DD(A1..4)

DD(MC)

Supply total voltage

-0.3V VDD+0.3V not valid for SD A, SCL,

SS

-0.3V 5.5V SDA, SCL, CLKI, HD

SS

-0.3V VDD+0.3V

SS

-0.3 3.8 V

-0.3 9 V

-0.25 0.25 V between V

difference
VSS, SUBS T total v oltag e

-0.25 0.25 V between SUBST,

difference

Total power dissip ation 1.28 W

CLKI, HD

V

DD(A1..4)

V

SS(MC), VSS(D),

V

SS(A1..4)

DD(D),

Latch-up protection -100 100 mA all inputs/outputs

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Func­tional operation under these conditions or at any other condition beyond those indicate d in the oper­ational sections of this specificat ion is not implied.

Micronas 7-42 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Recommended operating conditions

8 Recommended operating conditions

Parameter Symbol Min Nom Max Unit Remark

Supply voltages V

Supply voltage V
Ambient temperature T

1

) Any sequence and any rise time of the 3.3V and 8V supply voltage is allowed at power on. But all VSS

DD(D)

V

DD(A1..4)

DD(MC)

A

3.0 3.3 3.45 V

7.2 8.0 8.4 V
02570°C

1

)

1

)

pins as well as SUBST pin have to be connected to ground when applying any voltage.

TTL Inputs: VSYNC, RESN, TEST, FH1_2, CLEXT, SSD

High-level input voltage V
Low-level input voltage V

IH

IL

2.0V V

DD

V

00.8V

TTL Inputs: CLKI (CLEXT=High)

High-level input voltage V
Low-level input voltage V

IH

IL

2.0V 5.5 V

00.8V

Input VPROT

Threshold V1 1.4 1.5 1.6 V
Threshold V2 0.9 1.0 1.1 V

Input HPROT

Threshold V1 2.65 2.7 2.75 V
Threshold V2 1.4 1.5 1.6 V

Input BSOIN

Upper threshold (negative-going) V
Upper threshold (positive-going) V

THn

THp

Lower threshold 0.5 0.7 V

2.625 2.675*) 2.725 V see 11.2

2.725 2.775*) 2.825 V

*) The comparator has a hysteresis of typ. 100mV.

Input HSAFE

Low input voltage 1.8 V
Full range input voltage 2.7 V
Input voltage at 31.25 kHz V
Input voltage at 38 kHz V

31.25k

38k

1.9 2.0 2.1 V

1.225 1.24 1.26 V

31.25k

related to V

31.25k

!

Micronas 8-43 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Recommended operating conditions

Parameter Symbol Min Nom Max Unit Remark

Input voltage when watching of

01.5V

HSAFE is disabled

Input IBEAM

Low input voltage 0 V control bit RIBM=0

1.8 V control bit RIBM=1

Full range input voltage 2.7 V RIBM=0

2.7 V RIBM=1

Reference Voltage Pins

VREFH voltage 1.568 1.6 1.632 V tolerance +- 2%
VREFN voltage 0 V
VREFC resistor to VREFN 27 k

Ω tolerance +- 2%

Input Φ2

Low-level input voltage V
High-level input voltage

IL

V

IH

00.7V

2.0V V

DD

Input HSYNC (CLEXT=Low)

Input voltage range V
Input voltage Low level V
Input voltage High level V
Pulse width (HSWMI=0)

Pulse width (HSWMI=1)

HSpp

HSmin

HSmax

t

w

t

w

*) High or Low level allowed, INCR = 6, see 5.2

Input HSYNC (CLEXT=High)

Low-level input voltage V
High-level input voltage V
Setup time t

Hold time

t

IL

IH

SU

H

2V V

DD

see 5.2

0V see 5.2

V

DD

see 5.2

1.5 4.5 µs *), FH1_2 = High

3.0 9.0 µs *), FH1_2 = Low

0.8 4.5 µs *), FH1_2 = High

1.7 9.0 µs *), FH1_2 = Low

00.8V

2.0V V

DD

7 ns referred to rising

edge of CLKI

6 ns referred to rising

edge of CLKI

Micronas 8-44 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Recommended operating conditions

Parameter Symbol Min Nom Max Unit Remark
Input VSYNC

Pulse width high 100 ns 100/fH FH1_2=1, NI=0
Pulse width high 200 ns 100/fH FH1_2=0, NI=0
Pulse width high 1.5/fH 100/fH NI=1

Input CLKI (external clock mode, CLEXT=high)

Input frequency 25 27 30 MHz

Quartz Oscillator Input / Output X1, X2

Crystal frequency 24.576 MHz fundamental

crystal type, e.g.
Saronix
9922 520 00282

Crystal reso nant imped anc e 40
External capacitance 15 pF see 10

Ω

YUV Inputs

Y input voltage (black-to-white value) V

U input voltage (peak-to-peak value) V

V input voltage (peak-to-peak value) V

DC input current between clamping I
Input capacitance C
Maximum input current during

clamping
Internal bias during clamping at Y-

input
Internal bias during clamping at UV-

inputs

P-P

P-P

P-P

i

i

I

i-clamp

V

clampY

V

clampUV

100 µA

1

0.7

1.33

0.7

1.05

0.7

0.6 V

1.1 V

1.5

1.05

2

1.05

1.6

1.05
100 nA
7pF

V
V only Y0 input at

YLL = 1, or at
HDTV matrix

V
V

V
V

U = - (B - Y),
at HDTV matrix

V = - (R - Y),
at HDTV matrix

RGB Inputs (RGB2, RGB/YUV1 if RGBEN1=1, YUV/RGB0 if RGBEN0=1)

Input voltage (black-to-white value) V
DC input current between clamping I
Input capacitance C

P-P

i

i

Micronas 8-45 2001-01-29

0.7 1 V
100 nA
7pF

SDA 9380 - B21 Preliminary Data Sheet

Recommended operating conditions

Parameter Symbol Min Nom Max Unit Remark

Maximum input current during

I

i-clamp

100 µA

clamping
Internal bias during clamping V
Difference between black level of

clamp

∆V

o

0.6 V

internal and external signals at the
outputs

Delay difference of the three

∆t

d

0ns1)

channels

Fast Blanking Input FBL1 (RGB/YUV 1)

Input voltage no data insertion V
Input voltage data insertion V
Maximum input voltage V
Difference between transit times for

signal switching and signal insertion
Suppression of internal video signals

(insertion) or external video signals
(no insertion)

i-n
i-y
i-max

t

s

- t

0.9 V

i

55 dB f

Fast Blanking/Contrast Reduction Input FBL2 (RGB2)

50 mV

0.5 V

3.3 V
10 ns 1)

= 0 to 10 MHz, 1)

i

Maximum input voltage V
Difference between transit times for

i-max

t

s

- t

i

3.3 V
10 ns 1)

signal switching and signal insertion
Suppression of internal video signals

55 dB f

= 0 to 10 MHz, 1)

i

(insertion) or external video signals
(no insertion)

Fast Blanking (Control bit COR1..COR0 = 00)

Input voltage no data insertion V
Input voltage data insertion V

i-n
i-y

0.9 V

0.5 V

Fast Blanking and Contrast Reduction (Control bit COR1..COR0 = 01...11)

Input voltage no contrast reduction
of internal RGB signals

Input voltage contrast reduction of
internal RGB signals

Contrast reduction (control bit
COR1..COR0)

Input voltage no data insertion V

V

V

icr-n

icr-y

i-n

1.4

0.5

1.7

0.9

V FBL2L = 0

FBL2L = 1

V FBL2L = 0

FBL2L = 1

075%

2

1.2

V FBL2L = 0

FBL2L = 1

Micronas 8-46 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Recommended operating conditions

Parameter Symbol Min Nom Max Unit Remark

Input voltage data insertion V

i-y

2.5

1.8

V FBL2L = 0

FBL2L = 1

Dark current input DCI for cut off and white level control

Low input voltage 0 V control bit RDCI=0

1.8 V control bit RDCI=1

Full range input voltage 2.7 V
Maximum input current I

i-DCImax

10 mA V

i-DCI

> V

dd

Input RGB matrices
PAL/SECAM mode

RGB matrix coefficients:
R = Y - V
G = Y + P

U + PvV

u

B = Y - U

P

u

P

v

0.19

0.51

U = - (B - Y)
V = - (R - Y)

NTSC/Jap mode

RGB matrix coefficients:
R = Y + J
G = Y + J
B = Y + J

U + JvrV

ur

U + JvgV

ug

U

ub

J

ur

J

vr

J

ug

J

vg

J

ub

0.068

−=1.38

0.15

0.46

−=1

U = - (B - Y)
V = - (R - Y)

NTSC/US mode

RGB matrix coefficients:
R = Y + A
G = Y + A
B = Y + A

U + AvrV

ur

U + AvgV

ug

U + AvbV

ub

A

ur

A

vr

A

ug

A

vg

A

ub

A

vb

0.12

−=1.32

0.25

0.42

−=1.08

0.035

HDTV mode (according to SMPTE Standard 274M and EIA-770.3-A)

RGB matrix coefficients:
R = Y + H
G = Y + H
B = Y + H

V

vr

U + HvgV

ug

U

ub

H

vr

H

ug

H

vg

H

ub

1.575

−=0.187

−=0.468

1.856

Internal RGB matrices

See PAL/SECAM mode

Internal colour difference matrices

See PAL/SECAM mode

U = - (B - Y)
V = - (R - Y)

U = P’B =
= 0.539 (B - Y)

R

=

V = P’
= 0.635 (R - Y)

Micronas 8-47 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Recommended operating conditions

Parameter Symbol Min Nom Max Unit Remark
Saturation control (control bit B0...B5; subaddress 25h)

Saturation control range 52 dB 63 steps
Nominal saturation

B7...B2 = 110001 0 dB

Contrast control (control bit B7...B0; subaddress 24h)

Contrast control range 20 dB 255 steps
Nominal contrast

B7...B0 = 00000000 0 dB
T r acking between the three channels

over a control range of 10 dB

0.5 dB

Brightness control (control bit B7...B0; subaddress 23h)

Brightness control range +- 0.75 V 255 steps

Black level stretch (control bit BLCKS; subaddress 20h)

Maximum black level shift 15 21 27 IRE
Level shift at 100% peak white -1 0 1 IRE
Level shift at 50% peak white -1 3 IRE
Level shift at 15% peak white 8 11 14 IRE

Peak drive limit (control byte peak drive limit, bits B7...B0; bit PDD)
Peak detector

Peak detector level (at t he R, G or B
output at nominal white drive relative
to cut off)
IIC bus: peak drive limit B7...B4
minimum value (range -8)
maximum value (range +7)

1.5

3.5

V
V

Soft clipper

Starting level (relative to peak detek­tors level)
IIC bus: peak drive limit B3, B2
10
11
00
01 (soft clipper off)

Micronas 8-48 2001-01-29

100
105
110
infinite

%
%
%

SDA 9380 - B21 Preliminary Data Sheet

Recommended operating conditions

Parameter Symbol Min Nom Max Unit Remark

Slope
IIC bus: peak drive limit B1,B0
10
11
00
01

0.125

0.375

0.625

0.875

Blue stretch (control bit BLUES; subaddress 20h)

Decrease of small signal gain for red
and green at nominal input amplitu­des and nominal settings of contrast
and brightness

Percentage of nominal input voltage
at which decrease of gain begins
(nominal settings of contrast and
brightness)

I²C Bus (all values are referred to min(V

SCL clock frequency f
High-level input voltage V

Low-level input voltage V
Load capacitance C
Rise times of SCL, SDA t

Fall times of SCL, SDA t

SCL

IH

IL

b

R

F

17 %

80 %

) and max(VIL))

IH

0 400 kHz

0.75*
V

DD(D)

5.25 V

01.5V
400 pF

20+0.1*

/pF*)

C

b

20+0.1*

/pF*)

C

b

300*) ns

300 ns

Set-up time DATA t
Hold time DATA t
Spike duration at inputs C
*) Fast-mode (f

= 400 kHz)

SCL

SU;DAT

HD;DAT

b

100 ns
0ns

050ns

Micronas 8-49 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Characteristics (assuming recommended operating conditions)

9 Characteristics (assuming recommended operating conditions)

Parameter Symbol Min Nom Max Unit Remark

Average supply current of
V

DD(D) +VDD(A1..4)

Average supply current of V

DD(MC)

245 290 mA DEL1...0 = 11

32 40 mA
Total power dissipation 1.28 W
Standby supply current of

V

DD(D) +VDD(A1..4)

15 25 mA no standby mode

TTL Inputs CLKI, VSYNC, RESN, TEST, FH1_2, CLEXT, SSD

Input leakage current |I

| 10 µA

leak

Input X1

Input leakage current |I

| 50 µA

leak

Input HSYNC

Input leakage current |I

| 100 µA

leak

Analog Inputs HPROT, VPROT, HSAFE, BSOIN, IBEAM, FBL1, FBL2

Input leakage current |I

| 10 µA

leak

Analog Inputs Y/R0, U/G0, V/B0, R/Y1, G/U1, B/V1, R2, G2, B2, DCI

(maximum delay)

for V

DD(MC)

Input leakage current |I

I²C Input/Output SDA

SDA output Low level V

I²C Inputs SDA/SCL

Hysteresis of Schmitt trigger inputs V
Input leakage current |I

Output Pins SWITCH, VBLO

Output Low level V
Output High level V

Output PROTON

Output Low level
(if HPON=0 and VPON=0 )

Output High level
(if HPON=1 or VPON=1)

| 100 nA

leak

OL

hys

| 10 µA

leak

OL

OH

V

OL

V

OH

0.2 V 1)

2.4 V IO = -1 mA

2.4 V IO = -1 mA

0.6 V IO = 6 mA

0.4 V IO = 1 mA

0.4 V IO = 1 mA

Micronas 9-50 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Characteristics (assuming recommended operating conditions)

Parameter Symbol Min Nom Max Unit Remark
Output PWM

Output Low level V
Output High level
Period
Resolution t

OL

V

OH

T

PWM

R

2.4 V IO = -1 mA
T

H

TH/108 PWMS0=0

0.4 V IO = 1 mA

TH/864 PWMS0=1

Output SCP

Output Low level V
Output BLanking level

Output High level

OL

V

OHBL

V

OH

01VI
V

DD(MC)

/2

-0.6V

V

DD(MC)

V

DD(MC)

/2

V

DD(MC)

/2
+0.3V

V

DD(MC)

-1.3V

DAC Output D/A

DAC Resolution 8 bit
DAC Output LOW 0.20 V

TH = hor. period

(subaddress 1A)

= 1 mA

O

| I

| = 100 µA

O

IO = -1 mA

DAC Output HIGH 2.98 V
Load Capacitance 30 pF
Output Load 20 kOhm
Offset Error -3% 3%
Gain Error -3% 3%
INL -2 2 LSB
DNL -1 1 LSB

DAC Output E/W

DAC resolution 10 bit linear range:

100...900

DAC output LOW 0.64 V input data = 100
DAC output HIGH 2.48 V input data = 900
Load capacitance 30 pF
Output load 20 kOhm
Zero error -2% 2% DAC output

voltage = 1.6V,*)

Micronas 9-51 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Characteristics (assuming recommended operating conditions)

Parameter Symbol Min Nom Max Unit Remark

Gain error -5% 5% *)
INL -0.2% 0.2% *)
DNL -0.1% 0.1% *)
*) input range = 100...900

DAC Output VD+, VD-

DAC resolution 14 bit linear range:

1500...15000

DAC output LOW (VD-) 0.62 V input data = 1500
DAC output HIGH (VD-) 2.6 V input data = 15000
DAC output LOW (VD-) - (VD+) -1.90 V input data = 1500
DAC output HIGH (VD-) - (VD+) 1,96 V input data = 15000
Load capacitance 30 pF
Output load 20 kOhm
Zero error -1% 1% (VD-)-(VD+)=0V, *)
Gain error -5% 5% *)
INL -0.5% 0.5% *)
DNL monotonous guaranteed by

design

*) input range = 1500...15000

Reference Output VREFH

Output voltage 1.568 1.6 1.632 V tolerance +-2%

Open Drain Output HD

Output Low level V
Maximum Voltage V

OL

OH

01VI

= 8 mA

O

5.5 V

Output H35K

Output Low level V

OL

0.4 V IO = 1 mA
Output High level
Positive-going threshold of

f

Negative-going threshold of f
Hysteresis

HSYNCfTH1

HSYNCfTH2

V

f

TH1

OH

- f

2.4 V IO = -1 mA

33.9 kHz see 11.1

33.3 kHz see 11.1

TH2

0.6 kHz

Micronas 9-52 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Characteristics (assuming recommended operating conditions)

Parameter Symbol Min Nom Max Unit Remark

Delay from positive-going threshold
of

f

HSYNC

to output

Delay from negative-going threshold
of

f

HSYNC

to output

Output H38K

Output Low level V
Output High level V
Positive-going threshold of
Negative-going threshold of

f

HSYNCfTH3

f

HSYNCfTH4

Hysteresis
Delay from positive-going threshold

of

f

HSYNC

to output

Delay from negative-going threshold
of

f

HSYNC

to output

RGB Output

Differential output resistance R

t

D1

t

D2

f

TH3

t

D3

t

D4

OL

OH

o

- f

100 ns see 11.1

0.4 V IO = 1 mA

2.4 V IO = -1 mA

36.9 kHz see 11.1

36.4 kHz see 11.1

TH4

0.5 kHz

100 ns see 11.1

25 30 Ω

(14 - int(27/12 *

[kHz] -64)) * T

f

H0

(21 - int(27/12 *

[kHz] -64)) * T

f

H0

V

V

Maximum output current I
Minimum output voltage V
Maximum output voltage V

o

o-min
o-max

45 mA

0.8 V

V

DD(MC)

7V

-1.3

Output signal amplitude (peak-to­peak value)

V

o(p-p)

2.1 V at nominal lumi­nance input signal,
nominal contrast
and white-point
control

Maximum output signal amplitude

V

o(p-p)max

3.3 V

(peak-to-peak value)
Nominal black level voltage 2.5 V at nominal bright-

ness = +30

Control range of the black current

+-1 V

stabilisation
Blanking level

Leakage measurement level
Cut off measurement level
White point measurement level

-0.4

-0.05

0.25

0.36

V
V
V
V

difference with
nominal black level
at nominal con­trast and white
point

Micronas 9-53 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Characteristics (assuming recommended operating conditions)

Parameter Symbol Min Nom Max Unit Remark

Variation of black level with
temperature

1)

Gain range of white point control
loop

Relative variation in black level bet­ween all inputs during variation of:
Supply voltage (+-10%)
Saturation (50 dB)

Contrast (20 dB)

1)

Brightness (+-0.5V)
Temperature (range 40 °C)

Signal-to-noise ratio of the output

1)

signal
Bandwidth of the output signals for

1)

1)

1)

1)

S/N 60 dB V

B
all inputs:
Delay off (DELOFF = 1):

30
Maximum delay (DELOFF = 0,
DEL1 = 1, DEL0 = 1):

20

Scan velocity modulation output SVM (Y output)

1mV/K

+-6 dB

20
20

mV
mV

nominal controls
nom. contrast and
white point

20

mV

nom. saturation

and white point
20
20

mV
mV

nominal controls

nominal controls

/RMS

0(p-p)

noise

bandwidth 10 MHz

at -3 dB

MHz
MHz

Output signal amplitude (peak-to-

V

SVM(p-p)

1.9 V SVMOFF = 0

peak value)
Maximum output current I
Output signal at black level
Differential output resistance R
Bandwidth of the output signal for all

o-svm

V

SVM-black

o-svm

B

SVM

45 mA

0.6 V
25 30 Ω

30 MHz at -3 dB

inputs
Total delay from SVM output to RGB

D

svm0

outputs
DEL 1, DEL0:
00
01
10
11

Total delay from SVM output to RGB

D

svm1

25
35
45
55

15 ns DELOFF = 1

outputs

1)

not tested during production but characterization in pre-production

DELOFF = 0

ns
ns
ns
ns

(basic delay)

Micronas 9-54 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Application information

10 Application information

10.1 System overview Dig. TV 100Hz

CVBS1

Y

U

CVBS7

RGB1

RGB2

SDA

9402

PRIMUS

V

H, V

CLK

10.2 System overview Multisync Deflection

SCP

HPROT

VPROT

HSAFE

B+

Control

SDA 9380

RGB

Processor,

Deflection
Controller

B+

R
G

B

H-Drive
V-Drive

E/W

IBEAM

BSOIN
H35K

H38K

15pF

24,576
MHz

15pF

VSYNC
HSYNC

X1

X2

SDA
9380

HD

E/W

VD­VD+

IBEAM

VPROT

Micronas 10-55 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Application information

10.3 Application circuit diagram

VSYNC
HSYNC

YUV

In

RGBFB1

In

RGBFB2

In

27k

75 75 75

75 75 75 75

75 75 75 75

+3.3 V

100n

100n

27k

22n
22n
22n

22n
22n
22n

+3.3 V

+3.3 V

100n

32 3031 29 2728 26 2425 23 2122 20 19 1718

VD-

33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48

HSAFE

VPROT

BSOIN
IBEAM
PROTON
VREFH
VBLO
VREFN
VREFC
DCI
VDD(A4)
Y/R 0
U/G 0
V/B 0
VSS(A4)
R/Y 1
G/U 1
B/V 1

HPROT

FBL2

FBL1

R2G2B2

50 52 5453 55 5756 58 6059 61 62 6463

49 51

22n

22n

VD+

VSS(A3)

VDD(A3)

SDA 9380

VDD(MC)

ROUT

22n

+8 V

100n

D/A

E/W

VSS(A2)

VDD(A2)

GOUT

BOUT

SCP

VSS(MC)

Φ=2

SVM

100n100n

+3.3 V

+3.3 V

+5 V

FH1_2

HSYNC

VSS(A1)

VDD(A1)

VSS(D)

VDD(D)

SSD

VSYNC

PWM
H38K
H35K

HD
VSS(D)
VDD(D)

SDA

SCL

RESN

SUBST

TEST

CLEXT

CLKI

SWITCH

16
15
14
13
12
11

100n

10

9
8
7
6
5
4
3

X1

2

X2

1

+3.3 V

+3.3 V

+3.3 V

24.576 MHz

15p
15p

+3.3 V

+3.3 V

100n

IBeam
UB Sense
B+ Sense

V-Sawtooth

-V-Drive
+V-Drive
E/W-Parabola
H-Flyback

B+ Control_1
B+ Control_0
H-Drive

SVM-Out
RGB-Out
Sense

CLK

IIC bus

Micronas 10-56 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Waveforms

11 Waveforms

11.1 Timing diagram of H35K and H38K

f at

H

HSYNC

f at HD

H

H35K

31 kHz

31 kHz

f

TH1

35 kHz 35 kHz

t

D1

*) *) *) *)

H38K

11.2 Black Switch-Off diagrams

BSOIN

ca. 20% V

TH

f

TH3

38 kHz

f

TH4

38 kHz

35 kHz 35 kHz

**) **)

t

D3

*) new H-freque ncy detected
**) depends on decrease of B+

V

TH

f

TH2

31 kHz

31 kHz

VBL com­ponent of
SCP

t

D1

overscan depends on selected BSO mode (s. next page)

VD+

BSOIN controls VD+, VD- in mode 2, 3

t

D2

ROUT,
BOUT,
GOUT

HD

continuously HD pulses until Power-On-Reset is going High

tD1: 2...2.5 lines tD2: 42 lines

Micronas 11-57 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Waveforms

Mode 1 (constant overscan, BSO = 01):

160
152
144
136
128
120
112

V-overscan in %

104

96
88
80

0 10 20 30 40 50 60 70 80 90 100

V-overscan = f (voltage at BSOIN)

voltage BSOIN in %

Mode 2 (parabolic function, BSO = 10):

140
132
124
116
108
100

92

V-overscan in %

84
76
68
60

0 10 20 30 40 50 60 70 80 90 100

V-overscan = f (voltage at BSOIN)

voltage BSOIN in %

V-overscan in %:

f 100( ) 115



f75( ) 115



f50( ) 115



f25( ) 115



V-overscan in %:

f 100( ) 120.7



f75( ) 111.1



f50( ) 99.6



f25()86



Mode 3 (linear function, BSO = 11):

120
112
104

96
88
80
72

V-overscan in %

64
56
48
40

0 10 20 30 40 50 60 70 80 90 100

V-overscan = f (voltage at BSOIN)

voltage BSOIN in %

V-overscan in %:

f 100( ) 116.5



f75( ) 98.8



f50()81



f25()63



Micronas 11-58 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Waveforms

11.3 Power On/Off diagram

Supply
Voltage

Power­On­Reset

X1, X2

HD

2

I C-Bus

VREFH

Protection
(HPROT
>1.5V)

max. 2.6V

active
inactive

32768
cycles

SSD=0: ~ 8 lines
SSD=1: ~12 lines

IIC registers 01..1C

programmable

ready

min. 1.5V

tri-

state

32768
cycles

SSD=0: ~ 8 lines
SSD=1: ~12 lines

IIC registers 01..1C

programmable

ready

tristatetristate

I2C-Reg.

00, 1D..30h

I2C-Reg.

01..1C

de-

fault

default

programmable

programmable

de-

fault

default

programmable

programmable

de-

fault

de-

fault

CLL

~ 42 cycles

CPU

active
inactive

power on

glitch

power off

Micronas 11-59 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Waveforms

11.4 Standby mode, RESN diagram

Standby

RESN

HD

CPU

VREFH

Protection
(HPROT
>1.5V)

I2C-Reg.

01..1C

Phi2-loop

active

inactive

active

inactive

active

inactive

programmable

~ 42 CLL

cycles

free run

default values

Phi2-loop

programmable

~ 42 CLL

cycles

free run

default values

Phi2-loop

programmable

I2C-Reg.

programmable

00, 1D..30h

Standby mode

ext. reset

Micronas 11-60 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Waveforms

11.5 Function of H,V protection

HPROT VPROT Mode SCP HPON VPON

(IIC-Bus)

V1

1

V2

V1

2

or

V2

3

start up

H, V in

operation

EHT over-

voltage

continuous

blanking

a)

continuous

blanking

after t

2

after t

b)

(IIC-Bus)

0

00

1

2

b)

0

0

4

or

or

t0 < t < t

or

5

6

or

t > t

1

or

t > t

1

t0 = 2/fv...3/fv t1 = 64/fv...128/fv t2 = 1/fv...2/f
a) depends on IIC control items

b) HPON = 1 or VPON = 1: HD = 1(off)

H in

operation

V short
failure

1

V longer

failure

H off
after t

EHT

short over-

voltage

v

1

continuous

blanking

after t

if SSC = 0

0

continuous

blanking

after t

if SSC = 0

0

continuous

blanking

after t

2

00

0

1

after t

2

1

after t

1

after t

1

1

Micronas 11-61 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Waveforms

11.6 Black Stretch diagram

100

50

Output (IRE)

0

10050

Input

(IRE)

maximum blac k st retch

-30

11.7 Soft Clipping diagram

5V

4V

Output

nominal white drive)

3V

(R, G, B voltage measured at

the output relat iv e to cut-off at

2V

1V

0

0

range

+1

-1

0

Slope: IIC

soft clipping,

bits B1, B0

-2

AB

1V 2V 3V 4V 5V

Input

Micronas 11-62 2001-01-29

SDA 9380 - B21 Preliminary Data Sheet

Package outlines

12 Package outlines

P-MQFP-64

Micronas 12-63 2001-01-29

SDA 9380-B21 PRELIMINARY DATA SHEET

Micronas GmbH
Hans-Bunte-Strasse 19
D-79108 Freiburg (Germany)
P.O. Box 840
D-79008 Freiburg (Germany)
Tel. [phone]
Fax [phone]
E-mail: [e-mail]
Internet: www.micronas.com

Printed in Germany
Order No. 6251-549-1PD

All information and data contained in this data sheet are without any
commitment, are not to be considered as an offer for conclusion of a
contract, nor shall they be construed as to create any liability. Any new
issue of this data sheet invalidates previous issues. Product availability
and delivery ar e exclusively subj ec t t o o ur re s pe ct ive or der co nf irm at ion
form; the same applies to orders based on development samples deliv­ered. By this pu bli cat io n, Mi cr on as Gmb H do es no t assu m e r es po n sibi l­ity for patent infringements or other ri ghts of third parties which m ay
result from its use.
Further , M icro nas G mbH r eserv es th e righ t to revis e thi s pu blicat ion a nd
to make chang es to its cont en t, at any time , wi thout obli gati on t o no tify
any person or entity of such revisions or changes.
No part of this publication may be reproduced, photocopied, stored on a
retrieval system, or transmitted without the express written consent of
Micronas GmbH .

72 Micronas