Datasheet SDA5648, SDA5648X Datasheet (Siemens)

Decoder for Program Delivery
Control and Video Program System
PDC / VPS Decoder

Features

● Single-chip receiver for PDC data, broadcast either

– in Broadcast Data Service Packet (BDSP) 8/30/2

according to CCIR teletext system B, or

– in dedicated line no. 16 of the vertical blanking interval

(VPS)

● Reception of Unified Date and Time (UDT) broadcast in

BDSP 8/30/1

● Low external components count

● On-chip data and sync slicer

2

● I

C-Bus interface for communication with external

microcontroller

● Selection of PDC/VPS operating mode software controlled

by I2C-Bus register

● Pin and software compatible to VPS Decoder SDA 5642

● Supply voltage: 5 V ± 10 %

● Video input signal level: 0.7 Vpp to 1.4 Vpp

● Technology: CMOS

● Package: P-DIP-14-3 and P-DSO-20-1

● Operating temperature range: 0 to 70 °C

SDA 5648

SDA 5648X

CMOS IC

P-DIP-14-3

P-DSO-20-1

Type Ordering Code Package

SDA 5648 Q67000-A5186 P-DIP-14-3
SDA 5648X Q67006-A5198 P-DSO-20-1 Tape & Reel

Functional Description

The CMOS circuit SDA 5648 is intended for use in video cassette recorders to retrieve control data
of the PDC system from the data lines broadcast during the vertical blanking interval of a standard
video signal.

The SDA 5648 is devised to handle PDC data transported either in Broadcast Data Service Packet
(BDSP) 8/30 format 2 (bytes no. 13 through 25) of CCIR teletext system B or in the dedicated data
line no. 16 in the case of VPS.

Furthermore it is able to receive the Unified Date and Time (UDT) information transmitted in bytes
no. 15 through 21 of packet 8/30 format 1.

Semiconductor Group 21 12.94

Pin Configuration

(top view)

SDA 5648

SDA 5648X

P-DIP-14-3

P-DSO-20-1

Operating mode (PDC/VPS) is selected by a control register which can be written to via theI
interface.

2

C-Bus

Semiconductor Group 22

Pin Definitions and Functions

SDA 5648

SDA 5648X

Pin No.
P-DIP-14-3

1

Pin No.
P-DSO-20-1

1
2

Symbol Function

V

SS

V

SSA

V

SSD

Ground (0 V)
Analog ground (0 V)
Digital ground (0 V)

3 N.C. Not connected
2 4 SCL Serial clock input of I
3 5 SDA Serial data input of I
4 6 CS0 Chip select input determining the I

2

C-Bus.

2

C-Bus.

2

C-Bus addresses:
20H / 21H, when pulled low
22H / 23H, when pulled high.

5 7 VCS Video Composite Sync output from sync slicer used for

PLL based clock generation.

8 N.C. Not connected

6 9 DAVN Data available output active low, when PDC/VPS data

is received.

7 10 EHB Output signaling the presence of the first field active

high.

8 11 TI Test input; activates test mode when pulled high.
9 12 PD1 Phase detector/charge pump output of data PLL

(DAPLL).

13 N.C. Not connected
10 14 PD2/VCO2 Connector of the loop filter for the SYSPLL.
11 15 VCO1 Input to the voltage controlled oscillator #1 of the

DAPLL.

12 16

I

REF

Reference current input for the on-chip analog circuit.

13 17 CVBS Composite video signal input.

18 N.C. Not connected
14

19

V

DD

V

DDD

Positive supply voltage (+ 5 V nom.).
Positive supply voltage for the digital circuits

(+ 5 V nom.).

20

V

DDA

Positive supply voltage for the analog circuits
(+ 5 V nom.).

Semiconductor Group 23

SDA 5648

SDA 5648X

Block Diagram

Semiconductor Group 24

SDA 5648

SDA 5648X

Circuit Description

Referring to the functional block diagram of the PDC / VPS decoder, the composite video signal with
negative going sync pulses is coupled to the pin CVBS through a capacitor which is used for
clamping the bottom of the sync pulses to an internally fixed level. The signal is passed on to the
slicer, an analog circuitry separating the sync and the data parts of the CVBS signal, thus yielding
the digital composite sync signal VCS and a digital data signal for further processing by comparing
those signals to internally generated slicing levels.

The output of the sync separator is forwarded, on one hand, to the output pin VCS, and on the other
hand, to the clock generator and the Timing block. The VCS signal represents a key signal that is
used for deriving a system clock signal by means of a PLL.

The data slicer separates the data signal from the CVBS signal by comparing the video voltage to
an internally generated slicing level which is found by averaging the data signal during TV line no.
16 in the VPS mode or by averaging the data signal during the clock run-in period of the teletext
lines during the data entry window (DEW) in PDC mode.

The clock generator delivers the system clock needed for the basic timing as well as for the
regeneration of the data clock. It is based on two phase locked loops (PLL’s) all parts of which are
integrated on chip with the exception of the loop filter components. Each of the PLL’s is composed
of a voltage controlled oscillator (VCO), a phase/frequency detector (PFD), and a charge pump
which converts the digital output signals of the PFD to an analog current. That current is
transformed to a control voltage for the VCO by the off-chip loop filter. The generated VCO fre­quencies are 10 MHz and 13.875 MHz for VPS mode and PDC mode, respectively.

All signals necessary for the control of sync and data slicing as well as for the data acquisition are
generated by the Timing block.

In PDC mode, only teletext rows 8/30 containing Broadcast Data Service Package (BDSP) infor­mation are acquired. The relevant bytes of 8/30 format 1 (8/30/1) and 8/30 format 2 (8/30/2) are
extracted. The 8/30/1-bytes are stored in the acquisition register in a transparent way without any
bit manipulation, whereas the Hamming coded bytes of packet 8/30/2 are Hamming-checked and
bytes with one bit error are corrected. The storage of error free or corrected 8/30/2-data bytes in the
transfer register to the I2C-Bus is signalled by the DAVN output going low. The reception and
storage of 8/30/1- data, however, is not indicated by the DAVN output. The presence of 8/30/1 data
can only be checked by polling the data register via the I2C-Bus.

In VPS mode, the extracted data bits of TV line no. 16 are checked for biphase errors. With no
biphase errors encountered, the acquired bytes are stored in the transfer register to the I2C-Bus.
That transfer is signalled by a H/L transition of the DAVN output, as well.

In both operating modes data are updated when a new data line has been received, provided that
the chip is not accessed via the I2C-Bus at the same time.

A micro controller can read the stored bytes via the I2C-Bus interface at any time. However, one
must be aware that the storage of new data from the acquisition interface is inhibited as long as the
PDC decoder is being accessed via the I2C-Bus. At the end of an I2C-Bus reading the transfer
registers are set to FF (hex) until they are updated by the reception of new data packet contained
in the CVBS signal.

Semiconductor Group 25

SDA 5648

SDA 5648X

I2C-Bus

General Information

The I2C-Bus interface implemented on the PDC decoder is a slave transmitter/receiver, i.e., both
reading from and writing to the PDC / VPS decoder is possible. The clock line SCL is controlled only
by the bus master usually being a micro controller, whereas the SDA line is controlled either by the
master or by the slave. A data transfer can only be initiated by the bus master when the bus is free,
i.e., both SDA and SCL lines are in a high state. As a general rule for the I2C-Bus, the SDA line
changes state only when the SCL line is low. The only exception to that rule are the Start Condition
and the Stop Condition. Further details are given below. The following abbreviations are used:

START : Start Condition generated by master
AS : Ackknowledge by slave
AM : Ackknowledge by master
NAM : No Ackknowledge by master
STOP : Stop Condition generated by master

Chip Address

There are two pairs of chip addresses, which are selected by the CS0-input pin according to the
following table

CS0 Input Write Mode Read Mode

Low 20 (hex) 21 (hex)
High 22 (hex) 23 (hex)

Write Mode

For writing to the PDC decoder, the following format has to be used:

START Chipadress White Mode AS Byte Set Control Register AS STOP

Data Transfer (Write Mode)

Step1

: In order to start a data transfer the master generates a Start Condition on the bus by pulling

the SDA line low while the SCL line is held high.

Step 2
Step 3

: The bus master puts the chip address on the SDA line during the next eight SCL pulses.
: The master releases the SDA line during the ninth clock pulse. Thus the slave can generate

an acknowledge (AS) by pulling the SDA line to a low level.

Step 4
Step 5
Step 6

The write mode is used to set the I2C-Bus control register which determines the operating mode:

Semiconductor Group 26

: The controller transmits the data byte to set the Control register.
: The slave acknowledges the reception of the byte.
: The master concludes the data communication by generating a Stop Condition.

SDA 5648

SDA 5648X

Control Register

Bit Number 7 6 5 4 3 2 1 0

T4 T3 T2 T1 T0 DIS PDC/

VPS

Default: All bits are set to 0 on power-up.

Bit 0: Determines, which kind of data is accessed via the I2C-Bus when PDC mode is active.

Value

01
BDSP

8/ 30/ 2
data accessible

Bit 1: Determines the operating mode.

01
VPS mode active PDC mode active

BDSP 8/ 30/ 1 or
header row
data accessible (refer to description of Bit 2)

Value

FOR1/

FOR2

Bits 2 through 7 are used for test purposes.
DIS: Don‘t care.
Bits 3 through 7 must not be changed for normal operation by user software!

Read Mode

For reading from the PDC decoder, the following format has to be used.

START Chipaddress Read Mode AS 1st Byte AM … Last

Byte

NAM STOP

Semiconductor Group 27

SDA 5648X

Data Transfer (Read Mode)

Step1

: To start a data transfer the master generates a Start Condition on the bus by pulling the

SDA line low while the SCL line is held high. The byte address counter in the decoder is
reset and points to the first byte to be output.

SDA 5648

Step 2
Step 3

Step 4

Step 5

Step 6
Step 7
Step 8

Step 9

: The bus master puts the chip address on the SDA line during the next eight SCL pulses.
: The master releases the SDA line during the ninth clock pulse. Thus the slave can generate

an acknowledge (AS) by pulling the SDA line to a low level. At this moment, the slave
switches to transmitting mode.

: During the next eight clock pulses the slave puts the addressed data byte onto the SDA

line.

: The reception of the byte is acknowledged by the master device which, in turn, pulls down

the SDA line during the next SCL clock pulse. By acknowledging a byte, the master
prompts the slave to increment its internal address counter and to provide the output of the

next data byte.
: Steps no. 4 and no. 5 are repeated, until the desired amount of bytes have been read.
: The last byte is output by the slave since it will not be acknowledged by the master.
: To conclude the read operation, the master doesn’t acknowledge the last byte to be

received. A No Acknowledge by the master (NAM) causes the slave to switch from

transmitting to receiving mode. Note that the master can prematurely cease any reading

operation by not acknowledging a byte.
: The master gains control over the SDA line and concludes the data transfer by generating

a Stop Condition on the bus, i. e., by producing a low/high transition on the SDA line while

the SCL line is in a high state. With the SDA and the SCL lines being both in a high state,

the I2C-Bus is free and ready for another data transfer to be started.

The contents of up to 7 registers (bytes) can be read starting with byte 1 bit 7 (refer to the following
table).

Semiconductor Group 28

SDA 5648

SDA 5648X

Order of Data Output on the I2C-Bus and Bit Allocation of the 3 Different Operating Modes

I2C-Bus PDC Packet 8/30 VPS Mode

Format 1 Format 2

Byte 1 bit 7

t

byte 15 bit 0
6
5
4
3
2
1
0

2)

byte 16 bit 0
1
2
3
4

byte 17 bit 0
5
6
7

1)

byte 11 bit 0
1
2
3

1
2
3

2)

1
2
3
4
5
6
7

Byte 2 bit 7

Byte 3 bit 7

Byte 4 bit 7

byte 16 bit 0
6
5
4
3
2
1
0

byte 17 bit 0
6
5
4
3
2
1
0

byte 18 bit 0
6
5
4
3
2
1
0

byte 18 bit 0
1
2
3
4

byte 19 bit 0
5
6
7

byte 20 bit 0
1
2
3
4

byte 21 bit 0
5
6
7

byte 22 bit 0
1
2
3
4

byte 23 bit 0
5
6
7

byte 12 bit 0
1
2
3

1
2
3

byte 13 bit 0
1
2
3

1
2
3

byte 14 bit 0
1
2
3

1
2
3

1
2
3
4
5
6
7

1
2
3
4
5
6
7

1
2
3
4
5
6
7

1) Message bit numbers according to EBU specification of PDC system.

2) Transmission bit number

Semiconductor Group 29

SDA 5648

SDA 5648X

Order of Data Output on the I2C-Bus and Bit Allocation of the 3 Different Operating Modes

(cont’d)

I2C-Bus PDC Packet 8/30 VPS Mode

Format 1 Format 2

Byte 5 bit 7

Byte 6 bit 7

Byte 7 bit 7

byte 19 bit 0
6
5
4
3
2
1
0

byte 20 bit 0
6
5
4
3
2
1
0

byte 21 bit 0
6
5
4
3
2
1
0

byte 14 bit 0
1
2
3
4

byte 15 bit 0
5
6
7

byte 24 bit 0
1
2
3
4

byte 25 bit 0
5
6
7

byte 13 bit 0
1
2
3
4

– set to “1”
5

– set to “1”
6

– set to “1”
7

– set to “1”

byte 5 bit 0
1
2
3

1
2
3

byte 15 bit 0
1
2
3

1
2
3

– set to “1”
1

– set to “1”
2

– set to “1”
3

– set to “1”

– set to “1”

– set to “1”

– set to “1”

– set to “1”

1
2
3
4
5
6
7

1
2
3
4
5
6
7

Semiconductor Group 30

Description of DAVN and EHB Outputs

DAVN (Data Valid active low)
EHB (First Field active high)

Signal Output VPS Mode PDC Mode

8/30/2 8/30/1

DAVN

SDA 5648

SDA 5648X

H/L-transition

(set low)

L/H-transition

(set high)
always set high on power-up or

EHB

L/H-transition at the beginning of the first field
H/L-transition at the beginning of the second field

In test mode (i.e. TI = high), both DAVN and EHB are controlled by the CS0 pin and reproduce the
state of the CS0 input.

in line 16 when
valid VPS data is
received

at the start of
line 16

during I
acknowledge in order to generate the stop condition

2

C-Bus accesses when the bus master doesn’t

in the line
carrying
valid
8/30/2 data

at the beginning of the next field
i.e.,at the start of the next data entry window

in the line
carrying
valid
8/30/1 data

Semiconductor Group 31

SDA 5648

SDA 5648X

Electrical Characteristics

Absolute Maximum Ratings

T

= 25 °C

A

Parameter Symbol Limit Values Unit Test

min. typ. max.

Condition

Ambient temperature T
Storage temperature
Total power dissipation
Power dissipation per output
Input voltage
Supply voltage
Thermal resistance

Operating Range

Supply voltage V
Supply current
Ambient temperature range

Characteristics

T

= 25 °C

A

T
P
P
V
V
R

I
T

A

stg

tot

DQ

IM

DD

th SU

DD

DD

A

070°C in operation
– 40 125 °C by storage

300 mW

10 mW
– 0.3 6 V
– 0.3 6 V

80 K/W

4.5 5 5.5 V

515mA

070°C

Parameter Symbol Limit Values Unit Test

min. typ. max.

Condition

Input Signals SDA, SCL, CS0

H-input voltage
L-input voltage
Input capacitance
Input current

V
V
C
I

IH

IL

I

IM

0.7 × V

DD

0 0.3 × V

V

DD

DD

V

V
10 pF
10 µA

Input Signal TI

H-input voltage V
L-input voltage
Input capacitance
Input current

V
C
I

IH

IL

I

IM

0.9 × V

DD

V

DD

0 0.1 × V

10 pF
10 µA

DD

V

V

Semiconductor Group 32

SDA 5648

SDA 5648X

Characteristics (cont’d)

T

= 25 °C

A

Parameter Symbol Limit Values Unit Test

min. typ. max.

Input Signals CVBS

(pos. Video, neg. Sync)

Condition

Video input signal level
Synchron signal amplitude
Data amplitude

Coupling capacitor
H-input current
L-input current
Source impedance

V
V
V

C
I
I
R

CVBS

SYNC

DAT

C

IH

IL

S

0.7 1.0 2.0 V

0.15 0.3 1.0 V

0.25

1.5 × V

0.5 1.0 V VPS mode

SYNC

33 nF

10 µA VI=5V

– 1000 – 400 – 100 µA VI=0V

250 Ω

Leakage resistance at
coupling capacitor

R

C

0.91 1 1.2 MΩ

Output Signals DAVN, EHB, VCS

H-output voltage V
L-output voltage

QH

V

QL

V

– 0.5 V IQ= – 100 µA

DD

0.4 V IQ= 1.6 mA

Output Signals SDA (Open-Drain-Stage)

L-output voltage V

QL

0.4 V IQ= 3.0 mA

Permissible output voltage 5.5 V

PDC mode

PLL-Loop Filter Components (see application circuit)

Resistance at PD2/VCO2
Resistance at VCO1
Attenuation resistance
Resistance at PD2/VCO2
Integration capacitor
Integration capacitor

R
R
R
R
C
C

1

2

3

5

1

3

6.8 kΩ
1200 kΩ

6.8 kΩ
1200 kΩ

2.2 nF
33 nF

VCO – Frequence Range Adjustment

Resistance at IREF (for bias
current adjustment) R

4

100 kΩ

Semiconductor Group 33

SDA 5648

SDA 5648X

I2C-Bus Timing

Parameter Symbol Limit Values Unit

min. max.

Clock frequency
Inactive time prior to new transmission start-up
Hold time during start condition
Low-period of clock
High-period of clock
Set-up time for data
Rise time for SDA and SCL signal
Fall time for SDA and SCL signal

Set-up time for SCL clock during stop condition

f

SCL

t

BUF

t

HD;STA

t

LOW

t

HIGH

t

SU;DAT

t

TLH

t

THL

t

SU;STO

0 100 kHz

4.7 µs

4.0 µs

4.7 µs

4.0 µs
250 ns

1 µs
300 ns

4.7 µs

All values referred to

V

and VIL levels.

IH

Semiconductor Group 34

PDC/VPS-Receiver

SDA 5648

SDA 5648X

Application Circuit

Semiconductor Group 35

SDA 5648

SDA 5648X

I2C-Bus Signals During Write Operations

Semiconductor Group 36

SDA 5648

SDA 5648X

I2C-Bus Signals During Read Operations

Semiconductor Group 37

SDA 5648

SDA 5648X

Semiconductor Group 38

SDA 5648

SDA 5648X

Position of Teletext and VPS Data Lines within the Vertical Blanking Interval

(shown for first field)

Definition of Voltage Levels for VPS Data Line

Semiconductor Group 39

BDSP 8/30 Format 1 Bit Allocation

Byte No. Bit No. Contents

01234567

SDA 5648

SDA 5648X

15 Weight Weight Sign

–22–120

2

2122230

1

16

17 MJD Digit

18 MJD Digit

19 UTC Hours

MJD Digit
Weight 10

Weight 10

Weight 10

Units

4

1111

MJD Digit

2

Weight 10

3

MJD Digit

0

Weight 10

1

UTC Hours
Tens

Time Offset Code

Modified Julian Date (MJD)

1. Byte

Modified Julian Date

2. Byte

Modified Julian Date (MJD)

3. Byte

Universal Time Coordinated (UTC)

1. Byte

20 UTC Minutes

Units

21 UTC Seconds

Units

UTC Minutes
Tens

UTC Seconds
Tens

Universal Time Coordinated

2. Byte

Universal Time Coordinated

3. Byte

This corresponds to the coding adopted in CCIR teletext system B BDSP 8/30 format 1.

2

NB: The received bytes are output on the I

C-bus in a transparent way, i.e., on a bit-first-in-first-out
basis. No bit manipulation is performed on the chip in this operating mode. When evaluating the
numbers, note that each 4-bit-digit has been incremented by one prior to transmission, and the least
significant bits are transmitted first.

Semiconductor Group 40

SDA 5648

SDA 5648X

Structure of the Teletext Data Packet 8/30 Format 2

Semiconductor Group 41

SDA 5648

SDA 5648X

BDSP 8/30 Format 2 Bit Allocation

The four message bits of byte 13 are used as follows:
byte 13 bit 0 – LCI b1) label channel identifier

1 – LCI b2)
2 – LUF label update flag
3 – reserved but as yet undefined

The message bits of bytes 14 – 25 are used in a way similar to the coding of the label in the
dedicated television line as follows:

byte 14 bit 0 PCS b1) status of byte 20 bit 0 PIL b15)

1 PCS b2) analogue sound 1 PIL b16)

2 PIL b17) minute
2 ) reserved but yet 3 PIL b18)
3 ) undefined byte 21 bit 0 PIL b19)

1 PIL b20)

byte 15 bit 0 CNI b1)

1 CNI b2) country 2 CNI b5)
2 CNI b3) 3 CNI b6) country
3 CNI b4) byte 22 bit 0 CNI b7)

1 CNI b8)

byte 16 bit 0 CNI b9) network (or

1 CNI b10) program provider) 2 CNI b11)

3 CNI b12)
2 PIL b1) byte 23 bit 0 CNI b13) network (or
3 PIL b2) 1 CNI b14) program

byte 17 bit 0 PIL b3) day 2 CNI b15) provider)

1 PIL b4) 3 CNI b16)
2 PIL b5)

byte 24 bit 0 PTY b1)

3 PIL b6) 1 PTY b2)

byte 18 bit 0 PIL b7) month 2 PTY b3)

1 PIL b8) 3 PTY b4) program
2 PIL b9) byte 25 bit 0 PTY b5) type

1 PTY b6)
3 PIL b10) 2 PTY b7)

byte 19 bit 0 PIL b11) 3 PTY b8)

1 PIL b12) hour
2 PIL b13)
3 PIL b14)

Semiconductor Group 42

SDA 5648

.

.

SDA 5648X

Data Format of the Program Delivery Data in the Dedicated TV Line
















......





Time















......





































......







......

......










......










......

ML MLMLMLM LMLM LM L

binary

Program type

program

Network or

binary

Country

binary

Minute

Hour

binary

binary

Month

Day

binary

or

Net.

Not relevant
to PDC

Reserved for
enhancement
of VPS

and

1

: 00 don’t

2

Bits b

b

know

01mono

Not relevant
to PDC

Start

code

run-in

binary

provider

prov.

prog.

10stereo

11dual

bin.

and

sound

Bits b

3

N.......N N N 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 N ....................................... N A............................. A

are

4

b

reserved

Timer control code

N.......N N N 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 N ....................................... N A............................. A

N.......N N N 0 0 0 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 N ....................................... N A............................. A

Record inhibit/term.

1111 NN P................... ................ ...................... ......................P N .......................................N A .............................A

N.......N N N 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 N ....................................... N A............................. A

Interruption code

N.......N N N P ................... ................ ...................... ......................P N ....................................... N 1 1 1 1 1 1 1 1

Continuation code

Unenhanced VPS

PTY not in use

A = Bit value is that of the current PTY code

N = Bit value is that of the current CNI code

P = Bit value is that of the current PIL code

M = Most-significant bit

L = Least-significant bit

CNI = Country and Network Identification

PCS= Program Control Status

PIL = Program Identification Label

PTY = Program Type

, I = → 12341234 9101 2 3 4 5 6 7 8 910111213141516171819205 6 7 81112131415161 2 3 4 56 7 8

i

Parameter → PCS CNI CNI PIL CNI PTY

Byte No. → 1 2 3 & 4 5 6 to 10 11 12 13 14 15

Parameter bits b

Transmission bit No. → 01234567 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

Content → Clock

Reserved code

Semiconductor Group 43

values for

receiver control

(service codes)

Abbreviations: