Page 1
GHz PLL with I2C Bus
and Four Chip Addresses
Features
● 1-chip system for MPU
control (I
● 4 programmable chip addresses
● Short pull-in time for quick channel
switch-over and optimized loop
stability
2
C bus)
SDA 3302 Family
Bipolar ICPreliminary Data
● Charge pump output with switch
P-DIP-18-5 P-DSO-20-1
off option
● Up to 3*) high current band switch
outputs (20 mA)
● Up to 4*) output ports (5 mA)
*) depending on version
P-DSO-16-1
Type Ordering Code Package
SDA 3302-5 Q67000-H5112 P-DIP-18-5
SDA 3302-5X Q67000-H5111 P-DSO-20-1 (SMD)
SDA 3302-5X6 Q67000-H5110 P-DSO-16-1 (SMD)
SDA 3302-5X Q67006-H5111 P-DSO-20-1 Tape & Reel (SMD)
SDA 3302-5X6 Q67006-H5110 P-DSO-16-1 Tape & Reel (SMD)
Semiconductor Group 1
02.97
Page 2
SDA 3302 Family
Functional Description
Combined with a VCO (tuner) the SDA 3302 device, with four hardware-switched chip
addresses, forms a digitally programmable phase-locked loop for use in television sets with
PLL frequency-synthesis tuning.
The PLL permits precise crystal-controlled setting of the frequency of the tuner oscillators
between 16 and 1300 MHz in increments of 62.5 kHz. The tuning process is controlled by a
2
microprocessor via an I
the higher-order harmonics, which reduces the moiré noise considerably.
Circuit Description
Tuning Section (refer to block diagram)
UHF/VHF The tuner signal is capacitively coupled at the UHF/VHF input and
REF
subsequently amplified. The reference input REF should be decoupled to
ground using a capacitor of low series inductance. The signal passes
through an asynchronous divider with a fixed ratio of
divider with ratio N = 256 through 32767 and is then compared in a digital
phase/frequency detector to a reference frequency f
latter is derived from a balanced, low-impedance 4 MHz crystal oscillator
Q1, Q2 (pin Q1, Q2), whose output signal is divided by
C bus. The crystal oscillator generates a sinusoidal signal suppressing
P = 8, an adjustable
of 7.8125 kHz. The
REF
Q = 512.
The phase detector has two outputs UP and DOWN that drive the two current
sources
I+ and I– of a charge pump. If the negative edge of the divided VCO
signal appears prior to the negative edge of the reference signal, the I+
current source pulses for the duration of the phase difference. In the reverse
case the
I– current source pulses.
PD, UD When the two signals are in phase, the charge-pump output (PD) goes high-
impedance (PLL is locked). An active low-pass filter integrates the current
pulses to generate the tuning voltage for the VCO (internal amplifier an
external transistor at the UD output and an external RC circuitry). The
charge-pump output can also be set to high-impedance state when control
bit T0 = 1. Here it should be noted, however, that the tuning voltage can alter
over a long period in the high-impedance state as a result of self-discharge
in the peripheral circuitry. UD can be disconnected internally by the control
bit OS to enable external adjustments.
By means of a control bit 5I the pump current can be switched between two
values by software. This switchover permits alteration of the control
response of the PLL in the locked-in state. In this way different VCO gains in
the different TV bands can be compensated for example.
Semiconductor Group 2
Page 3
SDA 3302 Family
Circuit Description (cont’d)
P0-P2 The software-switched outputs (P0, P1, P2) can be used for direct band
selection (20-mA current output).
P4-P7 P4, P5, P6 and P7 are open-collector outputs for a variety of different
f
purposes. The test bit T1 = 1 switches the test signals
Cy (divided input signal) to P6 and P7.
CAS Four different chip addresses can be set by appropriate connection of pin
CAS.
2
C-Bus Interface
I
SCL, SDA Data are exchanged between the processor and the PLL on the I
clock is produced by the processor (input SCL), while pin SDA works as an
input or output depending on the direction of the data (open collector;
external pullup resistor). Both inputs have hysteresis and a lowpass
characteristic, which enhances the noise immunity of the I
The data from the processor are applied to an I
2
C bus controller and filed in
registers according to their function. When the bus is free, both lines are in
the marking state (SDA, SCL are high). Each telegram begins with a start
condition and ends with the stop condition. Start condition: SDA goes low
while SCL remains high; stop condition: SDA goes high while SCL remains
high. All further data exchanges occur while SCL is low and are accepted by
the controller with the positive clock edge.
(4 MHz/512) and
REF
2
C bus. The
2
C bus.
For what follows, refer to the table of logic allocations.
All telegrams are transmitted byte by byte, followed by a ninth clock pulse,
during which the controller puts the SDA line on low (acknowledge condition).
The first byte consists of seven address bits, with which the processor
selects the PLL from a number of peripheral devices (chip select). The eighth
bit is always low. In the data portion of the telegram the first bit of the first or
third data byte determines whether a divider ratio or control information
follows. In each case the byte following the first byte must be of the same
data type (or a stop condition).
V
, GND When the supply voltage is applied, a power-on reset circuit prevents the PLL
S
from putting the SDA line on low, which would block the bus.
Semiconductor Group 3
Page 4
Circuit Description (cont’d)
Logic Allocations
Address byte 11000MA1MA00A
Prog. divider byte 1 0 n14 n13 n12 n11 n10 n9 n8 A
Prog. divider byte 2 n7 n6 n5 n4 n3 n2 n1 n0 A
Control info. byte 1 1 5I T1 T0 1 1 1 OS A
SDA 3302 Family
MSB A = Acknowledge
Control info. byte 2 P7 P6 P5 P4 X P2 P1 P0 A
Divider Ratio
N = 16384 × n14 + 8192 × n13 + 4096 × n12 + 2048× n11 + 1024 × n10 + 512 × n9 + 256 × n8 +
+ 128
+ n0
Band Selection
P2-P0 = 1 Open-collector output is active.
Port Outputs
P7-P4 = 1 Open-collector output is active.
Pump Current Switchover
5I = 1 High current.
UD Disable
OS = 1
V
Test Mode
T1, T0 = 0,0 Normal mode
T1 = 1 P6 =
T0 = 1 Tristate charge pump PD is in high-impedance.
× n7 + 64 × n6 + 32 × n5 + 16 × n4 + 8 × n3 + 4 × n2 + 2 × n1
is disabled.
D
f
; P7 = Cy
REF
Semiconductor Group 4
Page 5
Circuit Description (cont’d)
Chip-Address Switching
MA1 MA0 Voltage on CAS
SDA 3302 Family
00
(0-0.1)
0 1 open
10
11
(0.4-0.6)
(0.9-1) V
V
S
V
S
S
Pulse Diagram
Telegram Examples
Start-Addr-DR1-DR2-CW1-CW2-Stop Start = start condition
Start-Addr-CW1-CW2-DR1-DR2-Stop Addr = address
Start-Addr-DR1-DR2-CW1-Stop DR1 = divider ratio 1st byte
Start-Addr-CW1-CW2-DR1-Stop DR2 = divider ratio 2nd byte
Start-Addr-DR1-DR2-Stop CW1 = control word 1st byte
Start-Addr-CW1-CW2-Stop CW2 = control word 2nd byte
Start-Addr-DR1-Stop Stop = stop condition
Semiconductor Group 5
Page 6
Pin Configuration (SDA 3302-5)
(top view)
SDA 3302 Family
P-DIP-18-5
Semiconductor Group 6
Page 7
Pin Definitions and Functions (SDA 3302-5)
Pin No. Symbol Function
1 PD Active-filter input/charge-pump output
2 Q1 Crystal
3 Q2 Crystal
SDA 3302 Family
4 SDA
5 SCL
Data input/output for I
Clock input for I2C bus
2
C bus
6 P7 Port output (open collector)
7 P6 Port output (open collector)
8 P5 Port output (open collector)
9 P4 Port output (open collector)
10 CAS Chip-address switchover
11 P2 Port output (open collector)
12 P1 Port output (open collector)
13 P0 Port output (open collector)
14
V
S
Supply voltage
15 UHF/VHF Signal input
16 REF Amplifier reference input
17 GND Ground
18 UD Output active filter
Semiconductor Group 7
Page 8
Pin Configuration (SDA 3302-5X)
(top view)
SDA 3302 Family
P-DSO-20-1
Semiconductor Group 8
Page 9
Pin Definitions and Functions (SDA 3302-5X)
Pin No. Symbol Function
1 PD Active-filter input/charge-pump output
2 Q1 Crystal
3 Q2 Crystal
4 N.C. Not connected
SDA 3302 Family
5 SDA
6 SCL
Data input/output for I
Clock input for I2C bus
2
C bus
7 P7 Port output (open collector)
8 N.C. Not connected
9 P6 Port output (open collector)
10 P5 Port output (open collector)
11 P4 Port output (open collector)
12 CAS Chip-address switchover
13 P2 Port output (open collector)
14 P1 Port output (open collector)
15 P0 Port output (open collector)
16
V
S
Supply voltage
17 UHF/VHF Signal input
18 REF Amplifier reference input
19 GND Ground
20 UD Active-filter output
Semiconductor Group 9
Page 10
Pin Configuration (SDA 3302-5X6)
(top view)
SDA 3302 Family
P-DSO-16-1
Semiconductor Group 10
Page 11
Pin Definitions and Functions (SDA 3302-5X6)
Pin No. Symbol Function
1 PD Active-filter input/output pump output
2 Q1 Crystal
3 Q2 Crystal
SDA 3302 Family
4 SDA
5 SCL
Data input/output for I
Clock input for I2C bus
2
C bus
6 P7 Port output (open collector)
7 P6 Port output (open collector)
8 P5 Port output (open collector)
9 P4 Port output (open collector)
10 CAS Chip-address switchover
11 P1 Port output (open collector)
12
V
S
Supply voltage
13 UHF/VHF Signal input
14 REF Amplifier reference input
15 GND Ground
16 UD Output active filter
Semiconductor Group 11
Page 12
Pin Definitions and Functions, Reference List
SDA 3302 Family
SDA 3302
P-DIP-18-5
Pin No.
SDA 3302X
P-DSO-20-1
Pin No.
SDA 3302X6
P-DSO-16-1
Pin No.
Symbol Function
1 1 1 PD Input active-filter input charge
pump output
2 2 2 Q1 Crystal
3 3 3 Q2 Crystal
- 4 - N.C. Not connected
4 5 4 SDA
5 6 5 SCL
Data input/output for I
Clock input for I2C bus
2
C bus
6 7 6 P7 Port output (open collector)
- 8 - N.C. Not connected
7 9 7 P6 Port output (open collector)
8 10 8 P5 Port output (open collector)
9 11 9 P4 Port output (open collector)
10 12 10 CAS Chip-address switchover
11 13 - P2 Port output (open collector)
12 14 11 P1 Port output (open collector)
13 15 - P0 Port output (open collector)
14 16 12
V
S
Supply voltage
15 17 13 UHF/VHF Signal input
16 18 14 REF Amplifier reference input
17 19 15 GND Ground
18 20 16 UD Output active filter
Semiconductor Group 12
Page 13
SDA 3302 Family
Block Diagram SDA 3302-5
Pin nos. refer to P-DIP-18 package only. For other packages, see reference list on page 16
Semiconductor Group 13
Page 14
Absolute Maximum Ratings
T
= 25 °C
A
SDA 3302 Family
Parameter
Supply voltage
Output PD
Crystal Q1
Crystal Q2
Bus input/output SDA
Bus input SCL
Port output P7, P6, P5, P4
Chip-address switchover
Port output P2, P1, P0
Signal input UHF/VHF
Reference input REF
Symbol
V
S
V
1
V
2
V
3
V
4
V
5
V
6, 7, 8, 9
V
10
V
11, 12, 13
V
15
V
16
2)
Limit Values Unit Remarks
min. max.
– 0.3 6 V
– 0.3
– 0.3
– 0.3
V
S
V
S
V
S
V
V
V
– 0.3 6 V
– 0.3 6 V
– 0.3 16 V
– 0.3
V
S
V
– 0.3 16 V open collector
– 0.3 0.3 V
– 0.3 0.3 V
for
for
V
S
V
S
= 0 V
= 0 V
Output active filter UD
Bus output SDA
Port output P7, P6, P5, P4
Port output P2, P1, P0
Chip temperature
Total port output current
Storage temperature
Thermal resistance (system-air)
2) Pin nos. refer to P-DIP-18 package
V
18
I
4L
I
6L, 7L, 8L, 9L
I
11L, 12L, 13L
T
C
Z
IL
T
stg
R
thSA
– 0.3
V
S
V
– 1 5 mA open collector
– 1 5 mA open collector
– 1 20 mA open collector
125 °C
25 mA
– 40 125 °C
80 K/W
Semiconductor Group 14
Page 15
Absolute Maximum Ratings
T
= 25 °C
A
SDA 3302 Family
Parameter
Symbol
Operating Range
Supply voltage
Ambient temperature
Input frequency
Crystal frequency
Programmable divider factor
1)Design note: no 100 % final inspection.
2)Pin nos. refer to P-DIP-18 package
V
T
f
f
N
15
2, 3
2)
Limit Values Unit Remarks
min. max.
S
A
4.5 5.5 V
–20 80 °C
16 1300 MHz
4 MHz
256 32767
Semiconductor Group 15
Page 16
Characteristics
V
= 5 V; TA=25°C
S
SDA 3302 Family
Parameter
Current
Symbol
I
S
consumption
Crystal-oscillator
f
2, 3
frequency
1)
Oscillator level
V
2, 3
(Voltage across
crystal)
Margin from 1st
1)
and 2nd harmonic
Input Sensitivity UHF/VHF
a
15
a
15
a
15
2)
Limit Values Unit Test Condition Test
min. typ. max.
35 mA
V
=5 V
S
3.99975 4.000 4.00025 MHz series capacitance 18 pF;
f
= 4 MHz
xtal
2.6 Vpp
20 dB
– 27/10
– 27/10
– 27/10
3/315
3/315
3/315
3)
= 70-500 MHz
f
15
= 1000 MHz
f
15
= 1100 MHz
f
15
Circuit
1
1
2
2
2
Band-Select Outputs P0-P2 (switch with open collector)
Reserve current
Residual voltage
I
V
13H
13L
10 µA
0.5 V
Port Outputs P4-P7 (switch with open collector)
Reserve current
Residual voltage
Note: The sum of the currents in ports P0-P7 must not exceed 25 mA
I
9H
V
9L
10 µA
0.5 V
Phase-Detector Output PD
Pump current
Pump current
Output voltage
1) Design note: no 100 % final inspection.
2) Pin nos. refer to P-DIP-18 package
3) dBm/mV
into 50 Ω
rms
I
1H
I
1H
V
1L
± 90 ± 230 ± 300 µA5I= HIGH;
± 22 ± 50 ± 75 µA5I= LOW;
1.0 2.5 V locked
V
13H
I
=20mA
13H
V
= 13.5 V
9H
I
= 1.7 mA
9L
V
=2 V
1
V
=2 V
1
= 13.5 V
3
3
4
4
Semiconductor Group 16
Page 17
Characteristics (cont’d)
V
= 5 V; TA=25°C
S
SDA 3302 Family
Parameter
Symbol
2)
min. typ. max.
Output Active Filter UD (T0 = 1)
Output current
Output voltage
Output voltage
–
I
18
V
18
V
18
500 µA
Chip-Address Switchover
Input current
Input current
I
10H
–I
10H
Bus Inputs SCL, SDA
Input voltage
V
5H
V
5L
3 5.5
Limit Values Unit Test Condition Test
Circuit
5
5
100 mV
V
= 0.8 V;
18
I
=90µA
IH
V
=0 V
1L
500 mV OS = 1 5
50 µA
50 µA
V
5.5
V
V
=5 V
10H
V
=0 V
10H
7
7
6
6
Input current
Input current
I
5H
I
–
5L
Output SDA (open collector)
Reverse current
Output voltage
I
4H
V
4L
Edges SCL, SDA
Rise time
Fall time
t
R
t
F
Shift Clock SCL
Frequency
H-pulse width
L-pulse width
f
5
t
5H
t
5L
10 µA
20 µA
10 µA
0.4 V
V
5H
V
5L
V
4H
I
=3mA
4L
= V
S
=0 V
= 5.5 V
6
6
6
6
1 µs6
0.3 µs6
0 100 kHz 6
4 µs6
4.7 µs6
2) Pin nos. refer to P-DIP-18 package
Semiconductor Group 17
Page 18
Characteristics (cont’d)
V
= 5 V; TA=25°C
S
SDA 3302 Family
Parameter
Start
Setup time
Hold time
Stop
Setup time
Bus free
Data Exchange
Setup time
Hold time
Input hysteresis
SCL, SDA
1)
Symbol
t
SUSta
t
HDSta
t
SUsto
t
BUF
t
SUDat
t
HDDat
2)
Limit Values Unit Test Condition Test
Circuit
min. typ. max.
4.7 µs6
4 µs6
4.7 µs6
4.7 µs6
0.25 µs6
0 µs6
300 mV
Lowpass cutoff
1)
frequency
SCL, SDA
1) Design note: no 100 % final inspection.
2) Pin nos. refer to P-DIP-18 package
500 kHz
Semiconductor Group 18
Page 19
SDA 3302 Family
Test Circuit 1
Semiconductor Group 19
Page 20
SDA 3302 Family
Test Circuit 2
Test Circuit 3
Semiconductor Group 20
Page 21
SDA 3302 Family
Test Circuit 4
Test Circuit 5
Semiconductor Group 21
Page 22
I2C Bus Timing Diagram
SDA 3302 Family
Test Circuit 6
Test Circuit 7
Semiconductor Group 22
Page 23
SDA 3302 Family
Application Circuit
Semiconductor Group 23
Page 24
Application Circuit
SDA 3302 Family
Calculation of Loop Filter
Loop bandwidth ωR= √ (I
Attenuation: ξ = 0.5 × ω
× K
p
) / (C
VCO
× R × C
R
× P × N)
1
1
P = prescaler
N = programmable divider
I
= pump current
p
K
= tuner slope
VCO
R, C
= loop filter
1
Example for channel 47:
P = 8, N = 11520, I
C
= 180 nF, ωR = 336 Hz, fr = 54 Hz, ξ = 0.67
1
Standard dimensioning:
Note: The high-impedance port outputs and CAS can be blocked against external noise with
a capacitor of 1 nF.
= 100 µA; K
p
C
= C
2
= 18.7 MHz/V, R = 22 kΩ,
VCO
1/5
Semiconductor Group 24
Page 25
Input Sensitivity
SDA 3302 Family
2
I
C Bus Noise Immunity
The sinusoidal noise pulses are applied via a coupling capacitance of 33 pF to SCL and SDA
inputs.
Semiconductor Group 25
Page 26
Package Outlines
Plastic-Package, P-DIP-18-5
(Plastic Dual In-Line Package)
SDA 3302 Family
Plastic-Package, P-DSO-20-1 (SMD)
(Plastic Dual Small Outline Package)
GPD05586
Semiconductor Group 26
GPS05094
Page 27
Plastic-Package, P-DSO-16-1 (SMD)
(Plastic Dual Small Outline Package)
SDA 3302 Family
GPS05119
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
SMD = Surface Mounted Device Dimensions in mm
Semiconductor Group 27
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