Datasheet SCN2681TC1A44 Datasheet (Philips)

INTEGRATED CIRCUITS

SCN2681T

Dual asynchronous receiver/transmitter
(DUART)

Product specification
Supersedes data of 1995 May 01
IC19 Data Handbook

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1998 Sep 04

Philips Semiconductors Product specification

SCN2681TDual asynchronous receiver/transmitter (DUART)

DESCRIPTION

The Philips Semiconductors SCN2681 Dual Universal
Asynchronous Receiver/Transmitter (DUART) is a single-chip
MOS-LSI communications device that provides two independent
full-duplex asynchronous receiver/transmitter channels in a single
package. The SCN2681T features a faster bus cycle time than the
standard SCN2681. The quick bus cycle eliminates or reduces the
need for wait states with fast CPUs and permits high throughput in
I/O intensive systems. Higher external clock rates may be used with
the transmitter, receiver and counter timer which in turn provide
greater versatility in baud rate generation. The SCN2681T
interfaces directly with microprocessors and may be used in a polled
or interrupt driven system.

The operating mode and data format of each channel can be
programmed independently. Additionally, each receiver and
transmitter can select its operating speed as one of eighteen fixed
baud rates, a 16X clock derived from a programmable counter/timer,
or an external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external
clock inputs. The ability to independently program the operating
speed of the receiver and transmitter make the DUART particularly
attractive for dual-speed channel applications such as clustered
terminal systems.

Each receiver is quadruple buffered to minimize the potential of
receiver over-run or to reduce interrupt overhead in interrupt driven
systems. In addition, a flow control capability is provided to disable
a remote DUART transmitter when the receiver buffer is full.

Also provided on the SCN2681T are a multipurpose 7-bit input port
and a multipurpose 8-bit output port. These can be used as general
purpose I/O ports or can be assigned specific functions (such as
clock inputs or status/interrupt outputs) under program control.

For a complete functional description and programming information
for the SCN2681T, refer to the SCN2681 product specification.

FEA TURES

•Fast bus cycle times reduce or eliminate CPU wait states

•Dual full-duplex asynchronous receiver/transmitters

•Quadruple buffered receiver data registers

•Programmable data format

– 5 to 8 data bits plus parity
– Odd, even, no parity or force parity
– 1, 1.5 or 2 stop bits programmable in 1/16-bit increments

•16-bit programmable Counter/Timer

•Programmable baud rate for each receiver and transmitter

selectable from:

– 22 fixed rates: 50 to 115.2k baud
– Non-standard rates to 115.2
– Non-standard user-defined rate derived from programmable

counter/timer

– External 1X or 16X clock

•Parity, framing, and overrun error detection

•False start bit detection

•Line break detection and generation

•Programmable channel mode

– Normal (full-duplex)
– Automatic echo
– Local loopback
– Remote loopback

•Multi-function programmable 16-bit counter/timer

•Multi-function 7-bit input port

– Can serve as clock or control inputs
– Change of state detection on four inputs
– 100kΩ typical pull-up resistors

•Multi-function 8-bit output port

– Individual bit set/reset capability
– Outputs can be programmed to be status/interrupt signals

•Versatile interrupt system

– Single interrupt output with eight maskable interrupting

conditions

– Output port can be configured to provide a total of up to six

separate wire-ORable interrupt outputs

•Maximum data transfer rates:

1X – 1MB/sec transmitter and receiver; 16X – 500kB/sec receiver
and 250kB/sec transmitter

•Automatic wake-up mode for multidrop applications

•Start-end break interrupt/status

•Detects break which originates in the middle of a character

•On-chip crystal oscillator

•Single +5V power supply

•Commercial and industrial temperature ranges available

ORDERING INFORMATION

DESCRIPTION VCC = +5V +10%, TA = 0°C to +70°C DWG #

40-Pin Plastic Dual In-Line Package (600mil-wide DIP) SCN2681TC1N40 SOT129-1
44-Pin Plastic Lead Chip Carrier (PLCC) SCN2681TC1A44 SOT187-2

NOTE: For a full register description and programming information see the SCN2681.

1998 Sep 04 853–1002 19970

2

Philips Semiconductors Product specification

SCN2681TDual asynchronous receiver/transmitter (DUART)

PIN CONFIGURATIONS

INDEX

A0

IP3

A1

IP1

A2

A3

IP0

WRN

RDN
RxDB
TxDB

OP1

OP3

OP5

OP7

D1
D3
D5

D7

GND

1
2
3
4
5

6
7
8
9

10

DIP

11
12

13

14
15
16
17
18

19

40
39
38
37
36

35
34
33
32
31
30
29

28

27
26
25
24
23

22
2120

NOTE:

Refer to SCN2681 for functional description.

V

CC

IP4
IP5
IP6
IP2

CEN
RESET
X2
X1/CLK
RxDA
TxDA
OP0

OP2

OP4
OP6
D0
D2
D4

D6
INTRN

CORNER

Figure 1. Pin Configurations

6

7

17

18

PIN/FUNCTION PIN/FUNCTION

1NC 23NC
2 A0 24 INTRN
3 IP3 25 D6
4A1 26D4
5 IP1 27 D2
6A2 28D0
7 A3 29 OP6
8 IP0 30 OP4
9 WRN 31 OP2
10 RDN 32 OP0
11 RxDB 33 TxDA
12 NC 34 NC
13 TxDB 35 RxDA
14 OP1 36 X1/CLK
15 OP3 37 X2
16 OP5 38 RESET
17 OP7 39 CEN
18 D1 40 IP2
19 D3 41 IP6
20 D5 42 IP5
21 D7 43 IP4

22 GND 44 V

1

PLCC

TOP VIEW

40

28

CC

SD00098

39

29

1998 Sep 04

3

Philips Semiconductors Product specification

SCN2681TDual asynchronous receiver/transmitter (DUART)

BLOCK DIAGRAM

D0–D7

RDN

WRN

CEN

A0–A3

RESET

INTRN

8

BUS BUFFER

OPERATION CONTROL

ADDRESS

4

DECODE

R/W CONTROL

INTERRUPT CONTROL

IMR
ISR

TIMING

BAUD RATE

GENERATOR

CLOCK

SELECTORS

CONTROL

TIMING

INTERNAL DATABUS

CHANNEL A

TRANSMIT

HOLDING REG

TRANSMIT

SHIFT REGISTER

RECEIVE

HOLDING REG (3)

RECEIVE

SHIFT REGISTER

MRA1, 2

CRA
SRA

CHANNEL B
(AS ABOVE)

INPUT PORT

CHANGE OF

STATE

DETECTORS (4)

IPCR
ACR

TxDA

RxDA

TxDB

RxDB

7

IP0-IP6

X1/CLK

COUNTER/

TIMER

X2

XTAL OSC

CSRA

CSRB

ACR

U

CTLR
CTLR

OUTPUT PORT

FUNCTION

SELECT LOGIC

OPCR

OPR

8

OP0-OP7

V

CC

GND

SD00099

Figure 2. Block Diagram

1998 Sep 04

4

Philips Semiconductors Product specification

SCN2681TDual asynchronous receiver/transmitter (DUART)

PIN DESCRIPTION

MNEMONIC TYPE NAME AND FUNCTION

D0–D7 I/O Data Bus: Bidirectional three-state data bus used to transfer commands, data and status between the DUART and

CEN I Chip Enable: Active low input signal. When low, data transfers between the CPU and the DUART are enabled on

WRN I Write Strobe: When low and CEN is also low, the contents of the data bus is loaded into the addressed register. The

RDN I Read Strobe: When low and CEN is also low , causes the contents of the addressed register to be presented on the

A0–A3 I Address Inputs: Select the DUART internal registers and ports for read/write operations.

RESET I Reset: A high level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OP0–OP7 in the high state,

INTRN O Interrupt Request: Active-low, open-drain output which signals the CPU that one or more of the eight maskable

X1/CLK I Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency (nominally

X2 I Crystal 2: Crystal connection. See Figure 7. If a crystal is not used it is best to keep this pin not connected although it

RxDA I Channel A Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is high, ‘space’ is low.
RxDB I Channel B Receiver Serial Data Input: The least significant bit is received first. ‘Mark’ is high, ‘space’ is low.
TxDA O Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the ‘mark’

TxDB O Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the

OP0 O Output 0: General purpose output, or channel A request to send (RTSAN, active-low). Can be deactivated

OP1 O Output 1: General purpose output, or channel B request to send (RTSBN, active-low). Can be deactivated

OP2 O Output 2: General purpose output, or channel A transmitter 1X or 16X clock output, or channel A receiver 1X clock output.
OP3 O Output 3: General purpose output, or open-drain, active-low counter/timer output, or channel B transmitter 1X clock

OP4 O Output 4: General purpose output, or channel A open-drain, active-low, RxRDYA/FFULLA output.
OP5 O Output 5: General purpose output, or channel B open-drain, active-low, RxRDYB/FFULLB output.
OP6 O Output 6: General purpose output, or channel A open-drain, active-low, TxRDYA output.
OP7 O Output 7: General purpose output, or channel B open-drain, active-low TxRDYB output.

IP0 I Input 0: General purpose input, or channel A clear to send active-low input (CTSAN). Pin has an internal VCC pull-up

IP1 I Input 1: General purpose input, or channel B clear to send active-low input (CTSBN). Pin has an internal VCC pull-up

IP2 I Input 2: General purpose input, or counter/timer external clock input. Pin has an internal VCC pull-up device supplying

IP3 I Input 3: General purpose input, or channel A transmitter external clock input (TxCA). When the external clock is used

IP4 I Input 4: General purpose input, or channel A receiver external clock input (RxCA). When the external clock is used by

IP5 I Input 5: General purpose input, or channel B transmitter external clock input (TxCB). When the external clock is used

IP6 I Input 6: General purpose input, or channel B receiver external clock input (RxCB). When the external clock is used by

V

CC

GND I Ground

the CPU. D0 is the least significant bit.

D0–D7 as controlled by the WRN, RDN, and A0–A3 inputs. When CEN is high, the DUART places the D0–D7 lines in
the three-state condition.

transfer occurs on the rising edge of the signal.

data bus. The read cycle begins on the falling edge of RDN.

stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark
(high) state. Clears Test modes, sets MR pointer to MR1.

interrupting conditions are true.

3.6864 MHz) must be supplied at all times. For crystal connections see Figure 7, Clock Timing.

is permissible to ground it.

condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is high, ‘space’ is low.

‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode. ‘Mark’ is high,
‘space’ is low.

automatically on receive or transmit.

automatically on receive or transmit.

output, or channel B receiver 1X clock output.

device supplying 1 to 4 A of current.

device supplying 1 to 4 A of current.

1 to 4 A of current.

by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC pull-up
device supplying 1 to 4 A of current.

the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device
supplying 1 to 4 A of current.

by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an internal VCC pull-up
device supplying 1 to 4 A of current.

the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal VCC pull-up device
supplying 1 to 4 A of current.

I Power Supply: +5V supply input.

1998 Sep 04

5

Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

V

µA

SCN2681TDual asynchronous receiver/transmitter (DUART)

ABSOLUTE MAXIMUM RATINGS

SYMBOL

T
T

A

STG

Operating ambient temperature range
Storage temperature range -65 to +150 °C
All voltages with respect to GND

1

PARAMETER RATING UNIT

2

3

0 to +70 °C

-0.5 to +6.0 V

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.

2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.

3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

DC ELECTRICAL CHARACTERISTICS

1, 2, 3

LIMITS

Min Typ Max

V
V
V

V
V

I

IL

I

LL

I

X1L

I

X1H

I

X2L

I

X2H

I

OC

I

CC

IL
IH
IH

OL
OH

Input low voltage 0.8
Input high voltage (except X1/CLK) 2.0 V
Input high voltage (X1/CLK) 3.5

Output low voltage IOL = 2.4mA 0.4
Output high voltage (except o.c. outputs)

Input leakage current VIN = 0 to V
Data bus 3-state leakage current VO = 0.4 to V

X1/CLK low input current VIN = 0, X2 grounded
X1/CLK high input current VIN = VCC, X2 = grounded

4

IOH = -400µA 2.4

CC

CC

VIN = 0, X2 floated

VIN = VCC, X2 floated

-10 10

-10 10

-4

-3

-1
0

-2

-1.5

0.2

3.5

10

0

mA

0

mA

1

mA

mA
X2 low input current VIN = 0, X1/CLK floated -100 -30 0 µA
X2 high input current VIN = VCC, X1/CLK floated 0 +30 100 µA

Open-collector output leakage current VO = 0.4 to V
Power supply current

5

CC

-10 10 µA
150 mA

NOTES:

1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V
supply range.

CC

2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a
transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.0V . All time measurements are referenced at inpu t voltages
of 0.8V and 2.0V and output voltages of 0.8V and 2.0V as appropriate.

3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.

4. Test conditions for outputs: C

5. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle

= 150pF, except interrupt outputs. T est conditions for interrupt outputs: CL = 50pF, RL = 2.7kΩ to VCC.

L

and the signal negated first terminates the cycle.

AC ELECTRICAL CHARACTERISTICS

RESET

1, 2, 3, 4

t

RES

SD00028

Figure 3. Reset Timing

NOTES:

1. Parameters are valid over specified temperature range. See Ordering information table for applicable operating temperature range and V
supply range.

2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.4V and 2.4V with a
transition time of 20ns maximum. For X1/CLK this swing is between 0.4V and 4.0V . All time measurements are referenced at inpu t voltages
of 0.8V and 2.0V and output voltages of 0.8V and 2.0V as appropriate.

3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.

4. Test conditions for outputs: C

1998 Sep 04

= 150pF, except interrupt outputs. T est conditions for interrupt outputs: CL = 50pF, RL = 2.7kΩ to VCC.

L

6

CC

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

1

SYMBOL

PARAMETER

1

UNIT

SCN2681TDual asynchronous receiver/transmitter (DUART)

LIMITS

Min Max

t

RES

A0–A3

Reset pulse width 1.0 µs

CEN

(READ)

RDN

D0–D7

(READ)

CEN

(WRITE)

WRN

D0–D7

(WRITE)

t

AVEL

t

RLDA

FLOAT FLOATVALIDINVALID

t

ELAX

t

RLDV

t

WLWH

t

RLRH

t

DVWH

VALID

t

WHDI

t

t

RHDI

t

EHEL

RHDF

t

EHEL

SD00100

Figure 4. Bus Timing

LIMITS

Min Max

t

AVEL

t

ELAX

t

RLRH

t

EHEL

t

RLDA

t

RLDV

t

RHDI

t

RHDF

t

WLWH

t

DVWH

t

WHDI

A0–A3 setup to RDN and CEN, or WRN and CEN low 0 ns
RDN and CEN, or WRN and CEN low to A0–A3 invalid 100 ns
RDN and CEN low to RDN or CEN high 120 ns
CEN high to CEN low

2, 3

110 ns
CEN and RDN low to data outputs active 15 ns
CEN and RDN low to data valid 100 ns
CEN or RDN high to data invalid 10 ns
CEN or RDN high to data outputs floating 65 ns
WRN and CEN low to WRN or CEN high 75 ns
Data input valid to WRN or CEN high 35 ns
WRN or CEN high to data invalid 15 ns

NOTES:

1. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.

2. If CEN is used as the ‘strobing’ input, the parameter defines the minimum high times between one CEN and the next. The RDN signal must
be negated for t
RDN input even if the CEN is used as the strobing signal for bus operations.

to guarantee that any status register changes are valid. As a consequence, this minimum time must be met for the

EHEL

3. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.

1998 Sep 04

7

Philips Semiconductors Product specification

SYMBOL

PARAMETER

1

UNIT

SYMBOL

PARAMETER

UNIT

SCN2681TDual asynchronous receiver/transmitter (DUART)

RDN

t

PH

t

PD

NEW DATA

SD00101

IP0–IP6

WRN

OP0–OP7

t

PS

(a) INPUT PINS

OLD DATA

(b) OUTPUT PINS

Figure 5. Port Timing

LIMITS

Min Max

t

PS

t

PH

t

PD

Port input setup time before RDN low 0 ns
Port input hold time after RDN high 0 ns
Port output valid after WRN high 200 ns

NOTE:

1. For bus operations, CEN and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle
and the signal negated first terminates the cycle.

V

WRN

M

t

INTERRUPT

NOTES:

1. INTRN or OP3-OP7 when used as interrupt outputs.

2. The test for open drain outputs is intended to guarantee switching of the output transistor. Measurement of this response is referenced from the midpoint of the switching
, to a point 0.5V above VOL. This point represents noise margin that assures true switching has occurred. Beyond this level, the effects of external circuitry and

signal, V

M

test environment are pronounced and can greatly affect the resultant measurement.

1

OUTPUT

IR

V

+0.5V

OL

V

OL

SD00102

Figure 6. Interrupt Timing

LIMITS

Min Max

INTRN (or OP3–OP7 when used as interrupts) negated from:

Read RHR (RxRDY/FFULL interrupt) 200 ns
Write THR (TxRDY interrupt) 200 ns

t

IR

Reset command (delta break interrupt) 200 ns
Stop C/T command (counter interrupt) 200 ns
Read IPCR (input port change interrupt) 200 ns
Write IMR (clear of interrupt mask bit) 200 ns

1998 Sep 04

8

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

SYMBOL

PARAMETER

UNIT

SCN2681TDual asynchronous receiver/transmitter (DUART)

t

CLK

t

CTC

t

Rx

t

X1/CLK
CTCLK

RxC
TxC

When using an external clock it is preferred to drive X2 and leave X1 open.
X2 is the input to the internal driver, while X1 is the output.
R1 is only required if U1 will not drive to X2 high level.
Previous specifications indicated X2 should be grounded and X1
should be driven. This is still acceptable. It is electrically easier to drive
the amplifier input than to overdrive its output.

Tx

t

CLK

t

CTC

t

Rx

t

Tx

DRIVING FROM

EXTERNAL SOURCE

U1

Figure 7. Clock Timing

X1/CLK high or low time 90 ns

t

CLK

f

CLK

t

CTC

f

CTC

t

RX

f

RX

t

TX

f

TX

X1/CLK frequency 2 4 MHz
CTCLK (IP2) high or low time 55 ns
CTCLK (IP2) frequency

1

RxC high or low time 55 ns
RxC frequency (16X)

(1X)

1

1

TxC high or low time 110 ns
TxC frequency (16X)

(1X)

1

1

NOTE:

1. Minimum frequencies are not tested but are guaranteed by design.

OPEN

1KΩ

+5V

1K

74LS04

SCN2681

+5V

CLOCK
TO OTHER
CHIPS

TO THE REST
OF THE DUART
CIRCUITS

SD00091

R1: 100K - 1Meg (See design note)
C1 = C2: 0-5pF + (STRAY < 5pF)

X1

X1

R1

X2

C1

R2

C2

X2

3.6864MHz

CRYSTAL SERIES RESISTANCE3 SHOULD BE LESS THAN 180Ω

R2 = 50kΩ to 150kΩ

LIMITS

Min Typ Max

0 8 MHz

0
0

0
0

3.6864 8
1

4
1

MHz

MHz
MHz

MHz

t

TXD

t

TCS

1998 Sep 04

1 BIT TIME

(1 OR 16 CLOCKS)

TxC

(INPUT)

t

TXD

TxD

t

TxC

(1X OUTPUT)

TCS

SD00103

Figure 8. Transmit

LIMITS

Min Max

TxD output delay from TxC external clock input on IP pin 300 ns
Output delay from TxC low at OP pin to TxD data output 0 100 ns

9

Philips Semiconductors Product specification

SYMBOL

PARAMETER

UNIT

SCN2681TDual asynchronous receiver/transmitter (DUART)

RxC

(1X INPUT)

t

RXS

t

RXH

TxD D1 D2 D3 D4 D6BREAK

TRANSMITTER

ENABLED

TxRDY

(SR2)

WRN

CTSN

(IP0)

RxD

t

RXS

t

RXH

SD00104

Figure 9. Receive

LIMITS

Min Max

RxD data setup time before RxC high at external clock input on IP pin 200 ns
RxD data hold time after RxC high at external clock input on IP pin 25 ns

D1 D2 D3 D4 D6START

1

BREAK

STOP

BREAK

D5 WILL

NOT BE

TRANSMITTED

2

RTSN

(OP0)

NOTES:

1. Timing shown for MR2(4) = 1.

2. Timing shown for MR2(5) = 1.

OPR(0) = 1 OPR(0) = 1

SD00094

Figure 10. Transmitter Timing

1998 Sep 04

10

Philips Semiconductors Product specification

SCN2681TDual asynchronous receiver/transmitter (DUART)

RxD

RECEIVER

ENABLED

RxRDY

(SR0)

FFULL

(SR1)

RxRDY/

FFULL

2

(OP5)

RDN

OVERRUN

(SR4)

1

RTS

(OP0)

OPR(0) = 1

NOTES:

1. Timing shown for MR1(7) = 1.

2. Shown for OPCR(4) = 1 and MR1(6) = 0.

D1 D2 D3 D4 D5 D6 D7 D8

D6, D7, D8 WILL BE LOST

SD

D1 D2 D3 D4

S = STATUS
D = DATA

D5 WILL
BE LOST

SD

SD SD

RESET BY
COMMAND

SD00105

Figure 11. Receiver T iming

TxD

TRANSMITTER

ENABLED

TxRDY

(SR2)

WRN

RxD

RECEIVER

ENABLED

RxRDY

(SR0)

RDN/WRN

MASTER STATION

MR1(4–3) = 11

MR1(2) = 1

PERIPHERAL STATION

MR1(4–3) = 11

BIT 9

ADD#1

1

ADD#1MR1(2) = 0D0 MR1(2) = 1 ADD#2

BIT 9

0

BIT 9

ADD#1 1

D0 0

ADD#1

BIT 9

D0 0

BIT 9

SD

D0 ADD#2

S = STATUS
D = DATA

Figure 12. Wake-Up Mode

ADD#2 1

ADD#2 1

BIT 9

BIT 9

BIT 9

0

SD

SD00106

1998 Sep 04

11

Philips Semiconductors Product specification

SCN2681TDual asynchronous receiver/transmitter (DUART)

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

1998 Sep 04

12

Philips Semiconductors Product specification

SCN2681TDual asynchronous receiver/transmitter (DUART)

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

1998 Sep 04

13

Philips Semiconductors Product specification

SCN2681TDual asynchronous receiver/transmitter (DUART)

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

Date of release: 09-98

Document order number: 9397 750 04363

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1998 Sep 04

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