Page 1
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1
1995 May 1 853-0307 15179
DESCRIPTION
The Philips Semiconductors SCN26562 Dual Universal Serial
Communications Controller (DUSCC) is a single-chip MOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SCN26562 interfaces to synchronous
bus MPUs and is capable of program-polled, interrupt driven,
block-move or DMA data transfers.
The operating mode and data format of each channel can be
programmed independently. Each channel consists of a receiver, a
transmitter, a 16-bit multi-function counter/timer, a digital
phase-locked loop (DPLL), a parity/CRC generator and checker, and
associated control circuits. The two channels share a common bit
rate generator (BRG), operating directly from a crystal or an external
clock, which provides 16 common bit rates simultaneously. The
operating rate for the receiver and transmitter of each channel can
be independently selected from the BRG, the DPLL, the
counter/timer, or from an external 1X or 16X clock, making the
DUSCC well suited for dual-speed channel applications. Data rates
up to 4Mbits per second are supported.
The transmitter and receiver each contain a four-deep FIFO with
appended transmitter command and receiver status bits and a shift
register. This permits reading and writing of up to four characters at
a time, minimizing the potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA overhead. In addition, a
flow control capability is provided to disable a remote transmitter
when the FIFO of the local receiving device is full.
Two modem control inputs (DCD and CTS) and three modem
control outputs (RTS and two general purpose) are provided.
Because the modem control inputs and outputs are general purpose
in nature, they can be optionally programmed for other functions.
This document contains the electrical specifications for the
SCN26562. See SCN26562/SCN68562 User’s Guide for complete
functional description.
FEATURES
General Features
•Dual full-duplex synchronous/asynchronous receiver and
transmitter
•Multiprotocol operation
– BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
etc.
– COP: BISYNC, DDCMP
– ASYNC: 5–8 bits plus optional parity
•Four character receiver and transmitter FIFOs
•0 to 4Mbit/sec data rate
•Programmable bit rate for each receiver and transmitter selectable
from:
– 16 fixed rates: 50 to 38.4k baud
– One user-defined rate derived from programmable
counter/timer
– External 1X or 16X clock
– Digital phase-locked loop
•Parity and FCS (frame check sequence LRC or CRC) generation
and checking
•Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
•Programmable channel mode: full- and half-duplex, auto-echo, or
local loopback
•Programmable data transfer mode: polled, interrupt, DMA, wait
•DMA interface
– Single- or dual-address dual transfers
– Half- or full-duplex operation
– Automatic frame termination on counter/timer terminal count or
DMA EOPN input
•Interrupt capabilities
– Vector output (fixed or modified by status)
– Programmable internal priorities
– Maskable interrupt conditions
•Multi-function programmable 16-bit counter/timer
– Bit rate generator
– Event counter
– Count received or transmitted characters
– Delay generator
– Automatic bit length measurement
•Modem controls
– RTS, CTS, DCD, and up to four general purpose pins per
channel
– CTS and DCD programmable auto-enables for Tx and Rx
– Programmable interrupt on change of CTS or DCD
•On-chip oscillator for crystal
•TTL compatible
•Single +5V power supply
Asynchronous Mode Features
•Character length: 5 to 8 bits
•Odd or even parity, no parity, or force parity
•Up to two stop bits programmable in 1/16-bit increments
•1X or 16X and Tx clock factors
•Parity, overrun, and framing error detection
•False start bit detection
•Start bit search 1/2-bit time after framing error detection
•Break generation with handshake for counting break characters
•Detection of start and end of received break
•Character compare with optional interrupt on match
•Transmits up to 4Mbit/sec data rate Receives up to 2Mbit/sec data
rate
Page 2
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
2
Character-Oriented Protocol Features
•Character length: 5 to 8 bits
•Odd or even parity, no parity, or force parity
•LRC or CRC generation and checking
•Optional opening PAD transmission
•One or two SYN characters
•External sync capability
•SYN detection and optional stripping
•SYN or MARK line-fill on underrun
•Idle in MARK or SYNs
•Parity, FCS, overrun, and underrun error detection
BISYNC Features
•EBCDIC or ASCII header, text and control messages
•SYN, DLE stripping
•EOM (end of message) detection and transmission
•Auto transparent mode switching
•Auto hunt after receipt of EOM sequence (with closing PAD check
after EOT or NAK)
•Control character sequence detection for both transparent and
normal text
Bit-Oriented Protocol Features
•Character length: 5 to 8 bits
•Detection and transmission of residual character: 0–7 bits
•Automatic switch to programmed character length for I field
•Zero insertion and detection
•Optional opening PAD transmission
•Detection and generation of FLAG, ABORT, and IDLE bit patterns
•Detection and generation of shared (single) FLAG between
frames
•Detection of overlapping (shared zero) FLAGs
•ABORT, ABORT-FLAGs, or FCS FLAGs line-fill on underrun
•Idle in MARK or FLAGs
•Secondary address recognition including group and global
address
•Single- or dual-octet secondary address
•Extended address and control fields
•Short frame rejection for receiver
•Detection and notification of received end of message
•CRC generation and checking
•SDLC loop mode capability
ORDERING INFORMATION
VCC = +5V +5%, TA = 0°C to +70°C
DESCRIPTION
Serial Data Rate =
4Mbps Maximum
DWG #
48-Pin Plastic Dual In-Line Package (DIP) SCN26562C4N48 SOT240-1
52-Pin Plastic Leaded Chip Carrier (PLCC) Package SCN26562C4A52 SOT238-3
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL PARAMETER RATING UNIT
T
A
Operating ambient temperature
2
0 to +70 °C
T
STG
Storage temperature -65 to +150 °C
V
CC
Voltage from VCC to GND
3
–0.5 to +7.0 V
V
S
Voltage from any pin to ground
3
–0.5 to VCC +0.5 V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature and thermal
resistance of 36°C/W junction to ambient for ceramic DIP, 40°C/W for plastic DIP, and 42°C/W for PLCC.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
Page 3
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
3
PIN CONFIGURATIONS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
28
27
26
25
21
22
23
24
IACKN
A3
A2
A1
RTxDAKBN/
IRQN
RDYN
RTSBN/
TRxCB
RTxCB
DCDBN/
TxDAKBN/
RTxDRQBN/
TxDRQBN/
CTSBN/LCBN
D7
D6
D5
D4
RDN
RESETN
GND
CEN
EOPN
D3
D2
D1
D0
CTSAN/LCAN
TxDRQAN/
RTxDRQAN/
TxDAKAN/
TxDA
DCDAN/
RTxCA
TRxCA
RTSAN/
X2
X1/CLK
RTxDAKAN/
A6
A5
A4
V
CC
N PACKAGE
GPI1BN
SYNOUTBN
SYNIBN
RxDB
TxDB
GPI2BN
GPO1BN
GPO2BN/RTSBN
WRN
GPO2AN/RTSAN
GPO1AN
GPI2AN
RxDA
SYNIAN
SYNOUTAN
GPI1AN
DIP
PIN FUNCTION PIN FUNCTION
1 IACKN 27 CEN
2 A3 28 WRN
3 A2 29 EOPN
4 A1 30 D3
5 RTxDAKBN/ 31 D2
GPI1BN 32 D1
6 IRQN 33 D0
7 NC 34 NC
8 RDYN 35 CTSAN/LCAN
9 RTSBN/ 36 TxDRQAN/
SYNOUTBN GPO2AN/RTSAN
10 TRxCB 37 RTxDRQAN/
11 RTxCB GPO1AN
12 DCDBN/ 38 TxDAKAN/
SYNIBN GPI2AN
13 NC 39 TxDA
14 RxDB 40 RxDA
15 TxDB 41 NC
16 TxDAKBN/ 42 DCDAN/
GPI2BN SYNIAN
17 RTxDRQBN/ 43 RTxCA
GPO1BN 44 TRxCA
18 TxDRQBN/ 45 RTSAN/
GPO2BN/RTSBN SYNOUTAN
19 CTSBN/LCBN 46 X2
20 D7 47 X1/CLK
21 D6 48 RTxDAKAN/
22 D5 GPI1AN
23 D4 49 A6
24 RDN 50 A5
25 RESETN 51 A4
26 GND 52 V
CC
1
46
20
33
47
34
21
8
PLCC
7
TOP VIEW
INDEX
CORNER
A PACKAGE
SD00203
Figure 1. Pin Configurations
Page 4
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
4
BLOCK DIAGRAM
D0–D7
RDYN
RDN
A1–A6
CEN
RESETN
BUS
BUFFER
CHANNEL
MODE AND
TIMING A/B
DPLL CLK
MUX A/B
DPLLA/B
CTCRA/B
CTPRHA/B
CTPRLA/B
RxD A/B
TxD A/B
CONTROL
INTERNAL BUS
BRG
COUNTER
TIMER A/B
C/T CLK
MUX A/B
CTHA/B
CTLA/B
TRANS CLK
MUX
TRANSMIT
A/B
TPRA/B
TTRA/B
TX SHIFT
REG
TRANSMIT
4 DEEP
FIFO
CRC
GENERATOR
SPEC CHAR
GEN LOGIC
RCVR CLK
MUX
RCVR
SHIFT REG
RECEIVER
4 DEEP
FIFO
CRC
ACCUM
RECEIVER
A/B
RPRA/B
RTRA/B
S1RA/B
S2RA/B
BISYNC
COMPARE
LOGIC
ADDRESS
DECODE
DMA
CONTROL
INTERFACE/
OPERATION
CONTROL
CCRA/B
PCRA/B
RSRA/B
TRSRA/B
ICTSRA/B
R/W
DECODE
GSR
CMR1A/B
CMR2A/B
OMRA/B
MPU
INTERFACE
WRN
RTxDRQAN/GPO1AN
DMA
INTERFACE
RTxDRQBN/GPO1BN
TxDRQAN/GPO2AN
TxDRQBN/GPO2BN
RTxDAKAN/GPI1AN
RTxDAKBN/GPI1BN
TxDAKAN/GPI2AN
TxDAKBN/GPI2BN
EOPN
TRxCA/B
SPECIAL
FUNCTION
PINS
RTxCA/B
CTSAN/LCAN
CTSBN/LCBN
DCDBN/SYNIBN
DCDAN/SYNIAN
RTSBN/SYNOUTBN
RTSAN/SYNOUTAN
INTERRUPT
CONTROL
ICRA/B
IERA/B
IVR
IVRM
IRQN
IACKN
X1/CLK
X2
OSCILLATOR
DUSCC
LOGIC
SD00204
Figure 2. Block Diagram
Page 5
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
5
PIN DESCRIPTION
MNEMONIC PIN NO. TYPE NAME AND FUNCTION
DIP PLCC
A1–A6 4–2,
47–45
4–2,
51–49
I Address lines.
D0–D7 31–28,
21–18
33–30,
23–20
I/O Bidirectional data bus.
RDN 22 24 I Read strobe.
WRN 26 28 I Write strobe.
CEN 25 27 I Chip select.
RDYN 7 8 O Ready.
IRQN 6 6 O Interrupt request.
IACKN 1 1 I Interrupt acknowledge.
X1/CLK 43 47 I Crystal 1 or external clock.
X2 42 46 I Crystal 2.
RESETN 23 25 I Master reset.
RxDA, RxDB 37, 12 40, 14 I Channel A (B) receiver serial data.
TxDA, TxDB 36, 13 39, 15 O Channel A (B) transmitter serial data.
RTxCA,
RTxCB
39, 10 43, 11 I/O Channel A (B) receiver/transmitter clock.
TRxCA,
TRxCB
40, 9 44, 10 I/O Channel A (B) transmitter/receiver clock.
CTSA/BN,
LCA/BN
32, 17 35, 19 I/O Channel A (B) clear-to-send input or loop control output.
DCDA/BN,
SYNIA/BN
38, 11 42, 12 I Channel A (B) data carrier detected or external sync.
RTxDRQA/BN,
GPO1A/BN
34, 15 37, 17 O Channel A (B) receiver/transmitter DMA service request or general purpose output.
TxDRQA/BN,
GPO2A/BN,
RTSA/BN
33, 16 36, 18 O Channel A (B) transmitter DMA service request, general purpose output or request-to-send.
RTxDAKA/BN,
GPI1A/BN
44, 5 48, 5 I Channel A (B) receiver/transmitter DMA acknowledge or general purpose input 1.
TxDAKA/BN,
GPI2A/BN
35, 14 38, 16 I Channel A (B) transmitter DMA acknowledge or general purpose input 2.
EOPN 27 29 I/O DMA transfer complete.
RTSA/BN,
SYNOUTA/BN
41, 8 45, 9 O Channel A (B) request-to-send or Sync detect.
V
CC
48 52 I Power input.
GND 24 26 I Signal and power ground.
Page 6
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
6
DC ELECTRICAL CHARACTERISTICS
1, 3
T
A
= 0°C to +70°C, VCC = 5.0V +5%
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min Typ Max
UNIT
V
IL
V
IH
Input low voltage:
All except X1/CLK
X1/CLK
Input high voltage:
All except X1/CLK
X1/CLK
2.0
2.4
0.8
0.4
V
CC
V
V
V
V
V
OL
V
OH
Output low voltage:
All except IRQN
IRQN
Output high voltage:
(Except open drain outputs)
IOL = 5.3mA
I
OL
= 8.8mA
IOH = –400µA 2.4
0.5
0.5
V
V
V
I
ILX1
I
IHX1
X1/CLK input low current
3
X1/CLK input high current
3
VIN = 0, X2 = GND
V
IN
= VCC, X2 = GND
–5.5
0.0
1.0
mA
mA
I
ILX2
I
IHX2
X2 input low current
3
X2 input high current
3
VIN = 0, X1 = open
V
IN
= VCC, X1 = open
–100
100
µA
µA
I
IL
Input low current
RESETN, TxDAKN, RxDAKN
VIN = 0 –40 µA
I
I
Input leakage current VIN = 0 to V
CC
–5 5 µA
I
OZH
I
OZL
Output off current high, 3-State data bus
Output off current low, 3-State data bus
VIN = V
CC
VIN = 0 –5
5
µA
µA
I
ODL
I
ODH
Open drain output low current in off
state: EOPN
IRQN, RDYN
Open drain output high current in off
state: EOPN, IRQN, RDYN
VIN = 0
V
IN
= V
CC
–120
–5
–25
5
µA
µA
µA
I
CC
Power supply current VO = 0 to V
CC
275 mA
C
IN
C
OUT
C
I/O
Input capacitance
2
Output capacitance
2
Input/output capacitance
2
VCC = GND = 0
V
CC
= GND = 0
V
CC
= GND = 0
10
15
20
pF
pF
pF
NOTES:
1. Parameters are valid over specified temperature range.
2. These values were not explicitly tested; they are guaranteed by design and characterization data.
3. X1/CLK and X2 are not tested with a crystal installed.
AC ELECTRICAL CHARACTERISTICS
1, 2, 3, 4
T
A
= 0°C to +70°C, VCC = 5V +5%
LIMITS
SYMBOL
PARAMETER
SCN26562C4 SCN26562C2
UNIT
Min Max Min Max
t
RELREH
RESETN low to RESETN high 1.2 1.2 µs
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.8V and 2.0V with a
transition time of 20ns maximum. For X1/CLK, this swing is between 0.4V and 2.4V . All time measurements are referenced at input voltages
of 0.4V and 2.4V and output voltages of 1.2V and 2.0V , as appropriate.
3. See Figure 17 for test conditions for outputs.
4. Tests for open drain outputs are intended to guarantee switching of the output transistor. Measurement of this response is referenced from
midpoint of the switching signal to a point 0.2V above the actual output signal level. This point represents noise margin that assures true
switching has occurred.
t
RELREH
RESETN
SD00205
Figure 3. Reset Timing
Page 7
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
7
AC ELECTRICAL CHARACTERISTICS (Continued)
A6–A1
t
ADVRDL
CEN
t
CEHCEL
t
CELRDL
RDN
t
RDHCEH
t
RDLADI
t
RDLRDH
t
RDHRDL
D0–D7
t
RDLDDV
t
RDHDDF
t
RDHDDI
RDYN
t
RDLRYL
t
RYZDDV
1
NOTES:
1. Wait on Rx. Receiver FIFO empty.
2. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN and RDN
(also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the
cycle.
SD00206
Figure 4. Read Cycle
LIMITS
SYMBOL
PARAMETER
SCN26562C4 SCN26562C2
UNIT
Min Max Min Max
t
ADVRDL
t
CELRDL
t
RDLADI
t
RDLRYL
t
RDLDDV
t
RDLRDH
t
RYZDDV
t
RDHCEH
t
CEHCEL
t
RDHDDI
t
RDHRDL
t
RDHDDF
Address valid to RDN low
CEN low to RDN low
RDN low to address invalid
RDN low to RDYN low
RDN low to read data valid
RDN low to RDN high
RDYN high impedance to read data valid
RDN high to CEN high
CEN high to CEN low
RDN high to read data invalid
RDN high to RDN low
RDN high to data bus floating
10
0
150
300
0
160
10
160
275
280
100
75
10
0
150
310
0
170
10
170
275
300
100
75
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 8
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
8
AC ELECTRICAL CHARACTERISTICS (Continued)
A6–A1
t
ADVWRL
CEN
t
CEHCEL
t
CELWRL
WRN
t
WRHCEH
t
WRLADI
t
WRLWRH
t
WRHWRL
D0–D7
t
WDVWRH
t
WRHWDI
RDYN
t
WRLRYL
1
NOTES:
1. Wait on Tx. Transmitter FIFO full.
2. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN and RDN
(also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated first terminates the
cycle.
SD00207
Figure 5. Write Cycle
LIMITS
SYMBOL
PARAMETER
SCN26562C4 SCN26562C2
UNIT
Min Max Min Max
t
ADVWRL
t
CELWRL
t
WRLRYL
t
WRHCEH
t
WRLWRH
t
WDVWRH
t
CEHCEL
t
WRLADI
t
WRHWRL
t
WRHWDI
Address valid to WRN low
CEN low to WRN low
WRN low to READY low
WRN high to CEN high
WRN low to WRN high
Write data valid to WRN high
CEN high to CEN low
WRN low to address invalid
WRN high to WRN low
WRN high to write data invalid
10
0
0
300
100
160
150
160
10
275
10
0
0
310
100
170
150
170
10
275
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 9
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
9
AC ELECTRICAL CHARACTERISTICS (Continued)
IRQN
Cleared
through
software
INTERRUPT REQUEST LOCKED
A
SERVICE
ROUTINE
VECTOR SETTLING
IACKN
B
C
VECTOR
LOCKED
A
A
t
IALDDV
t
IAHDDI
t
IAHDDF
C
D7–D0
NOTES:
ICR[5:4] = 01 or 10 (mode 1 or mode 2)
Call instruction (mode 2)
ICR[5:4] = 11 (mode 3)
A
B
C
SD00208
Figure 6. Interrupt Acknowledge Cycle
LIMITS
SYMBOL
PARAMETER
SCN26562C4 SCN26562C2
UNIT
Min Max Min Max
t
IALDDV
t
IAHDDF
t
IAHDDI
IACKN low to data bus valid
IACKN high to data bus floating
IACKN high to data bus invalid
10
280
150
10
280
150
ns
ns
ns
CEN
t
WRHGOV
WRN
GPO1_N
AND/OR
GPO2_N
OLD DATA NEW DATA
SD00209
Figure 7. Output Port Timing
LIMITS
SYMBOL
PARAMETER
SCN26562C4 SCN26562C2
UNIT
Min Max Min Max
t
WRHGOV
WRN high to GPO output data valid 300 300 ns
Page 10
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
10
AC ELECTRICAL CHARACTERISTICS (Continued)
CEN
t
RDLGII
RDN
GPI1N
AND/OR
GPI2N
t
GIVRDL
SD00210
Figure 8. Input Port Timing
LIMITS
SYMBOL
PARAMETER
SCN26562C4 SCN26562C2
UNIT
Min Max Min Max
t
GIVRDL
t
RDLGII
GPI input valid to RDN low
RDN low to GPI input invalid
20
100
20
100
ns
ns
t
CLHCLL
t
CCHCCL
t
RCHRCL
t
TCHTCL
X1/CLK
CTCLK
RxC
TxC
t
CLLCLH
t
CCLCCH
t
RCLRCH
t
TCLTCH
SD00211
Figure 9. Clock
LIMITS
SYMBOL
PARAMETER
SCN26562C4 SCN26562C2
UNIT
Min Typ Max Min Typ Max
t
CLHCLL
t
CLLCLH
t
CCHCCL
t
CCLCCH
t
RCHRCL
t
RCLRCH
t
TCHTCL
t
TCLTCH
f
CL
f
CC
f
RC
f
TC
X1/CLK high to low time
X1/CLK low to high time
C/T CLK high to low time
C/T CLK low to high time
RxC high to low time
RxC low to high time
TxC high to low time
TxC low to high time
X1/CLK frequency
C/T CLK frequency
RxC frequency (16X or 1X)
TxC frequency (16X or 1X)
25
25
100
100
110
110
110
110
2.0
0
0
0
14.7456 16.0
4.0
4.0
4.0
25
25
100
100
150
150
150
150
2.0
0
0
0
14.7456 16.0
4.0
2.5
2.5
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
Page 11
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
11
AC ELECTRICAL CHARACTERISTICS (Continued)
1 BIT TIME
(1 OR 16 CLOCKS)
t
CILTXV
t
COLTXV
TxC
(INPUT)
TxD
TxC
(1X OUTPUT)
SD00212
Figure 10. Transmit Timing
LIMITS
SYMBOL
PARAMETER
SCN26562C4 SCN26562C2
UNIT
Min Max Min Max
t
CILTXV
t
COLTXV
TxC input low (1X) to TxD output
TxC input low (16X) to TxD output
TxC output low to TxD output
240
435
50
240
435
50
ns
ns
ns
t
RCHSOL
t
SILRCH
t
RCHSIH
t
RXVRCH
t
RCHRXI
SYNOUTN
SYNIN
RXC (1X)
INPUT
RxD
SD00213
LIMITS
SYMBOL
PARAMETER
SCN26562C4 SCN26562C2
UNIT
Min Max Min Max
t
RXVRCH
t
RCHRXI
t
SILRCH
t
RCHSIH
t
RCHSOL
RxD data valid to RxC high:
For NRZ data
For NRZI, Manchester, FM0, FM1 data
RxC high to RxD data invalid:
For NRZ data
For NRZI, Manchester, FM0, FM1 data
SYNIN low to RxC high
RxC high to SYNIN high
RxC high to SYNOUT low
50
120
50
10
100
50
300
50
130
50
10
100
50
300
ns
ns
ns
ns
ns
ns
ns
Figure 11. Receive Timing
Page 12
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
12
AC ELECTRICAL CHARACTERISTICS (Continued)
t
WRHEOZ
t
WRLEOL
t
WRLTRH
A
EOPN
(OUTPUT)
t
EILWRH
t
WRHEIH
RTxDRQN OR
TxDRQN
CEN
WRN
D7–D0
EOPN
(INPUT)
A The TxFIFO is addressed during this write cycle.
SD00214
Figure 12. Transmit Dual Address DMA Timing
LIMITS
SYMBOL
PARAMETER
SCN26562C4 SCN26562C2
UNIT
Min Max Min Max
t
WRLTRH
t
WRLEOL
t
WRHEOZ
t
EILWRH
t
WRHEIH
WRN low to Tx DMA REQN high
WRN low to EOPN output low
WRN high to EOPN output high impedance
EOPN input low to WRN high
WRN high to EOPN input high
50
50
320
225
225
50
50
320
225
225
ns
ns
ns
ns
ns
Page 13
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
13
AC ELECTRICAL CHARACTERISTICS (Continued)
t
RDLRRH
A
EOPN
(OUTPUT)
t
RDHEOZ
RTxDRQN
CEN
RDN
D7–D0
A The RxFIFO is addressed during this read cycle.
t
RDLEOL
SD00215
Figure 13. Receive Dual Address DMA Timing
LIMITS
SYMBOL
PARAMETER
SCN26562C4 SCN26562C2
UNIT
Min Max Min Max
t
RDLRRH
t
RDLEOL
t
RDHEOZ
RDN low to Rx DMA REQN high
RDN low to EOPN output low
RDN high to EOPN output high impedance
320
300
225
320
300
225
ns
ns
ns
Page 14
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
14
AC ELECTRICAL CHARACTERISTICS (Continued)
SD00216
t
TALTRH
t
TAHTAL
A
t
TALTAH
B
t
TAHEIH
t
EILTAH
t
TAHWDI
t
WDVTAH
t
TALEOL
t
TAHEOF
EOPN
(OUTPUT)
NOTES:
Ignored by the DUSCC since CEN is not asserted, but it can be used externally to qualify TxDAKN.
Memory read signal; not seen by DUSCC.
A
B
TxRQN
TxDAKN
WRN
MEMRN
EOPN
(INPUT)
D7–D0
Figure 14. DMA-Transmit Single Address Mode
LIMITS
SYMBOL
PARAMETER
SCN26562C4 SCN26562C2
UNIT
Min Max Min Max
t
TAHTAL
t
TALTAH
t
TALTRH
t
WDVTAH
t
TAHWDI
t
TALEOL
t
TAHEOF
t
EILTAH
t
TAHEIH
Transmit DMA ACKN high to low time
Transmit DMA ACKN low to high time
Tx DMA ACKN low to Tx DMA REQN high
Write data valid to Tx DMA ACKN high
Tx DMA ACKN high to write data invalid
Tx DMA ACKN low to EOPN output low
Tx DMA ACKN high to EOPN output float
EOPN input low to Tx DMA ACKN high
Tx DMA ACKN high to EOPN input high
100
250
90
30
50
50
250
170
200
100
250
90
30
50
50
250
170
200
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 15
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
15
AC ELECTRICAL CHARACTERISTICS (Continued)
NOTES:
Ignored by the DUSCC bit; it can be used to qualify RxDAKN.
Memory read signal; not seen by DUSCC.
t
RALRRH
t
RAHRAL
A
t
RALRAH
B
t
RAHDDI
t
RALDDV
t
RALEOL
t
RAHEOF
EOPN
(OUTPUT)
A
B
RxDRQN
RxDAKN
RDN
MEMWN
D7–D0
t
RAHDDF
SD00217
Figure 15. DMA-Receive Single Address Mode
LIMITS
SYMBOL
PARAMETER
SCN26562C4 SCN26562C2
UNIT
Min Max Min Max
t
RAHRAL
t
RALRAH
t
RALRRH
t
RALEOL
t
RAHEOF
t
RALDDV
t
RAHDDI
t
RAHDDF
Receive DMA ACKN high to low time
Receive DMA ACKN low to high time
Rx DMA ACKN low to Rx DMA REQN high
Rx DMA ACKN low to EOPN output low
Rx DMA ACKN high to EOPN output float
Rx DMA ACKN low to read data valid
Rx DMA ACKN high to read data invalid
Rx DMA ACKN high to data bus float
160
250
10
320
200
225
225
125
160
250
10
320
200
225
225
125
ns
ns
ns
ns
ns
ns
ns
ns
Page 16
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
16
AC ELECTRICAL CHARACTERISTICS (Continued)
RDN/WRN
t
RWHIRH
V
M
VOL +0.2V
V
OL
IRQN
SD00218
LIMITS
SYMBOL
PARAMETER
SCN26562C4 SCN26562C2
UNIT
Min Max Min Max
t
RWHIRH
RDN/WRN high to IRQN high for:
Read RxFIFO (RxRDY interrupt)
Write TxFIFO (TxRDY interrupt)
Write RSR (Rx condition interrupt)
Write TRSR (Rx/Tx interrupt)
Write ICTSR (counter/timer interrupt)
450
450
400
400
400
450
450
400
400
400
ns
ns
ns
ns
ns
X1/CLK
WRN
COMMAND
VALID
SD00219
RxC
1 2 3 4 5 6 7 8
RxD
LCN
a. Loop Control Output Assertion
1 2 3 4 5 6 7 8
b. Loop Control Output Negation
9
RxC
RxD
LCN
SD00220
Figure 18. Relationship Between Received Data and the Loop Control Output
Figure 16. Interrupt Timing
Figure 17. Command Timing
Page 17
Philips Semiconductors Product specification
SCN26562Dual universal serial communications controller (DUSCC)
1995 May 1
17
IRQN
50pF
2.7K
V
DD
RDYN
150pF
820Ω
+5.0V
50pF
1K
V
DD
EOPN
150pF
+5.0V
ALL OTHER
OUTPUTS
NOTE:
All C
L
includes 50pF stray capacitance,
i.e., C
L
= 150pF = 100pF discrete +50pF stray.
710
SD00221
Figure 19. Test Conditions for Outputs
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