Page 1
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1
1994 Apr 27 853-1067 12793
DESCRIPTION
The Philips Semiconductors SCN2651 PCI is a universal
synchronous/asynchronous data communications controller chip
designed for microcomputer systems. It interfaces directly to the
Philips Semiconductors SCN2650 microprocessor and may be used
in a polled or interrupt driven system environment. The SCN2651
accepts programmed instructions from the microprocessor and
supports many serial data communication disciplines, synchronous
and asynchronous, in the full or half-duplex mode.
The PCI serializes parallel data characters received from the
microprocessor for transmission. Simultaneously, it can receive
serial data and convert it into parallel data characters for input to the
microcomputer.
The SCN2651 contains a baud rate generator which can be
programmed to either accept an external clock or to generate
internal transmit or receive clocks. Sixteen different baud rates can
be selected under program control when operating in the internal
clock mode.
The PCI is constructed using Philips Semiconductors n-channel
silicon gate depletion load technology and is packaged in a 28-pin
DIP.
FEATURES
•Synchronous operation
– 5- to 8-bit characters
– Single or double SYN operation
– Internal character synchronization
– Transparent or non-transparent mode
– Automatic SYN or DLE-SYN insertion
– SYN or DLE stripping
– Odd, even, or no parity
– Local or remote maintenance loopback mode
– Baud rate: DC to 1Mbps (1X clock)
•Asynchronous operation
– 5- to 8-bit characters
– 1, 1-1/2 or 2 stop bits
– Odd, even, or no parity
– Parity, overrun and framing error detection
– Line break detection and generation
– False start bit detection
– Automatic serial echo mode
– Local or remote maintenance loopback mode
– Baud rate: DC to 1Mbps
(1X clock)
DC to 62.5kbps (16X clock)
DC to 15.625kbps
(64X clock)
PIN CONFIGURATIONS
24
23
22
21
20
19
18
17
16
15
28
27
12
10
11
9
8
7
6
5
4
3
2
1
14
13
26
25
D1
D0
V
CC
RxC
DTR
RTS
DSR
RESET
BRCLK
TxD
TxEMT/DSCHG
CTS
DCD
TxRDYRxRDY
R/W
A0
CE
A1
TxC
D7
D6
D5
D4
GND
RxD
D3
D2
DIP
TOP VIEW
SD00049
OTHER FEATURES
•Internal or external baud rate clock
•16 internal rates – 50 to 19,200 baud
•Double buffered transmitter and receiver
•Full or half duplex operation
•TTL compatible inputs and outputs
•Single 5V power supply
•No system clock required
•28-pin dual in-line package
APPLICATIONS
•Intelligent terminals
•Network processors
•Front-end processors
•Remote data concentrators
•Computer to computer links
•Serial peripherals
ORDERING CODE
VCC = 5V +5%
PACKAGES
Commercial
Industrial
DWG #
28-Pin Plastic Dual In-Line Package (DIP) SCN2651CC1N28 Not available SOT117-2
0°C to +70°C -40°C to +85°C
Page 2
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1994 Apr 27
2
BLOCK DIAGRAM
DATA BUS
D0–D7
RESET
A
0
A
1
R/W
CE
DATA BUS
BUFFER
OPERATION CONTROL
MODE REGISTER 1
BAUD RATE
GENERATOR
AND
CLOCK CONTROL
SYN/DLE CONTROL
SYN 1 REGISTER
SYN 2 REGISTER
DLE REGISTER
TRANSMITTER
TRANSMIT DATA
TxD
MODE REGISTER 2
COMMAND REGISTER
STATUS REGISTER
BRCLK
TxC
RxC
DSR
MODEM
CONTROL
DCD
CTS
RTS
DTR
TxEMT/*
DSCHG
HOLDING REGISTER
TRANSMIT
SHIFT REGISTER
TxRDY
RECEIVE
RECEIVE DATA
RECEIVER
RxD
RxRDY
SHIFT REGISTER
HOLDING REGISTER
(27, 28, 1, 2,
5, 6, 7, 8)
(21)
(12)
(10)
(13)
(11)
(20)
(9)
(25)
(22)
(16)
(17)
(23)
(24)
(18)
(15)
(19)
(14)
(3)
SD00050
ABSOLUTE MAXIMUM RATINGS
1
SYMBOL
PARAMETER RATING UNIT
T
A
Operating ambient temperature
2
Note 4 °C
T
STG
Storage temperature -65 to +150 °C
All voltages with respect to ground
3
-0.5 to +6.0
V
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not
implied.
2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effect of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature
range and operating supply range.
CAPACITANCE
T
A
= 25°C, V
CC
= 0V
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min Typ Max
UNIT
Capacitance
C
IN
C
OUT
C
I/O
Input
Output
Input/Output
f
C
= 1MHz
Unmeasured pins tied to ground
20
20
20
pF
pF
pF
Page 3
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1994 Apr 27
3
DC ELECTRICAL CHARACTERISTICS
1, 2, 3
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min Typ Max
UNIT
Input voltage
V
IL
V
IH
Low
High
2.0
0.8
V
V
Output voltage
V
OL
V
OH
Low
High
IOL = 1.6mA
I
OH
= -100µA 2.4
0.4
V
V
I
IL
Input leakage current VIN = 0 to 5.25V -10 10 µA
3-State output leakage current
I
LH
I
LL
Data bus high
Data bus low
VO = 4.0V
V
O
= 0.45V
-10
-10
10
10
µA
µA
I
CC
Power supply current 150 mA
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature
range and operating supply range.
2. All voltage measurements are referenced to ground. All time measurements are at the 50% level for inputs (except t
BRH
and t
BRL
) and at
0.8V and 2.0V for outputs. Input levels for testing are 0.45V and 2.4V .
3. Typical values are at +25°C, typical supply voltages and typical processing parameters.
AC ELECTRICAL CHARACTERISTICS
1, 2, 3
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Min Typ Max UNIT
Pulse width
t
RES
t
CE
Reset
Chip enable
1000
300
ns
ns
Set-up and hold time
t
AS
t
AH
t
CS
t
CH
t
DS
t
DH
t
RXS
t
RXH
Address setup
Address hold
R
/W control setup
R
/W control hold
Data setup for write
Data hold for write
RX data setup
RX data hold
20
20
20
20
225
0
300
350
ns
ns
ns
ns
ns
ns
ns
ns
t
DD
t
DF
t
CED
Data delay time for read
Data bus floating time for read
CE
to CE delay
C
L
= 100pF
C
L
= 100pF
700
250
150
ns
ns
ns
Input clock frequency
f
BRG
f
R/T
6
Baud rate generator
TxC
or RxC
1.0dc5.0688 5.0738
1.0
MHz
MHz
Clock width
t
BRH
5
t
BRL
5
t
R/TH
t
R/TL
6
Baud rate high
Baud rate low
TxC
or RxC high
TxC
or RxC low
70
70
500
500
ns
ns
ns
ns
t
TXD
t
TCS
TxD delay from falling edge of TxC
Skew between TxD changing and falling edge
of TxC output
4
C
L
= 100pF
C
L
= 100pF
0
650 ns
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature
range and operating supply range.
2. All voltage measurements are referenced to ground. All time measurements are at the 50% level for inputs (except t
BRH
and t
BRL
) and at
0.8V and 2.0V for outputs. Input levels for testing are 0.45V and 2.4V .
3. Typical values are at +25°C, typical supply voltages and typical processing parameters.
4. Parameter applies when internal transmitter clock is used.
5. Under test conditions of 5.0688MHz, f
BRG
, t
BRH
, and t
BRL
measured at VIH and VIL respectively.
6. t
R/T
and t
R/TL
shown for all modes except local loopback. For local loopback mode f
R/T
= 0.7MHz and t
R/TL
= 700ns min.
Page 4
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1994 Apr 27
4
PIN DESCRIPTION
Pin No. Symbol Name and Function Type
27, 28, 1, 2, 5-8 D0 – D
7
8-Bit data bus I/O
21 RESET Reset I
12, 10 A0–A
1
Internal register select lines I
13 R/W Read or write command I
11 CE Chip enable input I
22 DSR Data set ready I
24 DTR Data terminal ready O
23 RTS Request to send O
17 CTS Clear to send I
16 DCD Data carrier detected I
18 TxEMT/DSCHG Transmitter empty or data set change O
9 TxC Transmitter clock I/O
25 RxC Receiver clock I/O
19 TxD Transmitter data O
3 RxD Receiver data I
15 TxRDY Transmitter ready O
14 RxRDY Receiver ready O
20 BRCLK Baud rate generator clock I
26 V
CC
+5V supply I
4 GND Ground I
Table 1. Baud Rate Generator Characteristics
Crystal Frequency = 5.0688MHz
Baud
Rate
Theoretical
Frequency
16X Clock
Actual
Frequency
16X Clock
Percent
Error
Divisor
50 0.8kHz 0.8kHz – 6336
75 1.2 1.2 – 4224
110 1.76 1.76 – 2880
134.5 2.152 2.1523 0.016 2355
150 2.4 2.4 – 2112
300 4.8 4.8 – 1056
600 9.6 9.6 – 528
1200 19.2 19.2 – 264
1800 28.8 28.8 – 176
2000 32.0 32.081 0.253 158
2400 38.4 38.4 – 132
NOTE: *Error at 19200 can be reduced to zero by using crystal
frequency 4.9152MHz. 16X clock is used in asynchronous mode.
In synchronous mode, clock multiplier is 1X.
BLOCK DIAGRAM
The PCI consists of six major sections. These are the transmitter,
receiver, timing, operation control, modem control and SYN/DLE
control. These sections communicate with each other via an
internal data bus and an internal control bus. The internal data bus
interfaces to the microprocessor data bus via a data bus buffer.
Operation Control
This functional block stores configuration and operation commands
from the CPU and generates appropriate signals to various internal
sections to control the overall device operation. It contains read and
write circuits to permit communications with the microprocessor via
the data bus and contains mode registers 1 and 2, the command
register, and the status register. Details of register addressing and
protocol are presented in the PCI programming section of this data
sheet.
Timing
The PCI contains a baud rate generator (BRG) which is
programmable to accept external transmit or receive clocks or to
divide an external clock to perform data communications. The unit
can generate 16 commonly used baud rates, any one of which can
be selected for full-duplex operation. See Table 1.
Receiver
The receiver accepts serial data on the RxD pin, converts this serial
input to parallel format, checks for bits or characters that are unique
to the communication technique and sends an “assembled”
character to the CPU.
Transmitter
The transmitter accepts parallel data from the CPU, converts it to a
serial bit stream, inserts the appropriate characters or bits (based on
the communication technique) and outputs a composite serial
stream of data on the TxD output pin.
Modem Control
The modem control section provides interfacing for three input
signals and three output signals used for “handshaking” and status
indication between the CPU and a modem.
SYN/DLE Control
This section contains control circuitry and three 8-bit registers
storing the SYN1, SYN2, and DLE characters provided by the CPU.
These registers are used in the synchronous mode of operation to
provide the characters required for synchronization, idle fill and data
transparency.
Page 5
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1994 Apr 27
5
INTERFACE SIGNALS
The PCI interface signals can be grouped into two types: the
CPU-related signals (shown in Table 2), which interface the
SCN2651 to the microprocessor system, and the device-related
signals (shown in Table 3), which are used to interface to the
communications device or system.
OPERATION
The functional operation of the SCN2651 is programmed by a set of
control words supplied by the CPU. These control words specify
items such as synchronous or asynchronous mode, baud rate,
number of bits per character, etc. The programming procedure is
described in the PCI programming section of the data sheet.
After programming, the PCI is ready to perform the desired
communications functions. The receiver performs serial to parallel
conversion of data received from a modem or equivalent device.
The transmitter converts parallel data received from the CPU to a
serial bit stream. These actions are accomplished within the
framework specified by the control words.
Receiver
The SCN2651 is conditioned to receive data when the DCD input is
low and the RxEN bit in the command register is true. In the
asynchronous mode, the receiver looks for a high to low transition of
the start bit on the RxD input line. If a transition is detected, the
state of the RxD line is sampled again after a delay of one-half of a
bit-time. If RxD is now high, the search for a valid start bit is begun
again. If RxD is still low, a valid start bit is assumed and the receiver
continues to sample the input line at one bit time intervals until the
proper number of data bits, the parity bit, and one stop bit(s) have
been assembled. The data is then transferred to the receive data
holding register, the RxRDY bit in the status register is set, and the
RxRDY
output is asserted. If the character length is less than 8 bits,
the high order unused bits in the holding register are set to zero.
The parity error, framing error, and overrun error status bits are
strobed into the status register on the positive going edge of RxC
corresponding to the received character boundary. If a break
condition is detected (RxD is low for the entire character as well as
the stop bit[s]), only one character consisting of all zeros (with the
FE status bit set) will be transferred to the holding register. The RxD
input must return to a high condition before a search for the next
start bit begins.
When the PCI is initialized into the synchronous mode, the receiver
first enters the hunt mode on a 0 to 1 transition of RxEN (CR2). In
this mode, as data is shifted into the receiver shift register a bit at a
time, the contents of the register are compared to the contents of the
SYN1 register. If the two are not equal, the next bit is shifted in and
the comparison is repeated. When the two registers match, the
hunt mode is terminated and character assembly mode begins. If
single SYN operation is programmed, the SYN detect status bit is
set. If double SYN operation is programmed, the first character
assembled after SYN1 must be SYN2 in order for the SYN detect bit
to be set. Otherwise, the PCI returns to the hunt mode. (Note that
the sequence SYN1–SYN1–SYN2 will not achieve synchronization.)
When synchronization has been achieved, the PCI continues to
assemble characters and transfer them to the holding register,
setting the RxRDY status bit and asserting the RxRDY
output each
time a character is transferred. The PE and OE status bits are set
as appropriate. Further receipt of the appropriate SYN sequence
sets the SYN detect status bit. If the SYN stripping mode is
Table 2. CPU-Related Signals
PIN NAME
PIN
NO.
INPUT/
OUTPUT
FUNCTION
V
CC
26 I +5V supply input
GND 4 I Ground
RESET 21 I
A high on this input performs a master reset on the SCN2651. This signal asynchronously terminates any
device activity and clears the mode, command and status registers. The device assumes the idle state
and remains there until initialized with the appropriate control words.
A1 – A
0
10, 12 I Address lines used to select internal PCI registers.
R/W 13 I Read command when low, write command when high.
CE 11 I
Chip enable command. When low, indicates that control and data lines to the PCI are valid and that the
operation specified by the R
W, A1 and A0 inputs should be performed. When high, places the D0–D7 lines
in the 3-State condition.
D7 – D
0
8, 7, 6,
5, 2, 1,
28, 27
I/O
8-bit, three-state data bus used to transfer commands, data and status between PCI and the CPU. D0 is
the least significant bit, D
7
the most significant bit.
TxRDY 15 O
This output is the complement of status register bit SR0. When low, it indicates that the transmit data
holding register (THR) is ready to accept a data character from the CPU. It goes high when the data
character is loaded. This output is valid only when the transmitter is enabled. It is an open drain output
which can be used as an interrupt to the CPU.
RxRDY 14 O
This output is the complement of status register bit SR1. When low, it indicates that the receive data
holding register (RHR) has a character ready for input to the CPU. It goes high when the RHR is read by
the CPU, and also when the receiver is disabled. It is an open drain output which can be used as an
interrupt to the CPU.
TxEMT/DS
CHG
18 O
This output is the complement of status register bit SR2. When low, it indicates that the transmitter has
completed serialization of the last character loaded by the CPU, or that a change of state of the DSR
or
DCD
inputs has occurred. This output goes high when the status register is read by the CPU, if the
TxEMT condition does not exist. Otherwise, the THR must be loaded by the CPU for this line to go high.
It is an open drain output which can be used as an interrupt to the CPU.
Page 6
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1994 Apr 27
6
Table 3. Device-Related Signals
PIN NAME
PIN
NO.
INPUT/O
UTPUT
FUNCTION
BRCLK 20 I
5.0688MHz clock input to the internal baud rate generator. Not required if external receiver and
transmitter clocks are used.
RxC 25 I/O
Receiver clock. If external receiver clock is programmed, this input controls the rate at which the
character is to be received. Its frequency is 1X, 16X or 64X the baud rate, as programmed by mode
register 1. Data are sampled on the rising edge of the clock. If internal receiver clock is programmed, this
pin becomes an output at 1X the programmed baud rate.*
TxC 9 I/O
Transmitter clock. If external transmitter clock is programmed, this input controls the rate at which the
character is transmitted. Its frequency is 1X, 16X or 64X the baud rate, as programmed by mode register
1. The transmitted data changes on the falling edge of the clock. If internal transmitter clock is
programmed, the pin becomes an output at 1X the programmed baud rate.*
RxD 3 I Serial data input to the receiver. “Mark” is high, “Space” is low.
TxD 19 O
Serial data output from the transmitter. “Mark” is high, “space” is low. Held in mark condition when the
transmitter is disabled.
DSR 22 I
General purpose input which can be used for data set ready or ring indicator condition. Its complement
appears as status register bit SR7. Causes a low output on TxEMT
/DSCHG when its state changes.
DCD 16 I
Data carrier detect input. Must be low in order for the receiver to operate. Its complement appears as
status register bit SR6. Causes a low output on TxEMT
/DSCHG when its state changes.
CTS 17 I
Clear to send input. Must be low in order for the transmitter to operate. If it goes high during
transmission, the character in the transmit shift register will be transmitted before termination.
DTR 24 O
General purpose output which is the complement of command register bit CR1. Normally used to indicate
data terminal ready.
RTS 23 O
General purpose output which is the complement of command register bit CR5. Normally used to indicate
request to send.
NOTE: *RxC and TxC outputs have short circuit protection max. CL = 100pF
commanded, SYN characters are not transferred to the Holding
Register. Note that the SYN characters used to establish initial
synchronization are not transferred to the holding register in any
case.
Transmitter
The PCI is conditioned to transmit data when the CTS input is Low
and the TxEN command register bit is set. The SCN2651 indicates
to the CPU that it can accept a character for transmission by setting
the TxRDY status bit and asserting the TxRDY
output. When the
CPU writes a character into the transmit data holding register, these
conditions are negated. Data is transferred from the holding register
to the transmit shift register when it is idle or has completed
transmission of the previous character. The TxRDY conditions are
then asserted again. Thus, one full character time of buffering is
provided.
In the asynchronous mode, the transmitter automatically sends a
start bit followed by the programmed number of data bits, the least
significant bit being sent first. It then appends an optional odd or
even parity bit and the programmed number of stop bits. If,
following transmission of the data bits, a new character is not
available in the transmit holding register, the TxD output remains in
the marking (high) condition and the TxEMT
/DSCHG output and its
corresponding status bit are asserted. Transmission resumes when
the CPU loads a new character into the holding register. The
transmitter can be forced to output a continuous low (BREAK)
condition by setting the send break command bit high.
In the synchronous mode, when the SCN2651 is initially conditioned
to transmit, the TxD output remains high and the TxRDY condition is
asserted until the first character to be transmitted (usually a SYN
character) is loaded by the CPU. Subsequent to this, a continuous
stream of characters is transmitted. No extra bits (other than parity,
if commanded) are generated by the PCI unless the CPU fails to
send a new character to the PCI by the time the transmitter has
completed sending the previous character.
Since synchronous communication does not allow gaps between
characters, the PCI asserts TxEMT and automatically “fills” the gap
by transmitting SYN1s, SYN1–SYN2 doublets, or DLE–SYN1
doublets, depending on the state of MR16 and MR17. Normal
transmission of the message resumes when a new character is
available in the transmit data holding register. If the send DLE bit in
the command register is true, the DLE character is automatically
transmitted prior to transmission of the message character in the
THR.
PCI PROGRAMMING
Prior to initiating data communications, the SCN2651 operational
mode must be programmed by performing write operations to the
mode and command registers. In addition, if synchronous operation
is programmed, the appropriate SYN/DLE registers must be loaded.
The PCI can be reconfigured at any time during program execution.
However, if the change has an effect on the reception of a character
the receiver should be disabled. Alternatively if the change is made
1 1/2 RxC periods after RxRDY goes active it will affect the next
character assembly. A flowchart of the initialization process appears
in Figure 1.
The internal registers of the PCI are accessed by applying specific
signals to the CE
, R/W, A1 and A0 inputs. The conditions necessary
to address each register are shown in Table 4.
The SYN1, SYN2, and DLE registers are accessed by performing
write operations with the conditions A
1
= 0, A0 = 1, and R/W = 1.
The first operation loads the SYN1 register. The next loads the
SYN2 register, and the third loads the DLE register. Reading or
loading the mode registers is done in a similar manner. The first
write (or read) operation addresses mode register 1, and a
subsequent operation addresses mode register 2. If more than the
Page 7
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1994 Apr 27
7
required number of accesses are made, the internal sequencer
recycles to point at the first register. The pointers are reset to SYN1
register and mode register 1 by a RESET input or by performing a
“read command register” operation, but are unaffected by any other
read or write operation.
The SCN2651 register formats are summarized in Tables 5, 6, 7 and
8. Mode registers 1 and 2 define the general operational
characteristics of the PCI, while the command register controls the
operation within this basic framework. The PCI indicates its status
in the status register. These registers are cleared when a RESET
input is applied.
Mode Register 1 (MR1)
Table 5 illustrates mode register 1. Bits MR11 and MR10 select the
communication format and baud rate multiplier. 00 specifies
synchronous mode and 1X multiplier. 1X, 16X, and 64X multipliers
are programmable for asynchronous format. However, the multiplier
in asynchronous format applies only if the external clock input option
is selected by MR24 or MR25.
MR13 and MR12 select a character length of 5, 6, 7, or 8 bits. The
character length does not include the parity bit, if programmed, and
does not include the start and stop bits in asynchronous mode.
MR14 controls parity generation. If enabled, a parity bit is added to
the transmitted character and the receiver performs a parity check
on incoming data. MR15 selects odd or even parity when parity is
enabled by MR14.
In asynchronous mode, MR17 and MR16 select character framing of
1, 1.5, or 2 stop bits. (If 1X baud rate is programmed, 1.5 stop bits
default to 1 stop bit on transmit.) In synchronous mode, MR17
controls the number of SYN characters used to establish
synchronization and for character fill when the transmitter is idle.
SYN1 alone is used if MR17 = 1, and SYN1–SYN2 is used when
MR17 = 0. If the transparent mode is specified by MR16,
DLE–SYN1 is used for character fill and SYN detect, but he normal
synchronization sequence is used. Also DLE stripping and DLE
detect (with MR14 = 0) are enabled.
Mode Register 2 (MR2)
Table 6 illustrates mode register 2. MR23, MR22, MR21, and MR20
control the frequency of the internal baud rate generator (BRG).
Sixteen rates are selectable. When driven by a 5.0688MHz input at
the BRCLK input (Pin 20), the BRG output has zero error except at
134.5 2000, and 19,200 baud, which have errors of +0.016%,
+0.235%, and +3.125% respectively.
Table 4. SCN2651 Register Addressing
CE A
1
A0R/W FUNCTION
1 X X X 3-State data bus
0 0 0 0 Read receive holding register
0 0 0 1 Write transmit holding register
0 0 1 0 Read status register
0 0 1 1 Write SYN1/SYN2/DLE registers
0 1 0 0 Read mode registers 1/2
0 1 0 1 Write mode registers 1/2
0 1 1 0 Read command register
0 1 1 1 Write command register
NOTE: See AC Characteristics section for timing requirements.
MR25 and MR24 select either the BRG or the external inputs TxC
and RxC as the clock source for the transmitter and receiver,
respectively. If the BRG clock is selected, the baud rate factor in
asynchronous mode is 16X regardless of the factor selected by
MR11 and MR10. In addition, the corresponding clock pin provides
an output at 1X the baud rate.
LOAD
MODE REGISTER 1
LOAD
MODE REGISTER 2
SYNCHRONOUS?
LOAD
SYN 1 REGISTER
DOUBLE
SYNC?
LOAD
SYN 2 REGISTER
TRANSPARENT
MODE?
LOAD
DLE REGISTER
INITIAL RESET
N
Y
Y
N
N
Y
TRANSPARENT
MODE?
Y
N
LOAD
COMMAND REGISTER
OPERATE
RECONFIGURE?
N
Y
DISABLE
RCVR AND XMTR
NOTE:
SYN1 Register must be written
before SYN2 can be written, and
SYN2 before DLE can be written.
NOTE:
Mode Register 1 must be written
before 2 can be written. Mode Register 2
need not be programmed if external
clocks are used.
SD00051
Figure 1. SCN2651 Initialization Flowchart
Page 8
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1994 Apr 27
8
Table 5. Mode Register 1 (MR1)
MR17 MR16 MR15 MR14 MR13 MR12 MR11 MR10
Parity Type Parity Control Character Length Mode and Baud Rate Factor
Async: Stop bit length
00 = Invalid
01 = 1 Stop bit
10 = 1 1/2 Stop bits
11 = 2 Stop bits
0 = Odd
1 = Even
0 = Disabled
1 = Enabled
00 = 5 Bits
01 = 6 Bits
10 = 7 Bits
11 = 8 Bits
00 = Synchronous 1X rate
01 = Asynchronous 1X rate
10 = Asynchronous 16X rate
11 = Asynchronous 64X rate
Sync:
Number of SYN
char
0 = Double SYN
1 = Single SYN
Sync:
Transparency
control
0 = Normal
1 = Transparent
NOTE:
Baud rate factor in asynchronous applies only if external clock is selected. Factor is 16X if internal clock is selected. Mode must be selected
(MR11, MR10) in any case.
Table 6. Mode Register 2 (MR2)
MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20
Transmitter
Clock
Receiver
Clock
Baud Rate Selection
Not used 0 = External
1 = Internal
0= External
1 = Internal
0000 = 50 Baud 1000 = 1800 Baud
0001 = 75 1001 = 2000
0010 = 110 1010 = 2400
0011 = 134.5 1011 = 3600
0100 = 150 1100 = 4800
0101 = 300 1101 = 7200
0110 = 600 1110 = 9600
0111 = 1200 1111 = 19,200
Table 7. Command Register (CR)
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0
Operating Mode
Request
to Send
Reset Error
Receive
Control
(RxEN)
Data Terminal
Ready
Transmit
Control
(TxEN)
00 = Normal operation
01 = Async: automatic
echo mode
Sync: SYN and/or DLE
stripping mode
10 = Local Loopback
11 = Remote Loopback
0 = Force RTS
output high
1 = Force RTS
output low
0 = Normal
1 = Reset
error flag
in status reg
(FE, OE,
PE/DLE
DETECT)
Async:
Force Break
0 = Normal
1 = Force
break
Sync
Send DLE
0 = Normal
1 = Send DLE
0 = Disable
1 = Enable
0 = Force DTR
output high
1 = Force DTR
output low
0 = Disable
1 = Enable
Command Register (CR)
Table 7 illustrates the command register. Bits CR0 (TxEN) and CR2
(RxEN) enable or disable the transmitter and receiver respectively.
A 0 to 1 transition of CR2 forces start bit search (async mode) or
hunt mode (sync mode) on the second RxC
rising edge. Disabling
the receiver causes RxRDY
to go high (inactive). If the transmitter
is disabled, it will complete the transmission of the character in the
transmit shift register (if any) prior to terminating operation. The TxD
output will then remain in the marking state (high) while TxRDY
and
TxEMT
will go high (inactive). If the receiver is disabled, it will
terminate operation immediately. Any character being assembled
will be neglected.
Bits CR1 (DTR) and CR5 (RTS) control the DTR
and RTS outputs.
Data at the outputs is the logical complement of the register data.
In asynchronous mode, setting CR3 will force and hold the TxD
output low (spacing condition) at the end of the current transmitted
character. Normal operation resumes when CR3 is cleared. The
TxD line will go high for at least one bit time before beginning
transmission of the next character in the transmit data holding
register. In synchronous mode, setting CR3 causes the
transmission of the DLE register contents prior to sending the
character in the transmit data holding register. CR3 should be reset
in response to the next TxRDY.
Page 9
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1994 Apr 27
9
Table 8. Status Register (SR)
SR7 SR6 SR5 SR4 SR3 SR2 SR1 SR0
Data Set
Ready
Data Carrier
Detect
FE/SYN
Detect
Overrun
PE/DLE
Detect
TxEMT/
DSCHG
RxRDY TxRDY
0 = DSR input
is high
1 = DSR
input
is low
0 = DCD input
is high
1 = DCD
input
is low
Async:
0 = Normal
1 = Framing
ERROR
Sync:
0 = Normal
1 = SYN char
detected
0 = Normal
1 = Overrun
error
Async:
0 = Normal
1 = Parity error
Sync:
0 = Normal
1 = Parity
error or
DLE char
received
0 = Normal
1 = Change in
DSR
or
DCD
, or
transmit
shift
register is
empty
0 = Receive
holding
register
empty
1 = Receive
holding
register
has data
0 = Transmit
holding
register
busy
1 = Transmit
holding
register
empty
Setting CR4 causes the error flags in the status register (SR3, SR4,
and SR5) to be cleared. This is a one time command. There is no
internal latch for this bit.
The PCI can operate in one of four submodes within each major
mode (synchronous or asynchronous). The operational submode is
determined by CR7 and CR6. CR7 – CR6 = 00 is the normal mode,
with the transmitter and receiver operating independently in
accordance with the mode and status register instructions.
In asynchronous mode, CR7 – CR6 = 01 places the PCI in the
automatic echo mode. Clocked, regenerated received data are
automatically directed to the TxD line while normal receiver
operation continues. The receiver must be enabled (CR2 = 1), but
the transmitter need not be enabled. CPU to receiver
communications continues normally, but the CPU to transmitter link
is disabled. Only the first character of a break condition is echoed.
The TxD output will go high until the next valid start is detected.
The following conditions are true while in automatic echo mode:
1. Data assembled by the receiver are automatically placed in the
transmit holding register and retransmitted by the transmitter on
the TxD output.
2. The transmitter is clocked by the receive clock.
3. TxRDY
output = 1.
4. The TxEMT/DSCHG
pin will reflect only the data set change
condition.
5. The TxEN command (CR0) is ignored.
In synchronous mode, CR7 – CR6 = 01 places the PCI in the
automatic SYN/DLE stripping mode. The exact action taken
depends on the setting of bits MR17 and MR16:
1. In the non-transparent, single SYN mode (MR17 – MR16 = 10),
characters in the data stream matching SYN1 are not transferred
to the receive data holding register (RHR).
2. In the non-transparent, double SYN mode (MR17 – MR16 = 00),
characters in the data stream matching SYN1, or SYN2 if
immediately preceded by SYN1, are not transferred the RHR.
However, only the first SYN1 of an SYN1 – SYN1 pair is
stripped.
3. In transparent mode (MR16 = 1), character in the data stream
matching DLE, or SYN1 if immediately preceded by DLE, are not
transferred to the RHR. However, only the first DLE of a DLE–
DLE pair is stripped.
Note that automatic stripping mode does not affect the setting of the
DLE detect and SYN detect status bits (SR3 and SR5).
Two diagnostic submodes can also be configured. In local loopback
mode (CR7 – CR6 = 10), the following loops are connected
internally:
1. The transmitter output is connected to the receiver input.
2. DTR
is connected to DCD and RTS is connected to CTS.
3. The receiver is clocked by the transmit clock.
4. The DTR
, RTS and TxD outputs are held high.
5. The CTS
, DCD, DSR and RxD inputs are ignored.
Additional requirements to operate in the local loopback mode are
that CR0 (TxEN), CR1 (DTR), and CR5 (RTS) must be set to 1.
CR2 (RxEN) is ignored by the PCI.
The second diagnostic mode is the remote loopback mode (CR7 –
CR6 = 11). In this mode:
1. Data assembled by the receiver are automatically placed in the
transmit holding register and retransmitted by the transmitter on
the TxD output.
2. The transmitter is clocked by the receive clock.
3. No data is sent to the local CPU, but he error status conditions
(PE, OE, FE) are set.
4. The RxRDY
, TxRDY, and TxEMT/DSCHG outputs are held high.
5. CR0 (TxEN) is ignored.
6. All other signals operate normally.
Status Register
The data contained in the status register (as shown in Table 8)
indicate receiver and transmitter conditions and modem/data set
status.
SR0 is the transmitter ready (TxRDY) status bit. It, and its
corresponding output, are valid only when the transmitter is enabled.
If equal to 0, it indicates that the transmit data holding register has
been loaded by the CPU and the data has not been transferred to
the transmit shift register. If set equal to 1, it indicates that the
Holding Register is ready to accept data from the CPU. This bit is
initially set when the transmitter is enabled by CR0, unless a
character has previously been loaded into the holding register. It is
not set when the automatic echo or remote loopback modes are
programmed. When this bit is set, the TxRDY
output pin is low. In
the automatic echo and remote loopback modes, the output is held
high.
SR1, the receiver ready (RxRDY) status bit, indicates the condition
of the receive data holding register. If set, it indicates that a
Page 10
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1994 Apr 27
10
character has been loaded into the holding register from the receive
shift register and is ready to be read by the CPU. If equal to zero,
there is no new character in the holding register. This bit is cleared
when the CPU reads the receive data holding register or when the
receiver is disabled by CR2. When set, the RxRDY
output is low.
The TxEMT/DSCHG bit, SR2, when set, indicates either a change of
state of the DSR
or DCD inputs or that the transmit shift register has
completed transmission of a character and no new character has
been loaded into the transmit data holding register. Note that in
synchronous mode this bit will be set even though the appropriate
“fill” character is transmitted. TxEMT will not go active until at least
one character has been transmitted. It is cleared by loading the
transmit data holding register. The DSCHG condition is enabled
when TxEN = 1 or RxEN = 1. If the status register is read twice and
SR2 = 1 while SR6 and SR7 remain unchanged, then a TxEMT
condition exists. It is cleared when the status register is read by the
CPU. When SR2 is set, the TxEMT
/DSCHG output is low.
SR3, when set, indicates a received parity error when parity is
enabled by MR14. In synchronous transparent mode (MR16 = 1),
with parity disabled, it indicates that a character matching the DLE
register has been received. However, only the first DLE of two
successive DLEs will set SR3. This bit is cleared when the receiver
is disabled and by the reset error command, CR4.
The overrun error status bit, SR4, indicates that the previous
character loaded into the receive holding register was not read by
the CPU at the time a new received character was transferred into it.
This bit is cleared when the receiver is disabled and by the reset
error command, CR4.
In asynchronous mode, bit SR5 signifies that the received character
was not framed by the programmed number of stop bits. (If 1.5 stop
bits are programmed, only the first stop bit is checked.) If RHR = 0
when SR5 = 1, a break condition is present. In synchronous
non-transparent mode (MR16 = 0), it indicates receipt of the SYN1
character in single SYN mode or the SYN1 – SYN2 pair in double
SYN mode. In synchronous transparent mode (MR16 = 1), this bit is
set upon detection of the initial synchronizing characters (SYN1 or
SYN1 – SYN2) and, after synchronization has been achieved, when
a DLE–SYN1 pair is received. The bit is reset when the receiver is
disabled, when the reset error command is given in asynchronous
mode, and when the status register is read by the CPU in the
synchronous mode.
SR6 and SR7 reflect the conditions of the DCD
and DSR inputs
respectively. A low input sets its corresponding status bit and a high
input clears it.
Page 11
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1994 Apr 27
11
TIMING DIAGRAMS
RESET
t
RES
RESET
BRCLK,
TxC
, RxC
1/f
BRG
t
R/TH
t
BRH
t
R/TL
t
BRL
1/f
R/T
CLOCK
TRANSMIT
RECEIVE
TxC
(INPUT)
1 BIT TIME
(1, 16, OR 64 CLOCK PERIODS)
TxD
TxC
(OUTPUT)
t
TxD
t
TCS
t
TxD
RxD
RxC (IX)
t
RXS
t
RXH
t
CE
t
CED
CE
A
0
,
A
1
R/W
t
AS
t
CS
t
AH
t
CH
D0–D
7
(WRITE)
t
DS
t
DH
BUS
FLOATING
NOT
VALID
BUS
FLOATING
DATA VALID
t
DD
t
DF
D0–D
7
(READ)
READ AND WRITE
SD00052
Page 12
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1994 Apr 27
12
TIMING DIAGRAMS (Continued)
1 2 3 4 5
DATA 1
1 2 3 4 5
DATA 2
1 2 3 4 5
DATA 3
1 2 3 4 5
SYN 1
1 2 3 4 5
DATA 4
1 2 3 4 5
DATA 1
A B C 1 2 3 4 5A B C
DATA 2
1 2 3 4 5A B C
DATA 3
1 2A
DATA 4
D D
DATA 1 DATA 2 DATA 3 DATA 4
DATA 1 DATA 2 DATA 3 DATA 4
TxC
(1X)
TxD
TxEN
TxRDY
TxEMT
CE FOR
WRITE
OF THR
TxD
TxEN
TxRDY
TxEMT
CE FOR
WRITE
OF THR
ASYNCHRONOUS MODE SYNCHRONOUS MODE
TxRDY, TxEMT (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode])
NOTES:
A = Start bit
B = Stop bit 1
C = Stop bit 2
D = TxD marking condition
TxEMT goes low at the beginning of the last data bit, or, if parity is enabled, at the beginning of the parity bit.
SD00053
Page 13
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1994 Apr 27
13
TIMING DIAGRAMS (Continued)
1 2 3 4 5
SYN 1
1 2 3 4 5
DATA 1
1 2 3 4 5
DATA 2
1 2 3 4 5
DATA 3
1 2 3 4 5
DATA 4
1 2 3 4 5
DATA 1
A B C 1 2 3 4 5A B C
DATA 2
1 2 3 4 5A
DATA 3
D
READ RHR
(DATA 1)
READ RHR
(DATA 3)
READ
STATUS
RxC
RxD
RxEN
RxRDY
CE FOR
READ
RxD
RxEN
RxRDY
CE FOR
READ
ASYNCHRONOUS MODE SYNCHRONOUS MODE
RxRDY (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode])
NOTES:
A = Start bit
B = Stop bit 1
C = Stop bit 2
D = TxD marking condition
1
2 3 4 5
DATA 5
IGNORED
READ RHR
(DATA 1)
READ RHR
(DATA 2)
READ RHR
(DATA 3)
READ RHR
(DATA 3)
READ
STATUS
SYNDET
STATUS BIT
D
_ _
B C 1 2 3A
DATA 4
OVERRUN
STATUS BIT
SD00054
Page 14
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1994 Apr 27
14
TYPICAL APPLICATIONS
ADDRESS BUS
CONTROL BUS
DATA BUS
8
RxD
TxD
BRCLK
SCN2651
EIA TO TTL
CONVERT
(OPT)
5.0688MHz
OSCILLATOR
ASYNCHRONOUS INTERFACE TO CRT TERMINAL
CRT
TERMINAL
ADDRESS BUS
CONTROL BUS
DATA BUS
8
RxD
TxD
SCN2651
ASYNCHRONOUS INTERFACE TO TELEPHONE LINES
DSR
DTR
CTS
RTS
DCD
BRCLK
ASYNC
MODEM
5.0688MHz
OSCILLATOR
PHONE
LINE
INTERFACE
TELEPHONE
LINE
SD00055
Page 15
Philips Semiconductors Product specification
SCN2651Programmable communications interface (PCI)
1994 Apr 27
15
TYPICAL APPLICATIONS (Continued)
ADDRESS BUS
CONTROL BUS
DATA BUS
RxD
TxD
SCN2651
SYNCHRONOUS
TERMINAL OR
PERIPHERAL
DEVICE
SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL DEVICE
ADDRESS BUS
CONTROL BUS
DATA BUS
RxD
TxD
SCN2651
SYNCHRONOUS INTERFACE TO TELEPHONE LINES
DCD
RTS
DSR
DTR
SYNC
MODEM
PHONE
LINE
INTERFACE
TELEPHONE
LINE
RxC
TxC
RxC
TxC
CTS
SD00056
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