Datasheet MCM6341ZP10, MCM6341ZP11, MCM6341ZP12, MCM6341ZP15, SCM6341ZP10A Datasheet (Motorola)

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MCM6341/D

Advance Information

128K x 24 Bit Static Random
Access Memory

The MCM6341 is a 3,145,728–bit static random access memory organized as
131,072 words of 24 bits. Static design eliminates the need for external clocks
or timing strobes.

The MCM6341 is equipped with chip enable (E1

) pins, allowing for greater system flexibility and eliminating bus contention

(G
problems.

The MCM6341 is available in a 1 19–bump PBGA package.

• Single 3.3 V ± 10% Power Supply

• Fast Access Time: 10/11/12/15 ns

• Equal Address and Chip Enable Access Time

• All Inputs and Outputs are TTL Compatible

• Three–State Outputs

• Power Operation: 280/275/270/260 mA Maximum, Active AC

• Commercial Temperature (0°C to 70°C) and

Industrial Temperature (– 40°C to + 85°C) Options

BLOCK DIAGRAM

A
A

, E2, E3) and output enable

MCM6341

ZP PACKAGE

CASE 999–02

PIN NAMES

A Address Inputs. . . . . . . . . . . . . . . . . . . . . .

W
G
E1

, E2, E3 Chip Enable. . . . . . . . . . . . . . . .

DQ Data Input/Output. . . . . . . . . . . . . . . . .

NC No Connection. . . . . . . . . . . . . . . . . . . .

V

DD

V

SS

+ 3.3 V Power Supply. . . . . . . . . . . . .

PBGA

Write Enable. . . . . . . . . . . . . . . . . . . . . . .

Output Enable. . . . . . . . . . . . . . . . . . . . .

Ground. . . . . . . . . . . . . . . . . . . . . . . . .

DQ

DQ

E1
E2
E3

W

A
A
A
A
A
A
A

G

ROW

DECODER

INPUT

DATA

CONTROL

MEMORY MATRIX

COLUMN I/O

COLUMN DECODER

AAAAAAAA

DQ

DQ

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 2
2/18/98

 Motorola, Inc. 1998

MOTOROLA FAST SRAM

MCM6341

1

PIN ASSIGNMENT

6543217

A

NC NC

AA AA

B

NC A A E1

C
D
E

F
G

H
J

K
L
M
N
P

R
T
U

NC

DQ
DQ VDDVSSV

V

DQ

SS

DQ VDDV

V

DQ

SS

V

DQ

DD

V

V

SS

DD

V

DQ V

DD

DQ

V

SS

V

DQ V

DD

DQ

V

SS

V

DQ V

DD

DQ

NC NC

NC

AA AA

NC NC

A

E2 NC E3

SS

V

V

SS

DD

V

SS

SS

V

V

SS

DD

V

V

SS

SS

V

V

SS

DD

V

SS

SS

V

V

SS

DD

V

SS

SS

V

V

SS

DD

V

SS

SS

NC

W

AA

G

A

A

NC

V

V

DD

SS

V

V

DD

SS

V

V

DD

SS

V

V

SS

DD

V

V

DD

SS

V

V

SS

DD

V

V

DD

SS

V

V

DD

SS

V

V

DD

SS

V

V

DD

SS

V

V

DD

SS

NCNC

A

A

V

NC
DQ
DQ
DQ
DQ
DQ
DQ

DD

DQ
DQ
DQ
DQ
DQ
DQ
NC

119–BUMP PBGA

TOP VIEW

MCM6341
2

MOTOROLA FAST SRAM

TRUTH TABLE (X = Don’t Care)

E1 E2 E3 G W Mode I/O Pin Cycle Current

H X X X X Not Selected High–Z — I
X L X X X Not Selected High–Z — I
X X H X X Not Selected High–Z — I

L H L H H Output Disabled High–Z — I
L H L L H Read D
L H L X L Write High–Z Write I

out

Read I

SB1
SB1
SB1

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating

Power Supply Voltage Relative to V
Voltage Relative to VSS for Any Pin

Except V
Output Current (per I/O) I

Power Dissipation P
Temperature Under Bias Commercial

Storage Temperature — Plastic T

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

DD

exceeded. Functional operation should be restricted to RECOMMENDED OPER­ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.

SS

Industrial

Symbol Value Unit

V

DD

Vin, V

out

T

bias

stg

out

D

– 0.5 to + 5.0 V

– 0.5 to VDD + 0.5 V

± 20

1.0 W

– 10 to + 85
– 45 to + 90

– 55 to + 150 °C

mA

°C

, I

SB2

, I

SB2

, I

SB2
DDA
DDA
DDA

This device contains circuitry to protect the
inputs against damage due to high static volt­ages or electric fields; however, it is advised
that normal precautions be taken to avoid ap­plication of any voltage higher than maximum
rated voltages to these high–impedance circuits.

This CMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board and
transverse air flow of at least 500 linear feet per
minute is maintained.

MOTOROLA FAST SRAM

MCM6341

3

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

(TA = – 40 to + 85°C for Industrial Temperature Offering)

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage (Operating Voltage Range) V
Input High Voltage V
Input Low Voltage V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 2.0 ns).

**VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width ≤ 2.0 ns).

DD

IH
IL

DC CHARACTERISTICS (See Note)

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VDD) I
Output Leakage Current (E = VIH, V
Output Low Voltage (IOL = + 8.0 mA) V
Output High Voltage (IOH = – 4.0 mA) V

NOTE: E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.

= 0 to VDD) I

out

POWER SUPPLY CURRENTS (See Note)

Parameter

AC Active Supply Current MCM6341–10
(I

= 0 mA, VDD = max) MCM6341–11

out

AC Standby Current (VDD = max, E = VIH, MCM6341–10
No other restrictions on other inputs) MCM6341–11

CMOS Standby Current (E ≥ VDD – 0.2 V, Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V)
(VDD = max, f = 0 MHz)

NOTE: E1, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.

MCM6341–12
MCM6341–15

MCM6341–12
MCM6341–15

3.0 3.3 3.6 V

2.2 — VDD + 0.3** V

– 0.5*

lkg(I)

lkg(O)

OL

OH

Symbol 0 to 70°C

I

DD

I

SB1

I

SB2

— 0.8 V

— ± 1.0 µA
— ± 1.0 µA
— 0.4 V

2.4 — V

– 40 to

+ 85°C

280
275
270
260

50
50
50
45

20 20

290
285
280
270

55
55
55
50

Unit

mA

mA

mA

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V , T

Parameter Symbol Typ Max Unit

Input Capacitance All Inputs Except Clocks and DQs

Input/Output Capacitance DQ C

= 25°C, Periodically Sampled Rather Than 100% Tested)

A

E

, G, W

MCM6341
4

C

in

C

ck

I/O

4
5

5 8 pF

6
8

pF

MOTOROLA FAST SRAM

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VDD = 3.3 V ± 10%, TA = 0 to + 70°C, Unless Otherwise Noted)

(TA = – 40 to + 85°C for Industrial Temperature Offering)

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 2 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load See Figure 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

READ CYCLE TIMING (See Notes 1, 2, and 3)

MCM6341–10 MCM6341–11 MCM6341–12 MCM6341–15

Parameter Symbol

Read Cycle Time t
Address Access Time t
Enable Access Time t
Output Enable Access Time t
Output Hold from Address Change t
Enable Low to Output Active t
Output Enable Low to Output Active t
Enable High to Output High–Z t
Output Enable High to Output High–Z t

NOTES:

1. W

is high for read cycle.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.

3. E1

, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.

4. All read cycle timings are referenced from the last valid address to the first transitioning address.

5. Addresses valid prior to or coincident with E

6. At any given voltage and temperature, t
to device.

7. Transition is measured ± 200 mV from steady–state voltage.

8. This parameter is sampled and not 100% tested.

9. Device is continuously selected (E

AVAV
AVQV
ELQV
GLQV
AXQX
ELQX
GLQX
EHQZ

GHQZ

EHQZ

≤ VIL, G ≤ VIL).

Min Max Min Max Min Max Min Max

10 — 11 — 12 — 15 — ns 4

— 10 — 11 — 12 — 15 ns
— 10 — 11 — 12 — 15 ns 5
— 5 — 6 — 6 — 7 ns

3 — 3 — 3 — 3 — ns
3 — 3 — 3 — 3 — ns 6, 7, 8
0 — 0 — 0 — 0 — ns 6, 7, 8
0 5 0 6 0 6 0 7 ns 6, 7, 8
0 5 0 6 0 6 0 7 ns 6, 7, 8

going low.

max t t

ELQX

min, and t

GHQZ

max t t

min, both for a given device and from device

GLQX

Unit Notes

MOTOROLA FAST SRAM

OUTPUT

Z0 = 50

Ω

Figure 1. AC Test Load

RL = 50

VL = 1.5 V

Ω

MCM6341

5

A (ADDRESS)

READ CYCLE 1 (See Note 9)

t

t

AXQX

AVAV

Q (DATA OUT)

A (ADDRESS)

E

(CHIP ENABLE)

(OUTPUT ENABLE)

G

Q (DATA OUT)

SUPPLY CURRENT

I

DD

I

SB

HIGH–Z

t

AVQV

READ CYCLE 2 (See Notes 3 and 5)

t

AVAV

t

ELQV

t

ELQX

t

t

GLQX

t

AVQV

GLQV

DATA VALID

DATA VALIDPREVIOUS DATA VALID

t

EHQZ

t

GHQZ

MCM6341
6

MOTOROLA FAST SRAM

WRITE CYCLE 1 (W Controlled; See Notes 1, 2, 3, and 4)

MCM6341–10 MCM6341–11 MCM6341–12 MCM6341–15

Parameter Symbol

Write Cycle Time t
Address Setup Time t
Address Valid to End of W rite t
Address Valid to End of Write (G

High)
Write Pulse Width t

Write Pulse Width (G High) t

Data Valid to End of W rite t
Data Hold Time t
Write Low to Data High–Z t
Write High to Output Active t
Write Recovery Time t

NOTES:

1. A write occurs during the overlap of E

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.

3. If G

goes low coincident with or after W goes low, the output will remain in a high–impedance state.

4. E1

, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.

5. All write cycle timings are referenced from the last valid address to the first transitioning address.

6. Transition is measured ± 200 mV from steady–state voltage.

7. This parameter is sampled and not 100% tested.

8. At any given voltage and temperature, t

AVAV
AVWL
AVWH

t

AVWH

WLWH

t

WLEH

WLWH

t

WLEH

DVWH
WHDX

WLQZ

WHQX
WHAX

low and W low.

WLQZ

Min Max Min Max Min Max Min Max

10 — 11 — 12 — 15 — ns 5

0 — 0 — 0 — 0 — ns
9 — 10 — 10 — 12 — ns
8 — 9 — 9 — 10 — ns

9 — 10 — 10 — 12 — ns

8 — 9 — 9 — 10 — ns

4 — 5 — 5 — 6 — ns
0 — 0 — 0 — 0 — ns
0 5 0 6 0 6 0 7 ns 6, 7, 8
3 — 3 — 3 — 3 — ns 6, 7, 8
0 — 0 — 0 — 0 — ns

max < t

min both for a given device and from device to device.

WHQX

Unit Notes

A (ADDRESS)

E

(CHIP ENABLE)

W (WRITE ENABLE)

D (DATA IN)

Q (DATA OUT)

WRITE CYCLE 1 (W Controlled; See Notes 1, 2, 3, and 4)

t

AVAV

t

AVWH

t

WLWH

t

WLEH

t

AVWL

t

WLQZ

HIGH–Z

t

DVWH

DATA VALID

HIGH–Z

t

WHAX

t

WHDX

t

WHQX

MOTOROLA FAST SRAM

MCM6341

7

WRITE CYCLE 2 (E Controlled; See Notes 1, 2, 3, and 4)

MCM6341–10 MCM6341–11 MCM6341–12 MCM6341–15

Parameter Symbol

Write Cycle Time t
Address Setup Time t
Address Valid to End of W rite t
Address Valid to End of Write (G

High)
Enable Pulse Width t

Enable Pulse Width (G High) t

Data Valid to End of W rite t
Data Hold Time t
Write Recovery Time t

NOTES:

1. A write occurs during the overlap of E

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.

3. If G

goes low coincident with or after W goes low, the output will remain in a high–impedance state.

4. E1

, E2, and E3 are represented by E in this data sheet. E2 is of opposite polarity to E1 and E3.

5. All write cycle timing is referenced from the last valid address to the first transitioning address.

6. If E

goes low coincident with or after W goes low, the output will remain in a high–impedance condition.

7. If E

goes high coincident with or before W goes high, the output will remain in a high–impedance condition.

AVAV
AVEL

AVEH

t

AVEH

ELEH,

t

ELWH
ELEH,

t

ELWH

DVEH
EHDX
EHAX

low and W low.

Min Max Min Max Min Max Min Max

10 — 11 — 12 — 15 — ns 5

0 — 0 — 0 — 0 — ns
9 — 10 — 10 — 12 — ns
8 — 9 — 9 — 10 — ns

9 — 10 — 10 — 12 — ns 6, 7

8 — 9 — 9 — 10 — ns 6, 7

4 — 5 — 5 — 6 — ns
0 — 0 — 0 — 0 — ns
0 — 0 — 0 — 0 — ns

Unit Notes

A (ADDRESS)

(CHIP ENABLE)

E

W

(WRITE ENABLE)

D (DATA IN)

Q (DATA OUT)

WRITE CYCLE 2 (E Controlled; See Notes 1, 2, 3, and 4)

t

AVAV

t

t

AVEL

AVEH

HIGH–Z

t

ELEH

t

ELWH

t

DVEH

DATA VALID

t

EHAX

t

EHDX

MCM6341
8

MOTOROLA FAST SRAM

Motorola Memory Prefix

ORDERING INFORMATION

(Order by Full Part Number)

xCM 6341 XX XX XX

Shipping Method (PBGA Standard)

Part Number

Full Commercial Part Numbers — MCM6341ZP10

MCM6341ZP11
MCM6341ZP12
MCM6341ZP15

0.20

4X

C

E

D2

E2

B

D

D1

16X

e

6X e

TOP VIEW

A3

A2

A

Full Industrial Temperature Part Numbers — SCM6341ZP10A

P ACKAGE DIMENSIONS

ZP PACKAGE

119–PBGA

CASE 999–02

119X

b

M

0.3 CA B

M

7654321

E1

BOTTOM VIEW

0.25 A

0.35 A

0.15 A

A
B
C
D
E
F

G

H
J
K
L

M

N
P
R
T
U

0.20 A

Speed (10 = 10 ns, 11 = 11 ns, 12 = 12 ns,
15 = 15 ns)

Package (ZP = PBGA)

SCM6341ZP12A
SCM6341ZP15A

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.

2. ALL DIMENSIONS IN MILLIMETERS.

3. DIMENSION b IS THE MAXIMUM SOLDER BALL
DIAMETER MEASURED PARALLEL TO DATUM A.

4. DATUM A, THE SEATING PLANE, IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.

MILLIMETERS

DIM MIN MAX

A ––– 2.40
A1 0.50 0.70
A2 1.30 1.70
A3 0.80 1.00

D 22.00 BSC
D1 20.32 BSC
D2 19.40 19.60

E 14.00 BSC
E1 7.62 BSC
E2 11.90 12.10

b 0.60 0.90

e 1.27 BSC

A1

MOTOROLA FAST SRAM

SIDE VIEW

SEATING
PLANE

A

MCM6341

9

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

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MCM6341
10

◊

MOTOROLA FAST SRAM

MCM6341/D