Datasheet SC9270C-D Datasheet (SILAN)

Silan
Semiconductors

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SC9270C/D

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HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD



Rev: 1.1 2001.04.27

1

DTMF RECEIVER

DESCRIPTION

The SC9270C/D is a complete DTMF receiver integrating both
the bandsplit filter and digital decoder functions. The filter section
uses switched capacitor techniques for high- and low-group filters
and dial-tone rejection. Digital counting techniques are employed in
the decoder to detect and decode all 16 DTMF tone-pairs into a 4-bit
code. External component count is minimized by on-chip provision of
a differential input amplifier, clock-oscillator and latched 3-state bus
interface.

FEATURES

*Complete receiver in an 18-pin package
*Excellent performance
*CMOS, single 5 volt operation,
*Widely operating voltage: 1.2V ~ 5.25V
*Minimum board area
*Central office quality
*Low power consumption
*Power-Downmode (SC9270D only)
*Inhibit-mode (SC9270D only)

DIP-18



APPLICATIONS

*Paging systems
*Repeater systems / Mobile radio
*Credit card systems
*Remote control
*Personal computers

PIN CONFIGURATIONS

1
2
3
4
5
6
7
8

SC9270C

IN+

IN-

GS

VREF

IC*

IC*

OSCI

OSCO Q1

16
15
14
13
12
11
10

VDD

St/GT

ESt

StD

Q4

Q3

Q2

9

18
17

VSS TOE

* Connect to V

SS

1
2
3
4
5
6
7
8

SC9270D

IN+

IN-

GS

VREF

INH

PWDN

OSCI

OSCO Q1

16
15
14
13
12
11
10

VDD

St/GT

ESt

StD

Q4

Q3

Q2

9

18
17

VSS TOE

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Semiconductors

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SC9270C/D

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HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

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Rev: 1.1 2001.04.27

2

BLOCK DIAGRAM

BIAS

CIRCUIT

18 9 6

Chip power Chip bias

1
2

DIAL

TONE

FILTER

3

5

HIGH GROUP

FILTER

HIGH GROUP

FILTER

DIGITAL

DETECTION

ALGORITHM

CODE

CONVERTER

AND

LATCH

11

12

13

14

STEERING

LOGIC

16 151787 10

St
GT

Chip clock

Chip ref

Zero crossingdetectors

-

+

+

-

IN+

GS

IN-

V

DDVSS

PWDN V

REF

Q1

Q2

Q3

Q4

TOEStDEStSt/GTOSCOOSCI

4

INH

Figure 1. block diagram

ABSOLUTE MAXIMUM RATINGS

(Notes 1, 2, 3)

Characteristic Symbol Value Unit

Power Supply Voltage VDD-V

SS

6V
Voltage on any pin -- VSS-0.3 ~ VDD+0.3 V
Current at any pin -- 10 mA
Operating temperature Topr -40~+85

°C

Storage Temperature Tstg -65~+150

°C
Package power dissipation 500 mW
Note: 1. Absolute maximum ratings are those values beyond which damage to the device may occur.

2. Unless otherwisespecified, all voltages are referenced to ground.

3. Power dissipation temperature derating: -12 mV / from 65°C to 85°C

RECOMMENDED OPERATING CONDITIONS

(Note 1)

Parameter Symbol Conditions Min Typ(Note 2) Max Unit

Positive SupplyVoltages V

DD

VSS=0V 1.2 5 -- V
Oscillator Clock Frequency fc -- -- 3.579545 -- MHz
Oscillator Frequency Tolerance

∆fc

-- --

±0.1

-- %

Note: 1. Voltages are with respect to ground(Vss), unless otherwise stated.

2 .Typical figures are at 25°C and are for design aid only: not guaranteedandnot subject to production testing.

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SC9270C/D

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HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

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Rev: 1.1 2001.04.27

3

DC ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Unit

SUPPLY

Operating Supply Voltage V

DD

-- 1.2 -- 5.25 V

Operating Supply Current I

CC

-- -- 3.0 7.0 mA

Power Consumption P

O

f=3.579MHz; VDD=5V -- 15 35 mW

Standby Current I

S

PWDN pin = V

DD

-- -- 100

µA

INPUTS

Low Level Input Voltage V

IL

-- -- -- 1.5 V

High Level Input Voltage V

IH

-- 3.5----V

Input Leakage Current IIH/IILVIN=VSSor V

DD

-- 0.1 --

µA

Pull up(Source) Current I

SO

TOE(Pin 10)=0V -- 7.5 15

µA

Input Impedance (IN+, IN-) R

IN

@1kHz -- 10 --

MΩ

Steering Threshold Voltage V

TSt

-- -- 2.35 -- V

OUTPUTS

Low Level Output Voltage V

OL

No load -- 0.03 -- V

High Level Output Voltage V

OH

No load -- 4.97 --

µA

Output Low(Sink) Current I

OL

V

OUT

=0.4V 1.0 2.5 -- mA

Output High(Source) Current I

OH

V

OUT

=4.6V 0.4 0.8 -- mA

V

REF

Output Voltage V

REF

No load 2.4 -- 2.7 V

V

REF

Output Resistance R

OR

-- -- 10 --

kΩ

OPERATING CHARACTERISTICS

Gain Setting Amplifier

Parameter Symbol Conditions Min Typ Max Unit

Input Leakage Current I

IN

VSS<VIN<V

DD

--

±100

-- nA

Input Resistance R

IN

-- -- 10 --

MΩ

Input Offset Voltage V

OS

-- --

±25

-- mV
Power Supply Rejection PSRR 1kHz -- 60 -- dB
Common Mode Rejection CMRR -3.0V < VIN<3.0V --60--dB
DC Open Loop Voltage Gain A

VOL

-- -- 65 -- dB

Open Loop UnityGain Bandwidth f

C

-- -- 1.5 -- MHz

Output Voltage Sw ing V

O

RL≥100kΩ to V

SS -- 4.5 -- V

PP

Tolerable capacitive load(GS) C

L

-- -- 100 -- PF

Tolerable resistive load(GS) R

L

-- -- 50 --

kΩ

Common Mode Range V

CM

No load -- 3.0 -- V

PP

Notes : 1. All voltages referenced to VDD unless otherwise noted.

2. V

DD

=5.0V,VSS=0V,TA= 25°C .

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SC9270C/D

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HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

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Rev: 1.1 2001.04.27

4

AC CHARACTERISTICS

(All voltage referenced to Vss otherwise noted; VDD=5.0V, VSS=0V, TA=25°C,

f

CLK

=3.579545 MHz, using test circuit of figure 2 & 3. Typical figures areat 25°C and are for design aid only: not

guaranteed and not subject to production testing)

Parameter

Symbo

l

Test Conditions Min Typ Max Unit

SIGNAL CONDITIONS

-- Note:1,2,3,5,6,9,11 -- -- -40 dBm

-- Note:1,2,3,5,6,9,11 -- -- 7.75 mV

RMS

-- Note:1,2,3,5,6,9,11 +1 -- -- dBm

Valid Input Signal Levels
(each tone of composite signal)

-- Note:1,2,3,5,6,9,11 883 -- -- mV

RMS

Positive Twist Accept -- Note:2,3,6,9,11 -- 10 -- dB
Negative Twist Accept -- Note:2,3,6,9,11 -- 10 -- dB
Frequency Deviation Accept Limit -- Note:2,3,5,9,11 --

±1.5%±2Hz

-­Frequency Deviation Reject Limit -- Note:2,3,5,11 ±3.5 -- -­Thrid Tone Tolerance -- Note:2,3,4,5,9,13 -18.5 -- dB
Noise Tolerance -- Note:2,3,4,5,7,9,10 -- -12 dB
Dial Tone Tolerance -- Note:2,3,4,5,8,9,11 -- +18 -- dB

TIMING

Tone Present Detection Time tDPRefer to Fig. 4. Note:12 5 14 16 ms
Tone Absent Detection Time tDARefer to Fig. 4. Note:12 0.5 4 8.5 ms
Tone Duration Accept t

REC

User adjustable -- -- 40 ms

Tone Duration Reject t

REC

User adjustable 20 -- -- ms
Interdigit Pause Accept tIDUser adjustable -- -- 40 ms
Interdigit Pause Reject t

DO

User adjustable 20 -- -- ms

OUTPUTS

Propagation Delay (St to Q) t

PQ

TOE=V

DD

-- 8 11

µs

Propagation Delay (St to StD) t

PSED

TOE=V

DD

-- 12 --

µs

Output Data Set Up (Q to Std) t

QSED

TOE=V

DD

-- 4.5 --

µs

Propagation Delay (TOE to Q Enable) t

PTE

RL=10kΩ,CL=50pf

-- 50 -- ns

Propagation Delay (TOE to Q Disable) t

PTD

RL=10kΩ,CL=50pf

-- 300 -- ns

CLOCK

Crystal/Clock Frequency fC-- 3.5759 3.5759 3.581 MHz
Clock Input Rise Time t

LHCL

Ext. clock -- -- 110 ns
Clock Input Fall Time t

HLCL

Ext. clock -- -- 110 ns
Clock Input Duty Time DCCLExt. clock 40 50 60 %
Capacitive Load (OSCO) CLO-- -- -- 30 pf
Notes: 1. dBm = decibels above or below a reference power of 1mW into a 600 Ohm load.

2. Digit sequences consists of all 16 DTMF tones.

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SC9270C/D

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HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

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Rev: 1.1 2001.04.27

5

3. Tone duration = 40mS Tonepause = 40mS.

4. Nominal DTMFfrequencies are used.

5. Both tones in the composite signal have an equal amplitude.

6. Tone pair is deviated by ±1.5% ±2Hz.

7. Bandwidth limited (3kHz) Gaussian Noise.

8. The precise dial tone frequencies are (350Hz and 440Hz )±2%.

9. For an error rate of less than 1 in 10,000.

10. Referenced to the lowest level frequency component in DTMF signal.

11. Referenced to the minimum valid accept.

12. For guard time calculation purpose.

13. Referenced to Fig.10 Input DTMF Tone level at –25dBm(-28dBm at GS Pin) interference Frequency
Range between 480—3400Hz.

1
2
3
4
5
6
7
8

SC9270C

IN+

IN-

GS

V

REF

IC

IC

OSCI

OSCO Q1

16
15
14
13
12
11
10

V

DD

St/GT

ESt

StD

Q4

Q3

Q2

9

18
17

VSSTOE

5V

100nf

100kΩ

100kΩ

3.58MHz

300kΩ

100nf

0.1µf

Figure 2. Single ended input cofiguration

1
2
3
4
5
6
7
8

SC9270D

IN+

IN-

GS

V

REF

INH

PWDN

OSCI

OSCO Q1

16
15
14
13
12
11
10

V

DD

St/GT

ESt

StD

Q4

Q3

Q2

9

18
17

VSSTOE

5V

100nf

100kΩ

100kΩ

3.58MHz

300kΩ

100nf

0.1µf

Vin

5V

Figure 3. Single ended input cofiguration

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SC9270C/D

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HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

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Rev: 1.1 2001.04.27

6

PIN DESCRIPTION

Pin No. Pin Name I/O Description

1 IN+ I Non-Inverting input
2 IN- I Inverting input

Connections to the front-end differential amplifier.

3GS--

Gain select. Gives access to output of front-end differential amplifier for
connection of feedback resistor.

4V

REF

O

Reference voltage output, nominally V

DD

/

2. May be used to bias the inputs at

mid-rail (see application diagram).

5INHI

Inhibit (input) logic high inhibit the detection of 1633Hz internal built-in pulldown
resistor. (SC9270D only). (For SC9270C, this pin must be tied to V

SS

)

6PWDNI

Power down (input). Active highpowerdown the device and inhibitthe oscillator
internal built-in pull down resistor. (SC9270D only). (For SC9270C, this pin
must be tied to V

SS

)
7 OSC1 I Clock Input
8 OSC2 O Clock Output

3.579545MHz crystal connected between these pins
completes internal oscillator.

9VSS-- Negative powersupply, normally connected to 0V.

10 TOE I

3-state data output enable. Logic high enables the outputs Q1-Q4. This pin is
Internally pulled up.

11~14 Q1 ~ Q4 O

3-state data outputs. When enabled by TOE, provide the code corresponding to
the last valid tone-pair received (see Table 1). When TOE is logic low, the data
outputs are high impedance.

15 StD O

Delayed steering output. Presents a logic high when a received tone-pair has
been registered and the output latch updated; returns to logic low when the
voltage on St/GT falls below V

TSt.

16 ESt O

Early steering output. Presents a logic high immediately when the digital
algorithm detects a recognizable tone-pair (signal condition). Any momentary
loss of signal condition will cause ESt to return to a logic low.

17 St/GT I/O

Steering input/guard time output (bi-directional). A voltage greater than V

TSt

detected at St causes the device to register the detected tone-pair and update
the output latch. A voltagelessthan V

TSt

frees the device to accepta new tone­pair. The GT output acts to reset the external steering time-constant; its state is
a function of ESt and the voltage on St.

18 V

DD

-- Positive power supply.

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SC9270C/D

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HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

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Rev: 1.1 2001.04.27

7

TIMING DIAGRAM

AB

C

D

FGE

t

REC

t

REC

t

ID

t

DO

t

DP

t

DA

t

GTP

t

GTA

t

PQ

t

PSTD

t

PTE

t

PTD

V

Tst

EVENTS

ESt

St/GT

DATA

OUTPUTS

Q1 ~ Q4

StD

OUTPUT

TOE

TONE # n

TONE # n+1 TONE # n+1

HIGH IMPEDANCE

DECODED TONE #n+1

DECODED TONE#n

DECODED TONE #n -1

TONE DROPOUT

Vin

Figure 4. Timing diagram

EXPLANATION OF EVENTS EXPLANATIONN OF SYMBOLS

A. Short tone bursts: detected. Tone duration is invalid.
B. Tone #n is detected. Tone duration is valid. Decoded

to outputs.
C. End of tone #n is detected and validated.
D. 3 State outputs disabled (high impedance).
E. Tone #n + 1 is detected. Tone duration is valid.

Decoded to outputs.
F. Tristate outputs are enabled. Acceptable drop out of

tone #n + 1 does not negister at outputs.

G. End of tone #n + 1 is detected and validated.

Vin: DTMF composite input signal.

tREC

:Maximum DTMF signal duration not detected as

valid.

t

REC:

Minimum DTMF Signal duration required for valid
recognition.

t

ID

: Minimum time between valid DTMF signals.

t

DO

: Maximum allowabledropout during valid DTMF

signal

t

DP

: Time to detect the presence of valid DTMF signals.

t

DP

: Time to detect the absence of valid DTMF signals.

t

GTP

: Guard Time, Tone present.

t

GTP

: Guard Time, Tone absent.

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SC9270C/D

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HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

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Rev: 1.1 2001.04.27

8

FUNCTION DESCRIPTIONS

The SC9270C/D monolithic DTMF receiver offers small size, low power consumption and high performance. Its
architecture consists of a bandsplitfilter section, which separates the high and low tonesof receiver pair, followed by
a digital counting section which verifies the frequency and duration of the received tones before passing the
corresponding code to the output bus.

1. FILTER SECTION

Separation of the low-group and high-group tones is achieved by applying the dual tone signal to the inputs of two
filters a sixth order for the high group and an eighth order for the lowgroup. The bandwidths of which correspond to
the bands enclosing the low-group and high-group tones (see table 1). The filter section also in corporates notches
at 350Hz and 440 Hz for exceptional dial-tone rejection. Each filter output is followed by a second-order switched­capacitor section which smooth the signals prior to limiting. Limiting is performed by high-gain comparators which
are provided with hysteresis to prevent detection of unwanted low-level signals and noise; the outputs of the
comparators provide full-rail logic swings at the frequencies of the incoming tones.

Flow Fhigh KEY TOE Q4 Q3 Q2 Q1

697 1209 1 H 0 0 0 1
697 1336 2 H 0 0 1 0
697 1477 3 H 0 0 1 1
770 1209 4 H 0 1 0 0
770 1336 5 H 0 1 0 1
770 1477 6 H 0 1 1 0
852 1209 7 H 0 1 1 1
852 1336 8 H 1 0 0 0
852 1477 9 H 1 0 0 1
941 1336 0 H 1 0 1 0
941 1209 * H 1 0 1 1
941 1477 # H 1 1 0 0
697 1633 A H 1 1 0 1
770 1633 B H 1 1 1 0
852 1633 C H 1 1 1 1
941 1633 D H 0 0 0 0

-- -- ANY L Z Z Z Z

L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE

Table 1: Function decode table

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SC9270C/D

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HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

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Rev: 1.1 2001.04.27

9

0

10

20

30

40

50

FREQUENCY

1kHz

FREQUENCY

(dB)

PRECISE
DIAL TONES

X=350Hz
Y=440Hz

DTMF TONES
A=697Hz

B=770Hz
C=852Hz
D=941Hz
E=1209Hz
F=1336Hz
G=1477Hz
H=1633Hz

X

YABCDEFGH

Figure 5. Filter Response

2. DECODER SECTION

The decoder used digital counting techniques to determine the frequencies of the limited tones and to verify that they
correspond to standard DTMF frequencies. A complex averaging algorithm(protects) against tone simulation by
extraneous signals, such as voice, while providing tolerance to small frequency deviations and variations. This
averaging algorithm has been developed toensure an optimum combination of immunity to “talk-off”and tolerance to
the presence of interfering signals (“third tones”) and noise. When the detector recognizes the simultaneous
presence of two valid tones (referred to as “signal condition” in some industry specifications), it raises the “early
steering” flag (ESt). Any subsequent loss of signal condition will cause ESt to fall.

3. STEERING CIRCUIT

Before registration of a decoded tone-pair, the receiver
checks f or a valid signal duration (referred to as
“character- recognition-c o nd ition ”). This check is per­formed by an external RC time-constant driven by ESt. A
logic high on ESt causes V

C

(see Fig.4) to rise as the
capacitor discharges. Provided signal-condition is
maintained (ESt remains high) for the validation period
(t

GTP

), Vc reaches the threshold (V

TSt

) of the steering
logic to register the tone-pair, latching its corresponding
4-bit code (see Fig.3) into the output latch. At this point,
the GT output is activated and drives V

C

to VDD.GT

V

DD

0.1µf

V

C

R

V

DD

St/GT

ESt

StD

t

GTA

=(RC)ln( )

V

DD

V

DD-VTST

t

GTA

=(RC)ln( )

V

DD

V

TST

Figure 6. Basic steering Circuit

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continues to drive high as long as ESt remains high. Finally after a short delay to allow the output latch to settle, the
“delayed-steering” output flag, StD, goes high, signaling that a received tone-pair has been registered.The contents
of the output latch are made available on the 4-bit output bus by raising the 3-state control input (TOE) to a logic
high. The steer ingcircuit works in reverseto validate the interdigit pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver will tolerate signal interruptions (“drop-out”) too short to be
considered a valid pause. The facility, together with the capability of selecting the steering time-constants externally,
allows the designer to tailor performance to meet a wide variety of system requirements.

4. GUARD TIME ADJUSTMENT

In many situations not requiring independent selection of receive and pause, the simple steering circuit of Fig.6 is
applicable. Component values are chosen according to the following formulae:

t

REC =tDP +tGTP tID =tDA +tGTA

The value of tDP is a parameter of the device (see table) and tREC is the minimum signal duration to be recognized
by the receiver. A value for C of 0.1µF is recommended for most applications, leaving R to be selected by the
designer. For example, a suitable value of R for a t

REC of 40mS would be 300k. Different steering arrangements

may be used to select independently the guard-times for tone-present (t

GTP ) and tone-absent (tGTA ). This may be

necessary to meet system specifications which place both accept and reject limits on both tone duration and
interdigital pause. Guard-time adjustment also allows the designer to tailor system parameters such as talk off and
noise immunity. Increasing t

REC improves talk-off performance, since it reduces the probability that tones simulated

by speech will maintain signal condition for long enough to be registered. On the other hand, a relatively short t

REC

withalongtDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to
drop - outs would be required. Design information for guard-time adjustment is shown in Fig.7.

V

DD

St/GT

ESt

R1

R2

C

V

DD

St/GT

ESt

R1

R2

C

t

GTP

=(Rp C)ln( )

V

DD

V

DD-VTST

t

GTA

=(R1 C)ln( )

V

DD

V

TST

Rp=

R1R2
R1+R2

a) Decreasing t

GTP(tGTP<tGTA

)

t

GTP

=(Rp C)ln( )

V

DD

V

DD-VTST

t

GTA

=(R1 C)ln( )

V

DD

V

TST

Rp=

R1R2
R1+R2

b) Decreasingt

GTP(tGTP>tGTA

)

Figure 7. Guard time adjustment

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5. INPUT CONFIGURATION

The input arrangement of the SC9270C/D provides a differential-input operational amplifier as well as a bias source
(V

REF ) which is used to bias the inputs at mid-rail.

Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain.In a single­ended configuration, the input pins are connected as shown in Fig.2 with the op-amp connected for unity gain and
V

REF biasing the input at 1/2VDD.

Fig.8 shows the differential configuration, which permits the adjustment of gain with the feedback resistor R5.

+

-

SC9270C/D

GSR5

R4

V

REF

R2

R1C1

C2

IN+

IN-

R3

DIFFERENTIAL INPUT AMPLIFIER

C1=C2=10nF
R1=R4=R5=100k
R2=60k, R3=37.5k

R3=

R2*R5
R2+R5

All resistorsare +/- 1% tolerance
All capacitors are +/- 5% tolerance

VOLTAGE GAIN (Av diff)=

R5
R1

INPUT IMPEDANCE(Zi diff)=

2 R12+

1

C

2

Figure 8. Differential input configuration

6. POWER – DOWN AND INHIBIT MODE

A logic high applied to pin 6 (PWDN) will power the device to minimize the power consumption in a standbymode. It
stops the oscillator and the functions of the filters.
Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of 1633 Hz. The output code
will remain the same as the previous detected code (see table 2).

fLOW Fhigh KEY

TOE Q4 Q3 Q2 Q1

fLOW Fhigh KEY

TOE Q4 Q3 Q2 Q1

697 1209 1 H L L L H 697 1209 1 H L L L H
697 1336 2 H L L H L 697 1336 2 H L L H L
697 1477 3 H L L H H 697 1477 3 H L L H H
770 1209 4 H L H L L 770 1209 4 H L H L L
770 1336 5 H L H L H 770 1336 5 H L H L H
770 1477 6 H L H H L 770 1477 6 H L H H L
852 1209 7 H L H H H 852 1209 7 H L H H H
852 1336 8 H H L L L 852 1336 8 H H L L L
852 1477 9 H H L L H 852 1477 9 H H L L H
941 1336 0 H H L H L 941 1336 0 H H L H L
941 1209 * H H L H H 941 1209 * H H L H H
941 1477 # H H H L L 941 1477 # H H H L L

697 1633 A H H H L H 697 1633 A H

770 1633 B H H H H L 770 1633 B H
852 1633 C H HHHH 8521633 C H
941 1633 D H LLLL 9411633 D H

PREVIOUS DATA

-- --ANYL ZZZZ -- --ANYLZZZZ
Table 2: Truth table

INH = V

SS

(Z: high impedance) INH = V

DD

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Rev: 1.1 2001.04.27

12

6. CRYSTAL OSCILLATOR

The internal clock circuit is completed with the addition of
an external 3.579545MHz crystal and is normally
connected as shown in Figure 2. However, it i s possible
to configure several SC9270C/D devices employing only
a single oscillator crystal. The oscillator output of the first
device in the chain is coupled through a 30pF capacitor
to the oscillator input (OSCI) of the next device.
Subsequent devices are connected in a similar fashion.
Refer to Figure 9 for details. The problems associated
with unbalanced loading are not a concern with the
arrangement shown, ie: precision balancing capacitors
are not required.

C

C

X-tal

OSCO

OSCI

OSCI

OSCO

c=30pF
X-tal=3.579545MHz

To OSCIof next
SC9270C/D

Figure 9 Oscillator Connection

PACKAGE OUTLINE

DIP-18-300-2.54 UNIT: mm

6.40

2.54

3.51

5.083.30

7.62

0.25

15 degree

0.46

22.95

1.50

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