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Silan
Semiconductors
PLL FOR DTS
DESCRIPTION
The SC9257 is phase-locked loop (PLL) LSIs for digital tuning
systems (DTS) with built in 2 modulus prescalers.
All functions ate controlled through 3 serial bus lines. These LSIs
are used to configure high-performance digital tuning system.
FEATURES
* Optimal for configuring digital tuning systems in high-fi tuners
and car stereos.
* built-in prescalers. Operate at input frequency ranging from
30~150 MHz during FM
at 0.5~40MHz during AM
direct dividing).
* 16 bit programmable counter, dual parallel output phase
comparator, crystal oscillator and reference counter.
* 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz crystal oscillators can be
used.
* 15 possible reference frequencies. ( When using 4.5MHz crystal)
* Built-in 20 bit general-purpose counter for such uses as
measuring intermediate frequencies (IF
frequency pilot signal cycles (SC
* High-precision (±0.55~±7.15µs) PLL phase error detection.
* Numerous general-purpose I/O pins for such uses as peripheral
circuit control.
PIN CONFIGURATION
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
input (with 2 modulus prescaler) and
IN
input (with 2 modulus prescaler or
IN
and IF
IN1
).
IN
XT
XT
PERIOD
CLOCK
DATA
OT-1
OT-2
OT-3
OT-4
I/O - 5/CLK I/O-6
1
2
3
4
5
6
7
8
9
) and low-
IN2
SC9257
20
19
18
17
16
15
14
13
12
1110
1
SC9257
DIP-20-300-2.54
SOP-20-300-1.27
* 4 N-channel open-drain output ports
(OFF withstanding voltage:12V) for such
uses as control signal output.
* Standby mode function (turns off FM, AM
and IF amps) to save current
consumption.
* All functions controlled through 3 serial
bus lines.
* CMOS structure with operating power
supply range of VDD=5.0±0.5V.
DO2
DO1
I/O-7/SC
IN
I/O - 8/IF
IN1
I/O - 9/IF
IN2
GND
FM
IN
AM
IN
V
DD
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Semiconductors
BLOCK DIAGRAM
FM
L
1/2
OSC
CIRCUIT
FM
AMIN
DATA
CLOCK
PERIOD
AMP
IN
XT
XT
2 MODULUS
PERSCALER
HFFMH
FM
PSC
4bit SWALLOW
COUNTER
12bit PROGRAMMA BLE COUNTER
LF
MODE
REFERENCE COUNTER MAX
OSC
1ms
ADDRESS
DECODER
OUTPUT PORT
OT-1
OT-3
OT-2
4
24bit REGIST ER
24bit SHIFT REGISTE R
8
TEST
24bit REGIST ER
4
4
20bit BINARY COUNTER
UNIVERSAL COUNTER
OT-4
OT-4
12
24 22
CONTROL
XT
10
15
1ms
V
DD
POWER ON
RESET
4
5
PHASE
UNLOCK
GATE
SC9257
GND
RESET
TRI-STAT E
BUFFER
TRI-STAT E
BUFFER
COMPARATOR
OT4
5
I/O PORT
AMP
AMP
DO1
DO2
I/O-5/CLK
I/O-6
I/O-9/IF
I/O-8/IFIN1
I/O-7/SCIN
IN2
ABSOLUTE MAXIMUM RATINGS
Characteristic Symbol Value Unit
Supply Voltage VCC -0.3~6.0 V
Input Voltage VIN -0.3~VDD+0.3 V
N-ch Open-Drain Off withstanding
Voltage
Power Dissipation PD 300(200) mW
Operating Temperature T
Storage Temperature T
(Ta=25°C)
V
13 V
OFF
-40~85
OPR
-65~150
STG
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
REV: 1.0 2001.10.18
2
°C
°C
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Semiconductors
ELECTRICAL CHARACTERISTICS
Characteristic Symbol Test Condition/Pin Min Typ. Max Unit
Operating Power Supply Voltage V
Operating Power Supply Current I
Stand-by mode
Crystal Oscillation Frequency
Supply Voltage
Operating Power Supply Current I
Operating Power Supply Current I
Operating frequency range
Crystal Oscillation Frequency fXT
FM
(FMH, FML) fFM
IN
FMIN (FML) f
AMIN (HF) fHF HF mode, VIN=0.2Vp-p 1 ~ 40 MHz
AMIN (LF) fLF LF mode, VIN=0.2Vp-p 0.5 ~ 20 MHz
IF
, IF
IN1
SCIN f
Operating input amplitude range
FMIN (FMH, FML)
FMIN (FML) V
AMIN (HF) VHF HF mode, fIN=1~40MHz 0.2 ~ VDD-0.5 Vp-p
AMIN (LF) VLF LF mode, fIN=0.5~20MHz 0.2 ~ VDD-0.5 Vp-p
IF
IN1
OT1~OT4 N-ch open drain
Output Current “L” level I
OFF-leak Current I
f
IN2
, IF
V
IN2
V
V
DD1
DD1
DD2
DD2
DD3
FML
IF
SC
FM
FML
OL1
OEF
(unless otherwise specified, Ta= -40~85°C, VDD=4.5~5.58V.)
PLL operation
(normal operating)
=5.0V, XT=10.8MHz,
V
DD
FMIN=150MHz
PLL OFF
(Operating crystal
oscillation)
VDD=5.0V, XT =10.8MHz
PLL OFF
=5.0V, XT stop,
V
DD
PLL OFF
Connect crystal resonator
to XT-
FM
V
FML mode, VIN=0.3Vp-p 30 ~ 150 MHz
VIN=0.2Vp-p 0.1 ~ 15 MHz
V
square wave input.
FM
f
IN
FML mode, fIN=30~150MHz 0.3 ~ VDD-0.5 Vp-p
FIN=0.1~15MHz 0.2 ~ VDD-0.5 Vp-p
IF
VOL=1.0V 5.0 10.0 -- mA
V
terminal
XT
FML mode,
H,
=0.2Vp-p
IN
=0.7VDD, VIL=0.3VDD,
IH
FML mode,
H,
=30~130MHz
=12V -- --- 2.0
OFF
4.5 5.0 5.5 V
-- 7 15 mA
4.0 5.0 5.5 V
-- 0.8 1.5 mA
-- 120 240
3.6 ~ 10.8 MHz
30 ~ 130 MHz
-- ~ 100 kHz
0.2 ~ V
SC9257
µA
-0.5 Vp-p
DD
µA
(To be continued)
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
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Semiconductors
(Continued)
Characteristic Symbol Test Condition/Pin Min Typ. Max Unit
I/O-5~I/O-9, SCIN
“H” level V
“L” level V
“H” level IIH VIH=5V -- -- 2.0 Input Current
“L” level I
“H” level I
“L” level I
PERIOD, CLOCK, DATA
“H” level V
“L” level V
“H” level IIH VIH=5V -- -- 2.0 Input Current
“L” level I
“H” level I
“L” level I
DO1, DO2
“H” level I
“L” level I
Tri-State Lead Current ITL V
XT
“H” level I
“L” level I
Input feedback resistance
Input Feedback
Resistance
“H” level
“L” level
0.7VDD ~ VDD Input Voltage
IH1
0 ~ 0.3VDD
IL1
VIL=0V -- -- -2.0
IL
VOH=4.0V (expect SCIN) -2.0 -4.0 -- Output Current
OH4
VOL=1.0V (expect SCIN) 2.0 4.0 --
OL4
0.8VDD ~ VDD Input Voltage
IH2
0 ~ 0.2VDD
IL2
VIL=0V -- -- -2.0
IL
VOH=4.0V (DATA) -1.0 -3.0 -- Output Current
OH5
VOL=1.0V (DATA) 1.0 3.0 --
OL5
VOH=4.0V -2.0 -4.0 -- Input Current
OH3
VOL=1.0V 2.0 4.0 --
OL3
=5V, V
TLH
VOH=4.0V -0.1 -0.3 -- Output Current
OH2
VOL=1.0V 0.1 0.3 --
OL2
FMIN, AMIN, IFIN
Rf1
(Ta=25°C)
XT-
Rf2
XT
=0V -- --
TLL
(Ta=25°C)
350 700 1400
500 1000 4000
SC9257
V
µA
mA
V
µA
mA
mA
±1.0 µA
mA
kΩ
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
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Semiconductors
PIN DESCRIPTION
Pin No. Symbol Pin name Description Circuit diagram
1 XT
2
XT
Crystal oscillator
pins
Connects 3.6MHz, 4.5MHz, 7.2MHz or
10.8MHz crystal oscillator to supply
reference frequency and internal clock
SC9257
V
DD
XT XT
3 PERIOD Period signal input
4 CLOCK Clock signal input
5 DATA
6 OT-1
7 OT-2
8 OT-3
9 OT-4
10 I/O-5/CLK
11 I/O-6
13 AMIN
14 FMIN
16
17
I/O-
9/IFIN2
I/O-
8/IFIN1
Serial data
input/output
General-purpose
output ports
General-purpose
I/O ports
Programmable
counter input
General-purpose
I/O ports/General-
purpose counter
frequency
measurement
input
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
Serial I/O ports. These pins transfer
data to and from the controller to set
divisions and dividing modes, and to
control the general-purpose counter
and general-purpose I/O ports.
N channel open drain port pins, for
such uses as control signal output.
These pins are set to the OFF state
when power is turned on.
CMOS structure allows free use of
these ports for input or output. Ports
are set for input when the power is
turned on , I/O-5 can be switched for
use as a system clock output pin.
These pin input FM and AM band local
oscillator signals by capacitor
coupling. FMIN and AMIN operate at
low amplitude.
General-purpose I/O port input/output
pins. Can be switched for use as input
pins to measure general-purpose
counter frequencies. The frequency
measurement function has such uses
as measuring intermediate
frequencies (IF).
These pins feature built-in amps. Data
are input by capacitor coupling. FMIN
and AMIN operate at low amplitude.
(note) Pins are set for input when
power is turned on.
5
V
DD
Schmitt
input
DATA
N-channel open drain
V
DD
CLOCK,PERIOD
V
DD
(To be continued)
REV: 1.0 2001.10.18
Schmitt input
V
DD
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Semiconductors
(Continued)
Pin No. Symbol Pin name Description Circuit diagram
18
19 DO1
20 DO2/OT-4
15 GND
12 VDD
I/O-
7/SCIN
General-purpose
I/O ports/
General-purpose
counter cycle
measurement
input
Phase comparator
output (General-
purpose output
ports)
Power supply pins
General-purpose I/O port input/output
pin. Can be switched for use as signal
input pin to measure low-frequency
signal cycles.
(note) This pin is set for input when
power is turned on.
These pins are for phase comparator
tri-state output. DO1 and DO2 are
output in parallel.
Applies 5.0V±10%
SC9257
V
DD
VDD
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Semiconductors
FUNCTION DESCRIPTION
Serial I/O ports
As the block diagram shows, the functions are controlled by setting data in the 48 bits contained in each of the 2
sets of 24 bit registers. Each bit of data in these register is transferred through the serial ports between the
controller and the DATA, CLOCK and PERIOD pins. Each serial transfer consists of a total of 32 bits, with 8
address bits and 24 data bits.
Since all functions are controlled in units of registers, the explanation in this manual focuses on the 8 bit address
and functions of each register.
These registers consist of 24 bits and are selected by an 8 bit address.
A list of the address assignment for each register is given below under register assignments.
Register Address Contents of 24 bits No. of bit
PLL divisor setting
Input
register 1
Input
register 2
Output
register 1
Output
register 2
When the PERIOD signal falls, the input data are latched in register 1 or register 2 and the function is performed.
When the CLOCK signal falls for 9 time, the output data are latched in parallel in the output registers. The data
are subsequently output serially from the data pin.
D0H
D2H
D1H
D3H
Reference frequency setting
PLL input and mode setting
Crystal oscillator selection
General=purpose counter control (including lock detection bit
control)
I/O port and general-purpose counter switching bits
I/O-5/CLK pin switching bit
DO pin control
Test bit
I/O port control (also used as general-purpose counter input
selection bits)
Output data
General-purpose counter numeric data
Not used
Lock detection data
I/O port control data
Output data
Input data (undefined during output port selection)
Not used
SC9257
16
4
2
2
total 24
4
3
1
1
1
5
9
total 24
22
2
total 24
5
5
4
5
5
total 24
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
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Semiconductors
REGISTER ASSIGMENTS
Address=D0H
LSB
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R0 R1 R2 R3 MODEFM OSC1 OSC2
Input regi sters
Address=D2H
G0 G1 SC IF1 IF2 CLK DOHZ
Gate
time
select
Address=D1H
LSB
f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 BUSYOVER "0" "0"
Input regi sters
Address=D3H
ENA-
BLE
I/O port
and general -purpose
counter switching bits
UN
PE1 PE2 PE3 "0" "0" "0" "0" C5 C6 M7 M8 M9 O1 O2 O3 O4 I5 I6 I8I7 I9"0"
LOCK
Lock detection data Not used I/O port control data Ou tput data Input data
CLK
bit
Program mable counter data
RESET S TART
RESET
TEST
bit
DOHZ
START
bit
bit
(*2)
C5 C6 M7 M8 M9 O1 O2 O3 O4 O5 O6 O8O7 O9TEST
bit
General-purpose counter data
Also used as
counter in put
selection bits
I/O port c ontrol
generalpurpose
Reference
frequency
code data
Output port output data
SC9257
LSB
mode
Crystal
oscill ator
selection bits
Not
used
Programmable
counter
When power is turned on, the input registers are set as shown below.
Address=D0H
LSB
(*1) (*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)1111 1100
(*1)
Input registers
Address=D2H
000000000 00000000000 0000
Note: 1. Data are undefined.
2. Set data to “0” for test bit.
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MSB
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Semiconductors
Serial transfer format
The serial transfer format consists of 8 address bits and 24 data bits (Fig. 1). Addresses D0H~D3H are used.
PERIOD
CLOCK
DATA
•
Serial data transfer
serial data are transferred in sync with the clock signal. In the idlestate, the PERIOD, CLOCK and DATA pin
lines are all set to “H” level. When the period signal is at “L” level, the falling of the clock signal initiates serial
data transfer. Data transfer ceases when the period signal is set to “L” level when the clock signal is at “H” level.
Once serial data transfer has begun, however, no more than 8 falls of the clock signal can occur during the time
the period signal is at “L” level.
Since the receiving side receives the serial data as valid data when the clock signal rises, it is effective for the
sending side to produce output in sync with the clock signal fall.
To receive serial data from the output registers (D1H, D3H), set the serial data output to high impedance after
the 8 bit address is output but before the next clock signal falls.
Data reception subsequently continues until the period signal becomes “L” level; data transfer ends just before
the period signal rises. Therefore, the data pin must have an open-drain or tristate interface.
Note: 1. when power is turned on, some internal circuit have undefined states. To set internal circuit states,
execute a dummy data transfer before performing regular data transfer.
2. times t1~t8 have the following value:
t1≥1.0µs
t2≥1.0µs
t3≥0.3µs
t4≥0.3µs
t5≥0.3µs
t6≥1.0µs
t7≥1.0µs
t8≥0.3µs
3. Asterisks represent numbers taken from addresses, as in D*H.
Start
t3
t4
t1 t2
t8
(*)(*)0010 11
LSB
8 address bits
Fig.1
t5
9 clock signal fall
MSB LSB
24 data bits
(24bit register)
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
9
SC9257
End
t6
t7
MSB
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Semiconductors
Crystal oscillator pins (XT, XT)
As fig.2 shows, the clock necessary for internal operation is produced by connecting a crystal oscillator between
capacitors. Use the crystal oscillator selection bit to select an oscillating frequency of 3.6MHz, 4.5MHz, 7.2MHz or
10.8MHz which matches that of the crystal oscillator used.
SC9257
LSB MSB
Address D0H
OSC1 OSC2
00
01
01
11
XT XT
CCX'tal
Note: set to 3.6MHz (OSC1=”0” and OSC2=”0”) when power is turned on. The crystal is not oscillating at this time
because the system is in standby mode.
OSCILLATOR
FREQUENCY
3.6MHz
4.5MHz
7.2MHz
10.8MHz
Divider
C=30pF Typ.
Fig.2
OSC1 OSC2
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Semiconductors
Reference counter (Reference frequency divider)
The reference counter section consists of a crystal oscillator and a counter.
A crystal oscillator frequency of 3.6MHZ, 7.2MHZ or 10.8MHZ can be selected .A maximum of 15 reference
frequencies can be generated.
1. Setting reference frequency
The reference frequency is set using bits R0~R3.
LSB MSB
Address D0H
R1R0
SC9257
R3R2
R0 R1 R2 R3
0000
0001
0100
1100
0010
1010
0110
1110
(Note 1) Reference frequencies marked with an asterisk “*”can only be generated with a 4.5MHZ crystal oscillator.
(Note 2) (*1)Standby mode
Standby mode occurs when bits R0,R1,R2,and R3 are all set to “1”.In standby mode, the programmable
counter stops, and FM, AM and IFIN(when selected IFIN) are set to “amp off” state (pins at “L” level). This
saves current consumption when the radio is turned off. The DO pins become high impedance during
standby mode.
During standby mode, the I/O ports (I/O-5~I/O-9) and output ports (OT1~OT4) can be controlled and the
crystal oscillator can be turned on and off.
(Note 3) The system is set to standby mode when power is turned on. At this time, the crystal oscillator is not
oscillating and the I/O ports are set to input mode.
REFERENCE
FREQUENCY
0.5 KHz
1 KHz
2.5 KHz
3 KHz
3.125 KHz
*3.90654 KHz
5 KHz
6.25 KHz
R0 R1 R2 R3
0001
1001
0101
1101
0011
1011
0111
1111
REFERENCE
FREQUENCY
*7.8125 KHz
9 KHz
10 KHz
12.5 KHz
25 KHz
50 KHz
100 KHz
Standby mode (*1)
Programmable counter
The programmable counter section consists of a 1/2 prescaler, a 2 modulus prescaler and a 4bit +12bit
programmable binary counter.
1. Setting programmable counter
16 bits of divisor data and 2 bits, which indicate the dividing mode, are set in the programmable counter.
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
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Semiconductors
(1) Setting dividing mode
The FM and MODE bits are used to select the input pin and the dividing mode (pulses wallow mode or
direct dividing mode). There are 4 possible choices, shown in the table below .Select one based on the
frequency band used.
LSB MSB
Address D0H
SC9257
FM MO DE
MODE FM
LF
HF
L
FM
FMH
0
0
1
1
MODE
DIVIDING MODE
Direct dividing mode
0
1
Pulse swallow mode
0
1/2 + pulse swallow
1
mode
TYPICAL
RECEIVING BAND
LW,MW,SWL
SWH
FM
FM
INPUT FREQUENCY
RANGE
0.5 ~ 20MHz
1 ~ 40MHz
30 ~ 130MHz
30 ~ 150MHz
30 ~ 130MHz
(2) Setting divisor
The divisor for the programmable counter is set as binary data in bits P0~P15.
• Pulse swallow mode (16 bits)
LSB MSB
Address D0H
P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P 15
0
2
2
15
Divisor setting range (pulse swallow mode):n=210H~FFFH (528~65535)
(Note) With the 1/2+pulse swallow mode, the actual divisor is twice the programmed value.
• Direct dividing mode (12 bits)
LSB MSB
Address D0H
P0 P1 P2 P3
Don't care
P4 P5 P6 P7 P8 P 9 P10 P11 P12 P13 P14 P15
0
2
11
2
Divisor setting range (direct dividing mode):n=10H~FFFH(16~4095)
With the direct dividing mode, data p0~p3 are don’t-care and bit p4 is the LSB.
INPUT
PIN
AMIN
FMIN
FREQUENCY
n
2n
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Semiconductors
2. Prescaler and programmable counter circuit configuration
(1) Pulse swallow mode circuit configuration
PSC
SC9257
P0-P3
FM
FM
IN
AM
IN
This circuit consists of a 2 modulus prescaler, a 4 bit swallow counter and a 12bit programmable counter.
During FM
(2) Direct dividing method circuit configuration
With the direct dividing mode, the prescaler section is bypassed and the 12bit programmable counter is used.
(3) Both FM
low amplitude.
IN(FMIN mode),a 1/2 prescaler is added to the preceding step.
AM
IN
IN and AMIN have built-in amps. Data are input by capacitor coupling. FMIN and AMIN operate at
1/2
FM
HF
L
Amp
H
FM,MODE
Prescaler section
12bit program counter
2 modulus
prescaler
Fig.3
Preset
P4-P15
Fig.4
4bit swallow counter
Preset
12bit programmable counter
P4-P15
To phase comparator
To phase
comparator
General-purpose counter
The general-purpose counter is a 20bit counter. It has such uses as counting AM/FM band intermediate
frequencies (IF) and detecting auto-stop signals during auto-search tuning. It also features a cycle measurement
function for such uses as measuring low-frequency pilot signal cycles.
1. General-purpose counter control bits
(1) Bits G0 and G1 … Used for selecting the general-purpose counter gate time.
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Semiconductors
LSB MSB
Address D2H
G0 G1
SC9257
G0 G1 GATE TIME
00
01
1ms
01
4ms
16ms
11
64ms
CYCLE MEASUREMENT
PULSE
50 KHz
150 KHz
900 KHz
Crystal oscillator frequency
(2) Bits SC,IF1 and IF2 …I/O port and general-purpose counter switching bits.
(*) The functions of the following pins are switched by data.
LSB MSB
Address D2H
sc IF1 IF2
SC
1
0
I/O-7/SC
SC
IN
I/O-7
I/O-8/IF
SC
I/O-8
IN1
IN
IN
IF1
1
0
IF2
I/O-9/IF
IN2
1
0
IF
IN2
I/O-9
(3) Bits M7, M8 and M9 … M7 sets the state for pin I/O-7/SCIN, M8 sets the state for pin I/O-8/IFIN1; M9, for
pin I/O-9/IFIN2.
These operations are valid when bits SC, IF1 and IF2 are all set to 1.
LSB MSB
Address D2H
M7 M9M8
M7 M8
00
(*)
(*) 1
1
M9
0
(*) 1
0
00
Note: Bits marked with an asterisk “(*)” are don’t care
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
PIN STATES (When bits sc, IF1 and IF2 are all set to "1")
SC
IN
INPUT disabled
INPUT enabled
IF
IN1
INPUT pulled down
INPUT enabled
INPUT pulled down
INPUT pulled down
INPUT enabled
INPUT pulled down
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IF
IN2
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Semiconductors
(4) Bits f0~f9…The general-purpose counter results can be read in binary from bits f0~f9 of the output register
(D1H).
LSB MSB
Address D1H
0
2
General-purpose counter data
(5) OVER and BUSY bits…Detect the operating state of the general-purpose counter.
Addres s D1H MSB
BUSYOVER
"0" "0"
f12 f14f13f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f15 f16 f17 f18 f19
BIT DATA = "1" BIT DATA = "0"
SC9257
OVER BUSY
"0" "0"
19
2
General-purpose counter
option monitor bit
General-purpose counter
overflow detection bit
General-purpose counter
busy
Counted value in generalpurpose counter
20
2
(Overflow state)
General-purpose counter
ended counting
Counted value in generalpurpose counter
20
2
-1
Note: When using the general-purpose counter, before referring to the contents of the general-purpose counter
result bit (f0~f9), confirm that the busy bit is “0” (counting is ended) and the OVER bit is “0” (general-purpose
counter data are normal).
(6) START bit…When the data are set to “1”, the general-purpose counter is reset then counting begins.
LSB MSB
Address D2H
start
01Counting continues uninterrupted.
Counting begins after general - purpose counter is reset.
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Semiconductors
2. General-purpose counter circuit configuration
The general-purpose counter section consists of input amps, a gate time control circuit and a 20 bit binary counter.
SC9257
IF
IN1
IF
IN2
SC
IN
(CMOS input)
Amp
Cycle measurement
pulse
SCIF1
IF2
START G0 G1
3. General-purpose counter measurement timing
PERIOD
IF
IN1
OR
IN2
IF
BUSY bit
Gate
End
T1
START bit set to "1"
T2
20bit binary counter Overflow detection
Gate
Gate time control circuit
Fig.5
PERIOD
IN
SC
BUSY
bit
Gate
f0-f19
T1
f
XT
BUSY
End
START bit set to "1"
OVER
Binary
counter
input
Clock pulse to be measured
Binary
counter
input
Reference clock pulse
Frequency measurement timing chart Cycle measurement timing chart
0<T1≤0.25(µs), 0<T2 ≤1 (ms)
Note: 1. IFIN1 and IFIN2 input have built-in amps. Data are input by capacitor coupling. FMIN and AMIN operate
at low amplitude.
2. SCIN is configured for CMOS input, so input signals should be logic level.
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Semiconductors
General-purpose I/O ports
These LSIs feature general-purpose output and I/O ports which are controlled through the serial ports.
Input/output form port Input/output configuration
Output port Dedicated: 4 ports N channel open-drain output
I/O ports Dedicated: 1 port,
Maximum: 5 ports
General-purpose output ports (OT-1~OT-4)
1.
Pins OT-1~OT-4 are general-purpose dedicated output ports. They have such uses as control signal output.
They are configured for N channel open-drain output and have an off withstanding voltage of 12V.
The data set in bits O1~O4 of the input register (D2H) are output in parallel from their correspond dedicated
output port pins OT-1~OT-4.
The data set in bits O1~O4 of the input register (D2H) can also be read from the DATA pins as output register
(D3H) serial data O1~O4.
(1) SC9257
LSB MSB
Address D2H
CMOS input/output
O3
SC9257
O4O2O1
O1~O4
0
1
(2)output register … The data set in bits O1~O4 of the input register can read as serial data O1~O4 from the output
register (D3H).
LSB MSB
Address D2H
LSB MSB
Address D3H
PIN OUTPUT STATE
OT-1~OT-4
High impedance
(N channel open drain output =off)
"L" level
(N channel open drain output =on)
O3 O4O2O1
O3 O4O2O1
Input
register
Output
register
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Semiconductors
2. General-purpose I/O ports (I/O-5~I/O-9)
Pins I/O-5~ I/O-9 are general-purpose I/O ports used for control signal input and output. They are configured
for CMOS input and output.
These I/O ports are set for input or output using bits C5, C6 and M7~M9 of the input register (D2H).
Setting bits C5, C6 and M7~M9 to “0” sets these ports for input. Data which are input in parallel from I/O-
5~I/O-9 are latched in the internal register on the ninth fall of the serial clock signal. These data can then be
read as serial data I5~I9 from the DATA pins.
Setting bit C5, C6 and M7~M9 to “1” sets these ports for output.
Data which are set in bits O5~O9 of the input register (D2H) are output in parallel from their corresponding
general-purpose I/O port pin I/O-5~I/O9.
These operations are valid when bits SC, IF1, IF2 and CLK are all set to “0”.
(1) SC9257
LSB MSB
Address D2H
SC
IF1
IF2
"0"
CLK
"0"
"0"
"0"
C5 C6 M7 M8 M9
SC9257
C5,C6
M7~M9
0
1
PIN INPUT /OUTPUT STATE (When SC,IF1 and IF2 are "0")
I/O -5~I/O -9
Input port
Output port
• Setting data for output ports
LSB MSB
Address D2H
SC
"0"
O5~O9
IF1
IF2
CLK
"0"
"0"
"0"
C5
"1"C6"1"M7"1"M8"1"M9"1"
O9O8O7O6O5
PIN OUTPUT STATE (When SC,IF1 and IF2 are "0")
I/O -5~I/O -9
0
1
"L"level
"H"level
Note: On the SC9257, pins I/O-7~I/O-9 also serve as general-purpose counter input pins. Therefore, bits SC, IF1
and IF2 of the input register (D2H) must be set to “0” when pins I/O-7~ I/O-9 are used for I/O ports. Since
pin I/O-5 also serves as the CLK pin, the CLK bit of the input register (D2H) must be set to “0” when pin I/O-
5 is used as an I/O port.
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Semiconductors
(2) Output register… Data which ate set in bits C5, C6 and M7~M9 of the input register (D2H) can be read as serial
data C5, C6 and M7~M9 from the output register (D3H).
LSB MSB
Address D2H
LSB MSB
Address D3H
Data which are input in parallel from pins I/O –5~I/O-9 can be read as serial data I5~I9 from the output register
(D3H)
LSB MSB
Address D3H
C5 C6 M7 M8 M9
C5 C6 M7 M8 M9
SC9257
Input register
Output register
I9I8I7I6I5
I/O-7I/O-5 I/O-6 I/O-8 I/O-9
Input data
Input register
INPUT PORTS
(I/O-5 ~ I/O-9)
"L" level
"H" level
BIT DATA
(15-19)
0
1
Note: 1. When pins I/O-5~I/O-9 are used for output, the data in I5~I9 of the output register(D3H) are undefined..
2.When power is turned on, input register (D2H) I/O port control bits C5, C6 and M7~M9 and output data
bits O5~O9 are set to “0”. General-purpose I/O ports are set as input ports. Pins which are used both as
general-purpose I/O ports and for general-purpose counter input are set for I/O port input. The output
state of general-purpose output ports is set to high impedance (N channel open drain output =off).
A typical example of data setting for general-purpose counter and I/O port use is shown below.
LSB MSB
Address D2H
SC
IF1
"0"
"1"
PIN NAME
Pin function
Pin input/
output state
IF2
"1"
I/O-7/SC
I/O-7
Output port
M7
"1"M8"1"M9"0"
IN
I/O-8/IF
IF
Input
enable
IN1
IN1
I/O-9/IF
IN2
IF
IN2
Input pulled
down
As shown above, the pins can be switched as necessary to enable use as an I/O port or general-purpose counter.
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Semiconductors
Phase comparator
The phase comparator outputs the phase error after comparing the phase difference of the reference frequency
signal supplied by the reference counter and the divided output from the programmable counter. The frequencies
and phase differences of these two signals are then equalized by passing them through low-pass filters. These
signals then control the VCO.
The filter constants can be customized for FM and AM bands since the signals are output in parallel from the
phase comparator then pass through the two tristate buffer pins, DO1 and DO2.
Reference frequency signal
Programmable
counter output
R
S
phase
comparator
Fig.7
DD
V
DO1
L.P.F
V
DD
DO2
L.P.F
CC
V
SC9257
FM
VCO
AM
VCO
DO
R
S
Low level
floating
High level
R1
DO
Standard
Tr1:2SC1815
Tr2:2SK246
R2
Tr1
DO Output Timing Chart
Typical Active Low-Pass Filter Circuit
Fig.8
L
R
C
R3
To VCO varactor diode
Tr2
Typical low-pass filter constants
(FM band reference values)
C=0.33
R1=10K
R2=8.2K
R3=330
RL=10K
F
Fig.9
The figures above show the DO output timing chart and a typical active low-pass filter circuit featuring a
Darlington connection between the FET and transistor.
The filter circuit shown above is just one example. Actual circuits should be designed based on the band
composition and the properties desired from the system.
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Semiconductors
Lock detection bits
The lock detection bits detect locked states in the PLL system. These systems have an unlock detection bit (unlock
bit) which is used to detect, using the reference frequency cycle, the phase difference between the reference
frequency and divided output of programmable counter. These systems also have phase error detection bits ( bits
PE1~PE3), which are capable of more precise detection (±0.55µs~±7.15µs).
1. Unlock detection bit (UNLOCK)
This bit detects, using the reference frequency cycle, the phase difference between the reference
frequency and the divided output of the programmable counter. When there is no lock, that is, when the
reference frequency and the divided output of the programmable counter are not the same, unlock F/F is set.
Unlock F/F is reset every time the input register (D2H) unlock reset bit (RESET) is set to “1”. After unlock
F/F has been reset in this way, locked state can detected by checking the unlock detection bit (UNLOCK) of
the output register (D3H). After unlock F/F has been reset, the unlock detection bit must be checked after a
time interval exceeding that of the reference frequency cycle has elapsed. This is because the reference
frequency cycle inputs the lock detection strobe to unlock F/F. If the time interval is short, the correct locked
state cannot be detected. Therefore, the output register (D3H) has a lock enable bit (ENABLE). This bit is
reset every time the input register (D2H) reset bit is set to “1”, and set to “1” through the lock detection timing.
That is, the locked state is correctly detected when the lock enable bit (ENABLE) is “1”.
Reference frequency
SC9257
Programmable
counter output
DO output
Phase comparator
Lock detection strobe
Unlock is reset (RESET)
Unlock F/F (UNLOCK)
Lock enable (ENABLE)
Phase error detection
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
Counts phase difference.
Fig.10
21
High impedance
"L" level
"H" level
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Address D2H
Address D3H
Silan
Semiconductors
LSB MSB
LSB MSB
ENA-
BLEUNLOCK
RESET
Setting data to "1" resets unlock detection bit and lock enable bit.
SC9257
Input register
Output register
10PLL lock detection enabled
PLL lock detection in waiting
state
Note: The asterisk (*) indicates an error state of over 180° phase difference relative to the reference frequency
2. Phase error detection bits (PE1~PE3)
The unlock bit detects, using the reference frequency cycle, the phase difference between the reference
frequency and the divided output of the programmable counter. The phase error detection bits (bits PE1~PE3)
are capable of precise phase error detection of ±0.55µs~±7.15µs using the reference frequency cycle.( If the
UNLOCK bit is set to “1” and the phase difference relative to the reference frequency is over 180°, bits
PE1~PE3 cannot correctly detect the phase error. Therefore, bits PE1~PE3 are normally used when the
UNLOCK bit is set to “0”.) Bits PE1~PE3 detect phase error normally when the phase difference is -180°~180°
relative to the reference frequency cycle.
LSB MSB
Address D3H
PE1
PE2 PE3
PE1 PE2 PE3
000
001
010
011
100
110
110
111
0.55sPE<1.65s
2.75sPE<3.85s
3.85sPE<4.95s
4.95sPE<6.05s
6.05sPE<7.15s
7.15sPE
10PLL in unlocked state(*)
PLL in locked state
PHASE ERROR (PE)
0.55s
PE<
1.65s PE<2.75s
The phase error data can be read from the output register (D3H) as serial data PE1~PE3.
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
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Semiconductors
Following is a typical lock detection operation. It shows the operation flow from locked state to frequency change
with a phase error greater than ±6.05µs.
Frequency change
WAIT
Phase error detection start
Reset bit 1
SC9257
Time interval exceeding that of
reference frequcncy cycle
detection bits PE1,PE2
NO
PE1=1,PE2=0,PE3=1?
Phase error=greater than 4.95s
and less than
WAIT
ENABLE=1?
YES
UNLOCK bit =0?
YES (Lock)
Check phase error
and PE3
YES
6.05s
Fig.11
NO
NO (UNLOCK)
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Semiconductors
Other control bits
CLK and C5 bits…Control bits which switch the function for the I/O-5/CLK pin.
1.
(1) The CLK bit controls switching of the I/O-5/CLK pin and CLK pin.
When bits R0~R3 of the input register (D0H) are all set to “1” (standby mode)
LSB MSB
Address D2H
CLK C5
SC9257
CLK C5
00
10
1
0
11
I/O port
CLK output
I/O-5/ CLK PIN STATE
Input port
Output port
System clock off
(CLK at "L" level)
System clock output(*)
CRYSTAL OSCILLATOR
CIRCUIT STATE
Oscillator circuit off
Oscillator circuit on
When one of bit R0~R3 of the input register (D0H) is set to “0” (not standby mode)
LSB MSB
Address D2H
CLK C5
CLK C5
00
10
10
11
I/O port
CLK output
I/O-5/ CLK PIN STATE
Input port
Output port
System clock output(*)
CRYSTAL OSCILLATOR
CIRCUIT STATE
Oscillator circuit on
Note: The system clock output marked with an asterisk “(*)” refers to output of the crystal oscillator
frequencies listed below.
Crystal oscillator (MHz) System clock (kHz) Duty (%)
10.8
7.2
3.6
600
50
4.2 750
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Semiconductors
DOHZ bit…controls the DO2 pin output state.
2.
LSB MSB
Address D2H
3. TEST bit… Data should normally be set to “0”.
DOHZ
DO2 output in normal operation
0
(phase comparison error output)
1
DO2 output fixed at high impedance
SC9257
Address D2H
LSB MSB
TEST
"0"
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
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ELECTRICAL CHARACTERISTICS CURVE
SC9257
AMIN(LF) Frequency Characteristics
1414
1000
500
200
106
71
50
20
10
5
INPUT LEVEL (mVrms)
2
1
0.1 0 .2 0.5 1 2 5 2010 50 100
INPUT FREQUENCY (MHz)
AMIN(HF) Frequency Characteristics
1414
1000
500
200
106
71
50
20
10
5
INPUT LEVEL (mVrms)
2
1
0.1 0.2 0.5 1 2 5 2010 50 100
INPUT FREQUENCY (MHz)
(Note)
Operating Guarantee Range
VDD=4.5~5.5v,Ta = -40 ~ 85)
Standard Characteristics(V
40
DD
= 5V,Ta =25)
FMIN(LF) Frequency Characteristics
1414
1000
500
200
106
71
50
20
10
5
INPUT LEVEL (mVrms)
2
1
40 60 80 100 120 140 160 180 200
020
INPUT FREQUENCY (MHz)
IFIN(LF) Frequency Characteristics
1414
1000
500
200
106
71
50
20
10
5
INPUT LEVEL (mVrms)
2
1
0.05 0.1 0.2 0.5 1 2 5 10 5015 20
INPUT FREQUENCY (MHz)
(Note)
+
Standard Characteristics(V
FMIN:FM
FMIN:FM
H
Operating Guarantee Range
(V
DD
=4.5~5.5v,Ta = -40 ~ 85)
L
DD
= 5V,Ta =25)
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
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Semiconductors
APPLICATION CIRCUIT
C
MicroController
PERIOD
CLOCK
DATA
CX'tal
HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD
V
1
2
3
4
5
6
7
8
9
20
19
18
F
0.01
17
F
0.01
16
SC9257
15
14
13
12
4.7
1110
4
F 0.1F
2
0.001F
0.01F
SC9257
CC
5Vtyp.
12V max.
Varator Diode
AM
VCO
AM
VCO
SCIN signal
IF
signal
AM
FM
IF
signal
I/O Port
Output Port
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7.62
Semiconductors
PACKAGE OUTLINE
DIP20-P-300-2.54 UNIT: mm
2.54
7.62
6.40B0.2
25.1
24.6B0.2
1.40B0.1
SC9257
+0.1
-0.05
0.25
o
15
3.5B0.2
B
4.15B0.33.30B0.3
SOP20-P-300-1.27 UNIT: mm
5.3B0.2
7.62 (300mil)
1.27
13.3
12.8B0.2
0.43B0.1
1.5B0.2
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