Datasheet SC9256, SC9256S Datasheet (SILAN)

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PLL FOR DTS

DESCRIPTION

The SC9256 is phase-locked loop (PLL) LSIs for digital tuning

systems (DTS) with built in2 modulus prescalers.

ll functions ate controlled through 3 serial bus lines. These LSIs

are used to configure high-performance digital tuning system.

FEATURES

* Optimal for configuring digital tuning systems in high-fi tuners

and car stereos.

* built-in prescalers. Operate at input frequency ranging from

30~150 MHz during FM
at 0.5~40MHz during AM
direct dividing).

* 16 bit programmable counter, dual parallel output phase

comparator, crystal oscillator and reference counter.

* 3.6MHz, 4.5MHz, 7.2MHz or 10.8MHz crystal oscillators can be

used.
* 15 possible reference frequencies. ( When using 4.5MHz crystal)
* Built-in 20 bit general-purpose counter for such uses as

measuring intermediate frequencies (IF
* High-precision (±0.55~±7.15µs) PLL phase error detection.
* Numerous general-purpose I/O pins for such uses as peripheral

circuit control.
* 3 N-channel open-drain output ports (OFF withstanding

voltage:12V) for such uses as control signal output.

PIN CONFIGURATION

input (with 2 modulus prescaler) and

IN

input (with 2 modulus prescaler or

IN

IN1

and IF

IN2

)

SC9256

DIP-16-300-2.54

SOP-16-300-1.27

* Standby mode function (turns off FM, AM

and IF amps) to save current
consumption.

* All functions controlled through 3 serial

bus lines.

* CMOS structure with operating power

supply range of V

ORDERING INFORMATION

Device Package

SC9256 DIP-16-300-2.54

SC9256S SOP-16-300-1.27

=5.0±0.5V.

DD

1

XT

2

XT

DATA

OT-1
OT-2
OT-3

3
4
5
6
7
8

SC9256

PERIOD

CLOCK

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16
15
14
13
12
11
10

9

DO2/OT-4
DO1

IN1

I/O-5/IF
I/O-6/IF

IN2

GND
FM

IN

AM

IN

V

DD

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BLOCK DIAGRAM

FM

L

1/2

OSC

CIRCUIT

H

FM

AM

DATA

CLOCK

PERIOD

AMP

IN

IN

XT

XT

2 MODULUS

PERSCALER

HFFM

FM

1ms

OUTPUT PORT

OT-1 OT-2 OT-3



PSC

4bit SWALLOW

COUNTER

12bit PROGRAMMABLE COUNTER

LF

MODE

4

REFERENCE COUNTER MAX

OSC

24bit REGISTER

24bit SHIFT REGISTER

8

4

TEST

24bit REGISTER

4

ADDRESS
DECODER

12

15

24 22

10

20bit BINARY COUNTER

UNIVERSAL COUNTER

CONTROL

XT

1ms

V

DD

POWER ON

RESET

4

5

PHASE

UNLOCK

GATE

SC9256

GND

RESET

TRI-STATE

BUFFER

TRI-STATE

BUFFER

COMPARATOR

OT4

5

I/O PORT

AMP

AMP

DO1

DO2/OT-4

I/O-6/IF

I/O-5/IF

IN2

IN1

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Value Unit

Supply Voltage V
Input Voltage V
N-ch Open-Drain Off withstanding Voltage V
PowerDissipation P
Operating Temperature T
Storage Temperature T

( ): Flat package

(Ta=25°C)

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2

CC

IN

OFF

D
OPR
STG

-0.3~6.0 V

-0.3~VDD+0.3 V
13 V

300(200) mW

-40~85

-65~150

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°C

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ELECTRICAL CHARACTERISTICS

Characteristic Symbol Test Condition/Pin Min Typ. Max Unit

Operating Power Supply Voltage V

DD1

(unless otherwise specified, Ta= -40~85°C, VDD=4.5~5.58V.)

PLL operation
(normal operating)

4.5 5.0 5.5 V

SC9256

Operating Power Supply Current I

Stand-by mode
Crystal Oscillation Frequency

Supply Voltage

Operating Power Supply Current I

Operating Power Supply Current I
Operating frequency range
Crystal Oscillation Frequency f

FMIN(FMH,FML)f

FMIN(FML)f
AMIN(HF) f
AMIN(LF) f
IF

,IF

IN1

IN2

SC

IN

Operating input amplitude range
FMIN(FMH,FML)

FMIN(FML)V
AMIN(HF) V
AMIN(LF) V
IF

,IF

IN1

IN2

OT1~OT4 N-ch open drain
Output Current “L” level I
OFF-leak Current I

V

V

VDD=5.0V, XT=10.8MHz,

DD1

FMIN=150MHz

PLL OFF
(Operating crystal

DD2

oscillation)
VDD=5.0V, XT =10.8MHz

DD2

PLL OFF
VDD=5.0V, XT stop,

DD3

PLL OFF

Connect crystal resonator

XT

to XT­FMH,FMLmode,

FM

V

IN

FMLmode, VIN=0.3Vp-p 30 ~ 150 MHz

FML

HF mode, VIN=0.2Vp-p 1 ~ 40 MHz

HF

LF mode, VIN=0.2Vp-p 0.5 ~ 20 MHz

LF

f

VIN=0.2Vp-p 0.1 ~ 15 MHz

IF

VIH=0.7VDD,VIL=0.3VDD,

f

SC

square wave input.

FMH,FMLmode,

FM

f

IN

FMLmode, fIN=30~150MHz 0.3 ~ VDD-0.5 Vp-p

FML

HF mode, fIN=1~40MHz 0.2 ~ VDD-0.5 Vp-p

HF

LF mode, fIN=0.5~20MHz 0.2 ~ VDD-0.5 Vp-p

LF

V

FIN=0.1~15MHz 0.2 ~ VDD-0.5 Vp-p

IF

VOL=1.0V 5.0 10.0 -- mA

OL1

V

OEF

OFF

terminal

XT

=0.2Vp-p

=30~130MHz

=12V -- --- 2.0

-- 7 15 mA

4.0 5.0 5.5 V

-- 0.8 1.5 mA

-- 120 240

3.6 ~ 10.8 MHz

30 ~ 130 MHz

-- ~ 100 kHz

0.2 ~ V

DD

(To be continued)

µA

-0.5 Vp-p

µA

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(Continued)

Characteristic Symbol Test Condition/Pin Min Typ. Max Unit

I/O-5~I/O-9, SC
Input Voltage

PERIOD, CLOCK, DATA
Input Voltage

DO1, DO2

Tri-State Lead Current I

XT

Input feedback resistance
Input Feedback
Resistance

IN

“H” level V
“L” level V
“H” level I
“L” level I
“H” level I
“L” level I

“H” level V
“L” level V
“H” level I
“L” level I
“H” level I
“L” level I

“H” level I
“L” level I

“H” level I
“L” level I

“H” level

“L” level Rf2

IH1

IL1

VIH=5V -- -- 2.0Input Current

IH

VIL=0V -- -- -2.0

IL

VOH=4.0V (expect SCIN) -2.0 -4.0 --Output Current

OH4

VOL=1.0V (expect SCIN)2.04.0--

OL4

IH2

IL2

VIH=5V -- -- 2.0Input Current

IH

VIL=0V -- -- -2.0

IL

VOH=4.0V (DATA) -1.0 -3.0 --Output Current

OH5

VOL=1.0V (DATA) 1.0 3.0 --

OL5

VOH=4.0V -2.0 -4.0 --Input Current

OH3

VOL=1.0V 2.0 4.0 --

OL3

V

TL

OH2
OL2

Rf1

=5V, V

TLH

VOH=4.0V -0.1 -0.3 --Output Current
VOL=1.0V 0.1 0.3 --

FMIN, AMIN, IFIN
(Ta=25°C)
XT-

XT

=0V -- --

TLL

(Ta=25°C)

0.7V

DD

0 ~ 0.3V

0.8V

DD

0 ~ 0.2V

350 700 1400

500 1000 4000

PIN DESCRIPTION

Pin No. Symbol Pin name Description Circuit diagram

1XT

Crystal oscillator
pins

2

XT

Connects 3.6MHz, 4.5MHz, 7.2MHz
or 10.8MHz crystal oscillator to
supply reference frequency and
internal clock

SC9256

~V

~V

XT XT

DD

DD

DD

DD

±1.0 µA

V

DD

V

µA

mA

V

µA

mA

mA

mA

kΩ

(To be continued)

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(Continued)

Pin No. Symbol Pin name Description Circuit diagram

3 PERIOD Period signal input
4 CLOCK Clock signal input

5DATA

6OT-1
7OT-2

8OT-3

10 AMIN

11 FMIN

13

14

15 DO1

16 DO2/OT-4

12 GND

9V

I/O-

6/IFIN2

I/O-5

/IFIN1

Serial data
input/output

General-purpose
output ports

Programmable
counter input

General-purpose
I/O ports/General­purpose counter
frequency
measurement
input

Phase comparator
output (General­purpose output
ports)

Power supply pins

DD

Serial I/O ports. These pins transfer
data to and from the controller to set
divisions and dividing modes, and to
control the general-purpose counter
and general-purpose I/O ports.
N channel open drain port pins, for
such uses as control signal output.
These pins are set to the OFF state
when power is turned on.

These pins input FM and AM band
local oscillator signals by capacitor
coupling. FM
low amplitude.

General-purpose I/O port input
/output pins. Can be switched for use
as input pins to measure general
purpose counter frequencies. The
frequency measurement function has
such uses as measuring inter­mediate frequencies (IF).
These pins feature built-in amps.
Data are input by capacitor coupling.
FM

IN

amplitude.

(note) Pins are set for input when

power is turned on.

These pins are for phase comparator
tri-state output. DO1 and DO2 are
output in parallel.

Applies 5.0V±10%

and AMINoperate at

IN

and AMINoperate at low

SC9256

V

DD

Schmitt
input

DATA

N-channel open drain

V

DD

V

DD

Schmitt input
CLOCK,PERIOD

VDD

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FUNCTION DESCRIPTION

Serial I/O ports

As the block diagram shows, the functions are controlled by setting data in the 48 bits contained in each of the 2
sets of 24 bit registers. Each bit of data in these register is transferred through the serial ports between the
controller and the DATA, CLOCK and PERIOD pins. Each serial transfer consists of a total of 32 bits, with 8
address bits and 24 data bits.

Since all functions are controlled in units of registers, the explanation in this manual focuses on the 8 bit address
and functions of each register.

These registers consist of 24 bits and are selected by an 8 bit address.

A list of the address assignment for each register is given below under register assignments.

Register Address Contents of 24 bits No. of bit

PLL divisor setting

Input
register 1

Input
register 2

Output
register 1

Output
register 2

D0H

D2H

D1H

D3H

Reference frequency setting
PLL input and mode setting
Crystal oscillator selection

General=purpose counter control (including lock detection bit
control)
I/O port and general-purpose counter switching bits
I/O-5/CLK pin switching bit
DO pin control
Test bit
I/O port control (also used as general-purpose counter input
selection bits)
Output data

General-purpose counter numeric data
Not used

Lock detection data
I/O port control data
Output data
Input data (undefined during output port selection)
Not used

SC9256

16

4
2
2

total 24

4

3
1
1
1
5

9

total 24

22

2

total 24

5
5
4
5
5

total 24

When the PERIOD signal falls, the input data are latched in register 1 or register 2 and the function is performed.

When the CLOCK signal falls for 9 time, the output data are latched in parallel in the output registers. The data
are subsequently output serially from the data pin.

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REGISTER ASSIGMENTS

Address=D0H

LSB

P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 R0 R1 R2 R3 MODEFM OSC1 OSC2

Programmable counterdata

Inputregisters

Address=D2H

G0 G1 -- IF1 IF2 O4C DOHZ

Gate

time

select

Address=D1H

LSB

f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 f16 f17 f18 f19 BUSYOVER "0" "0"

Address=D3H

Inputregisters

ENA­BLE

I/O port

and general-purpose

counter switching bits

UN

PE1 PE2 PE3 "0" "0" "0" "0" 0 0 0 M5 M6 O1 O2 O3 O4 0 0 I50I6"0"

LOCK

Lockdetection data Notused I/O portcontrol data Output data Input data

CLK

bit

DOHZ

bit



RESET START

RESET

bit

(*2)

XT -- -- M5 M6 O1 O2 O3 O4 -- -- O5-- O6TEST

TEST

bit

START

bit

General-purpose counterdata

Alsous ed as

general-purpose

counter input

selection bits

I/O portcontrol

SC9256

Reference

frequency

code data

Programmable

Output portoutput data

counter

mode

LSB

Crystal
oscillator
selection bits

Not

used

When power is turned on, the input registers are set as shown below.

Address=D0H

LSB

(*1) (*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)(*1)1111 1100

(*1)

Address=D2H

Input registers

000000000 00000000000 0000

Note: 1. Data are undefined.

2. Set data to “0” for test bit.

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Serial transfer format

The serial transfer format consists of 8 address bits and 24 data bits (Fig. 1). Addresses D0H~D3H are used.

Start

PERIOD

CLOCK

DATA

•

Serial data transfer

serial data are transferred in sync with the clock signal. In the idle state, the PERIOD, CLOCK and DATA pin
lines are all set to “H” level. When the period signal is at “L” level, the falling of the clock signal initiates serial
data transfer. Data transfer ceases when the period signal is set to “L” level when the clock signal is at “H” level.
Once serial data transfer has begun, however, no more than 8 falls of the clock signal can occur during the time
the period signal is at “L” level.

Since the receiving side receives the serial data as valid data when the clock signal rises, it is effective for the
sending side to produce output in sync with the clock signal fall.

To receive serial data from the output registers (D1H, D3H), set the serial data output to high impedance after
the 8 bit address is output but before the next clock signal falls.

Data reception subsequently continues until the period signal becomes “L” level; data transfer ends just before
the period signal rises. Therefore, the data pin must have an open-drain or tristate interface.
Note: 1. when power is turned on, some internal circuit have undefined states. To set internal circuit states,

execute a dummy data transfer before performing regular data transfer.

2. times t1~t8 have the following value:
t1≥1.0µs
t2≥1.0µs
t3≥0.3µs
t4≥0.3µs
t5≥0.3µs
t6≥1.0µs
t7≥1.0µs

t8≥0.3µs

3. Asterisks represent numbers taken from addresses, as in D*H.

t3

t4

t1 t2

t8

(*)(*)0010 11

LSB

8addressbits

Fig.1

t5

9 clock signal fall

MSB LSB

24 data bits
(24bit register)

SC9256

End

t6

t7

MSB

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Crystal oscillator pins (XT, XT)

As fig.2 shows, the clock necessary for internal operation is produced by connecting a crystal oscillator between

capacitors. Use the crystal oscillator selection bit to select an oscillating frequency of 3.6MHz, 4.5MHz, 7.2MHz or

10.8MHz which matches that of the crystal oscillator used.

LSB MSB

Address D0H

SC9256

OSC1 OSC2

01

OSCILLATOR
FREQUENCY

3.6MHz

4.5MHz

7.2MHz

10.8MHz

OSC1 OSC2

00

01
11

Divider

XT XT

CCX'tal

C=30pF Typ.

Fig.2

Note: set to 3.6MHz (OSC1=”0” and OSC2=”0”) when power is turned on. The crystal is not oscillating at this time

because the system is in standby mode.

Reference counter (Reference frequency divider)

The reference counter section consists of a crystal oscillator and a counter.
A crystal oscillator frequency of 3.6MHZ, 7.2MHZ or 10.8MHZ can be selected .A maximum of 15 reference

frequencies can be generated.

1. Setting reference frequency

The reference frequency is set using bits R0~R3.

Address D0H

LSB MSB

R3R2

R1R0

R0 R1 R2 R3

0000

0001
0100
1100
0010
1010
0110
1110

REFERENCE
FREQUENCY

0.5 KHz
1KHz

2.5 KHz
3KHz

3.125 KHz

*3.90654 KHz

5KHz

6.25 KHz

R0 R1 R2 R3

0001
1001
0101
1101
0011
1011
0111
1111

REFERENCE
FREQUENCY

*7.8125 KHz

9KHz

10 KHz

12.5 KHz
25 KHz
50 KHz

100 KHz

Standby mode (*1)

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Note: 1. Reference frequencies marked with an asterisk “*”can only be generated with a 4.5MHZ crystal oscillator.

2. (*1)Standby mode
Standby mode occurs when bits R0,R1,R2,and R3 are all set to “1”.In standby mode, the programmable
counter stops, and FM, AM and IF

IN(when selected IFIN) are set to “amp off” state (pins at “L” level). This

saves current consumption when the radio is turned off. The DO pins become high impedance during
standby mode.
During standby mode, the I/O ports (I/O-5~I/O-6) and output ports (OT1~OT4) can be controlled and the
crystal oscillator can be turned on and off.

3.The system is set to standby mode when power is turned on. At this time, the crystal oscillator is not

oscillating and the I/O ports are set to input mode.



Programmable counte r

The programmable counter section consists of a 1/2 prescaler, a 2 modulus prescaler and a 4bit +12bit

programmable binary counter.

1. Setting programmable counter

16 bits of divisor data and 2 bits, which indicate the dividing mode, are set in the programmable counter.

(1) Setting dividing mode

The FM and MODE bits are used to select the input pin and the dividing mode (pulses wallow mode or
direct dividing mode). There are 4 possible choices, shown in the table below .Select one based on the
frequency band used.

Address D0H

LSB MSB

FM MODE

SC9256

MODE FM

LF
HF

FM

L

FM

H

0
0

1

1

MODE

DIVIDING MODE
Directdividing mode

0
1

Pulse swallow mode

0

1/2 + pulse swallow

1

mode

TYPICAL

RECEIVING BAND

LW,MW,SWL

SWH

FM

FM

INPUT FREQUENCY

RANGE

0.5 ~ 20MHz
1~40MHz

30 ~ 130MHz
30 ~ 150MHz

30 ~ 130MHz

(2) Setting divisor

The divisor for the programmable counter is set as binary data in bits P0~P15.

• Pulse swallow mode (16 bits)

LSB MSB

Address D0H

P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15

0

2

15

2

Divisor setting range (pulse swallow mode):n=210H~FFFH (528~65535)
(Note) With the 1/2+pulse swallowmode, the actual divisor is twice the programmed value.

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INPUT

FREQUENCY

PIN

AM

IN

n

FM

IN

2n

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• Direct dividing mode (12 bits)

LSB MSB

Address D0H

Divisor setting range (direct dividing mode):n=10H~FFFH(16~4095)
With the direct dividing mode, data p0~p3 are don’t-care and bit p4 is the LSB.

2. Prescaler and programmable counter circuit configuration

(1) Pulse swallow mode circuit configuration

P0 P1 P2 P3

Don't care



P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15

0

2

PSC

11

2

P0-P3

SC9256

4bit swallow counter

Preset

12bit programmable counter

P4-P15

To phase
comparator

FM

AM

FM

H

IN

IN

1/2

FM

HF

L

FM,MODE

Prescaler section

2 modulus

prescaler

Fig.3
This circuit consists of a 2 modulus prescaler, a 4 bit swallow counter and a 12bit programmable counter.
During FM

IN(FMIN mode),a 1/2 prescaler is added to the preceding step.

(2) Direct dividing method circuit configuration

Preset

To phase comparator

AM

Amp

IN

12bit program counter

P4-P15

Fig.4

With the direct dividing mode, the prescaler section is bypassed and the 12bit programmable counter is used.

(3) Both FM

IN and AMIN have built-in amps. Data are input by capacitor coupling. FMIN and AMIN operate at

low amplitude.

General-purpose counter

The general-purpose counter is a 20bit counter. It has such uses as counting AM/FM band intermediate
frequencies (IF) and detecting auto-stop signals during auto-search tuning. General-purpose counter pins can also
be used as I/O ports.

1. General-purpose counter control bits

(1) Bits G0 and G1 … Used for selecting the general-purpose counter gate time.

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LSB MSB

Address D2H

G0G1



SC9256

G0 G1 GATE TIME

00

01

1ms

01

4ms

16ms

11

64ms

CYCLE MEASUREMENT

PULSE

50 KHz
150 KHz
900 KHz

Crystal oscillator frequency

(2) Bits SC,IF1 and IF2 …I/O port and general-purpose counter switching bits.

(*) The functions of the following pins are switched by data.

LSB MSB

Address D2H

(3) Bits M5 sets the state for pin I/O-5/IF
These operations are valid when bits SC, IF1 and IF2 are all set to 1.

Address D2H

LSB MSB

IF1 IF2

M5

0

(*) 1

1
00

IF1

1
0

; M6, for pin I/O-6/IF

IN1

M6

PIN STATES (When bits sc, IF1 and IF2 are all set to "1")

0

0

INPUT pulled down

INPUT enabled

INPUT pulled down

IF

IN1

I/O-5/IF

IF

IN1

I/O-5

IN2.

IN1

M6M5

I/O-6/IF

IF2

1
0

INPUT pulled down
INPUT enabled

INPUT pulled down

IF

IN2

I/O-6

IN2

IF

IN2

Note: Bits marked with an asterisk “(*)” are don’t care
(4) Bits f0~f9…The general-purpose counter results can be read in binary from bits f0~f9 of the output register

(D1H).

LSB MSB

OVERBUSY

Address D1H

f12 f14f13f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f15 f16 f17 f18 f19

0

2

General-purpose counter data

19

2

"0" "0"

(5) OVER and BUSY bits…Detect the operating state of the general-purpose counter.

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AddressD1H MSB

BUSYOVER

"0" "0"

BIT DATA = "1" BIT DATA = "0"

SC9256

General-purpose counter
option monitor bit

General-purpose counter
overflow detection bit

General-purposecounter
busy

Counted value in general­purpose counter
(Overflow state)

20



2

General-purpose counter
ended counting

Counted value in general­purpose counter



220-1

Note: When using the general-purpose counter, before referring to the contents of the general-purpose counter

result bit (f0~f9), confirm that the busy bit is “0” (counting is ended) and the OVER bit is “0” (general-purpose
counter data are normal).

(6) START bit…When the data are set to “1”, the general-purpose counter is reset then counting begins.

LSB MSB

Address D2H

start

01Counting continues uninterrupted.

Counting begins after general - purpose counter is reset.

2. General-purpose counter circuit configuration

The general-purpose counter section consists of input amps, a gate time control circuit and a 20 bit binary

counter.

IF

IN1

Amp

f0-f19

20bit binary counter Overflow detection

OVER

IF

IN2

Cycle measurement

SC

IN

(CMOS input)

pulse

SC IF1

IF2

START G0 G1

3. General-purpose counter measurement timing

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Gate

Gate time control circuit

Fig.5

13

BUSY

f

XT

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

PERIOD

End

SC9256

Note: 1. IF

and IF

IN1

low amplitude.

IN2

T1

IF

IN1

OR

IN2

IF

BUSY bit

Gate

Binary
counter
input

Frequency measurement timing chart

0<T1≤0.25(µs), 0<T2 ≤1(ms)

input have built-in amps. Data are input by capacitor coupling. FMINand AMINoperate at

START bit set to "1"

T2

Clock pulse to be measured

General-purpose I/O ports

These LSIs feature general-purpose output and I/O ports which are controlled through the serial ports.

Input/output form port Input/output configuration
Output port Dedicated: 4 ports N channel open-drain output
I/O ports Dedicated: 1 port,

Maximum: 5 ports

CMOS input/output

1. General-purpose output ports (OT-1~OT-4)

Pins OT-1~OT-4 are general-purpose dedicated output ports. They have such uses as control signal output.

They are configured for N channel open-drain output and have an off withstanding voltage of 12V.

The data set in bits O1~O4 of the input register (D2H) are output in parallel from their correspond dedicated
output port pins OT-1~OT-4. SC9256 do not have dedicated output port OT-4, but setting the input register
(D2H) CLK (O4C) bit to “1” converts pin DO2 into output port OT-4 (configured for CMOS output).

The data set in bits O1~O4 of the input register (D2H) can also be read from the DATA pins as output register
(D3H) serial data O1~O4.

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(1) SC9256

Address D2H

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LSB MSB



O4C

SC9256

O3

O4O2O1

O4C

0

1

(2)output register…The data set in bits O1~O4 of the input register can read as serial data O1~O4 from the

output register (D3H).

Address D2H

Address D3H

2. General-purpose I/O ports (I/O-5~I/O-6)

Pins I/O-5~ I/O-6 are general-purpose I/O ports used for control signal input and output. They are configured
for CMOS input and output.

These I/O ports are set for input or output using bits M5~M6 of the input register (D2H).

Setting M5~M6 to “0” sets these ports for input. Data which are input in parallel from I/O-5~I/O-6 are latched
in the internal register on the ninth fall of the serial clock signal. These data can then be read as serial data
I5~I6 from the DATA pins.

Data which are set in bits O5~O6 of the input register (D2H) are output in parallel from their corresponding
general-purpose I/O port pin I/O-5~I/O6.

These operations are valid when bits SC, IF1, IF2 and CLK are all set to “0”.

DO2/OT-4PIN

DO2

(Phase comparatoroutput)

OT-4

(General-purpose output port)

LSB MSB

LSB MSB

O1~O4

0

1

(N channel opendrain output =off)

(N channel open drain output =on)

PIN OUTPUT STATE

OT-1~OT-3

High impedance

"L" level

OT-4 (*1)

"L" Level (*1)

"H" Level (*1)

O3 O4O2O1

Input
register

O3 O4O2O1

Output
register

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(1) SC9256

Address D2H

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Semiconductors

LSB MSB



IF1

IF2

"0"

"0"

M5 M6

SC9256

M5, M6

0
1

PIN INPUT /OUTPUT STATE (When IF1 and IF2 are "0")

I/O -5, I/O -6

"L" Level

"H" Level

• Setting data for output ports

LSB MSB

Address D2H

IF1
"0"

O5, O6

0
1

IF2

CLK

"0"

"0"

M5

M6

"1"

"1"

O6O5

PIN OUTPUT STATE (When IF1 and IF2 are "0")

I/O -5, I/O -6

"L"level
"H"level

(2)OUTPUT register…data which are set in bits M5~M6 of the input register (D2H) can be read as serial data
M5~M6 from the output register (D3H).

Address D2H

Address D3H

LSB MSB

XT -- -- M5 M6

LSB MSB

000M5M6

Input register

Outputregister

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SC9256

LSB MSB

Address D3H

I/O-5 I/O-6
Input data

INPUT PORTS
(I/O-5 ~ I/O-6)

"L" level
"H" level

Note:

1. When pins I/O-5~I/O-6 are used for output, the data in I5~I6 of the output register(D3H) are undefined..

2. When power is turned on, input register (D2H) I/O port control bits M5~M6 and output data bits O5~O6 are
set to “0”. General-purpose I/O ports are set as input ports. Pins which are used both as general-purpose I/O
ports and for general-purpose counter input are set for I/O port input. The output state of general-purpose
output ports is set to high impedance (N channel open drain output =off).

3. Pin I/O-5 and I/O-6 also serve as general-purpose counter input pins. Therefore, bits IF1 and IF2 of input
register 2 must be set to “0” when these pins are used as I/O ports.

I6I5000

BIT DATA
(I5-I6)

0
1

Input register

Phase comparator

The phase comparator outputs the phase error after comparing the phase difference of the reference frequency
signal supplied by the reference counter and the divided output from the programmable counter. The frequencies
and phase differences of these two signals are then equalized by passing them through low-pass filters. These
signals then control the VCO.

The filter constants can be customized for FM and AM bands since the signals are output in parallel from the
phase comparator then pass through the two tristate buffer pins, DO1 and DO2.

Reference frequency signal

Programmable
counteroutput

R
S

phase

comparator

DD

V

DO1

FM

VCO

L.P.F

V

DD

DO2

AM

VCO

L.P.F

Fig.7

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R

S

DO

floating

Low level



V

CC

R

L

C

R2

High level

R1

DO

Standard
Tr1:2SC1815
Tr2:2SK246

Tr1

Tr2

R3

DO Output Timing Chart

Typical Active Low-Pass Filter Circuit

Fig.8

The figures above show the DO output timing chart and a typical active low-pass filter circuit featuring a
Darlington connection between the FET and transistor.

The filter circuit shown above is just one example. Actual circuits should be designed based on the band
composition and the properties desired from the system.
Pin DO2 can be switched for use as pin OT-4.

Lock detection bits

The lock detection bits detect locked states in the PLL system. These systems have an unlock detection bit
(unlock bit) which is used to detect, using the reference frequency cycle, the phase difference between the
reference frequency and divided output of programmable counter. These systems also have phase error detection
bits ( bits PE1~PE3), which are capable of more precise detection (±0.55µs~±7.15µs).

SC9256

To VCO varactor diode

Typicallow-pass filter constants
(FM bandreference values)



F

C=0.33
R1=10K

¡

R2=8.2K

¡

R3=330

¡

RL=10K

¡

Fig.9

1. Unlock detection bit (U NLOCK)

This bit detects, using the reference frequency cycle, the phase difference between the reference
frequency and the divided output of the programmable counter. When there is no lock, that is, when the
reference frequency and the divided output of the programmable counter are not the same, unlock F/F is set.

Unlock F/F is reset every time the input register (D2H) unlock reset bit (RESET) is set to “1”. After unlock
F/F has been reset in this way, locked state can detected by checking the unlock detection bit (UNLOCK) of
the output register (D3H). After unlock F/F has been reset, the unlock detection bit must be checked after a
time interval exceeding that of the reference frequency cycle has elapsed. This is because the reference
frequency cycle inputs the lock detection strobe to unlock F/F. If the time interval is short, the correct locked
state cannot be detected. Therefore, the output register (D3H) has a lock enable bit (ENABLE). This bit is
reset every time the input register (D2H) reset bit is set to “1”, and set to “1” through the lock detection timing.
That is, the locked state is correctly detected when the lock enable bit (ENABLE) is “1”.

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Reference frequency

Programmable

counter output

Phase comparator

Lock detection strobe

Unlock is reset (RESET)

Unlock F/F (UNLOCK)

Lock enable (ENABLE)

Phase error detection

DO output



Counts phase difference.

Fig.10

SC9256

"H" level

High impedance

"L" level

LSB MSB

Address D2H

LSB MSB

Address D3H

Note: The asterisk (*) indicates an error state of over 180° phase difference relative to the reference frequency

2. Phase error detection bits (PE 1~PE3)

The unlock bit detects, using the reference frequency cycle, the phase difference between the reference
frequency and the divided output of the programmable counter. The phase error detection bits (bits PE1~PE3)
are capable of precise phase error detection of ±0.55µs~±7.15µs using the reference frequency cycle.( If the
UNLOCK bit is set to “1” and the phase difference relative to the reference frequency is over 180°,bits
PE1~PE3 cannot correctly detect the phase error. Therefore, bits PE1~PE3 are normally used when the
UNLOCK bit is set to “0”.) Bits PE1~PE3 detect phase error normally when the phase difference is -180°~180°
relative to the reference frequency cycle.

ENA-

BLEUNLOCK

10PLL lock detectionenabled

PLL lock detection in waiting
state

RESET

Settingdatato "1" resets unlockdetection bit and lock enablebit.

10PLLinunlockedstate(*)

PLLinlockedstate

Input register

Output register

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Address D3H

LSB MSB

PE1

PE2 PE3

SC9256

PE1 PE2 PE3

000
001
010
011
100
110
110
111

PHASE ERROR (PE)

PE<





0.55sPE<1.65s



1.65sPE<2.75s



2.75sPE<3.85s



3.85sPE<4.95s



4.95sPE<6.05s



6.05sPE<7.15s



7.15sPE

0.55s

The phase error data can be read from the output register (D3H) as serial data PE1~PE3.

Following is a typical lock detection operation. It shows the operation flow from locked state to frequency change

with a phase error greater than ±6.05µs.

Frequency change

WAIT

Phase error detection

start Reset bit 1

Time interval exceeding thatof

WAIT

reference frequcncy cycle

ENABLE=1?

YES

UNLOCK bit =0?

NO

NO (UNLOCK)

YES (Lock)

Check phase error

detection bits

PE1,PE2 and PE3

NO

PE1=1,PE2=0,PE3=1?

YES

Phase error=greater than4.95s

and less than



6.05s

Fig.11

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Other Control Bits

1.

CLK and C5 bits…Control bits which switch the function for the OT-4/DO2 pin.

The O4C bit controls switching of the DO2 pin and OT-4 pin.
When bits R0~R3 of the input register (D0H) are set to “1” (standby mode).

LSB MSB

Address D2H



O4C XT

SC9256

O4C XT

00

10
10
11

DO2/OT-4 PINSTATE

DO2 output

OT-4 output

CRYSTAL OSCILLATOR

CIRCUIT STATE
Oscillator circuit off

Oscillator circuit on
Oscillator circuit off
Oscillator circuit on

When one of bit R0~R3 of the input register (D0H) is set to “0” (not standby mode)

LSB MSB

Address D2H

2.

DOHZ bit…controls the DO2 pin output state.

Address D2H

LSB MSB

O4C XT

O4C XT

00

10
10
11

DO2/OT-4 PINSTATE

DO2 output

OT-4 output

DOHZ

CRYSTAL OSCILLATOR

CIRCUIT STATE

Oscillator circuit on

3.

TEST bit… Data should normally be set to “0”.

LSB MSB

Address D2H

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01phase comparison error output

DO2 output fixed at high impedance

TEST

"0"

21

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ELECTRICAL CHARACTERISTICS CURVE



SC9256

AMIN(LF) Frequency Characteristics

1414
1000

500

200
106

71
50

20
10

5

INPUT LEVEL (mVrms)

2
1

0.1 0.2 0.5 1 2 5 2010 50 100

INPUT FREQUENCY (MHz)

AMIN(HF) Frequency Characteristics

1414
1000

500

200
106

71
50

20
10

5

INPUT LEVEL (mVrms)

2
1

0.1 0.2 0.5 1 2 5 2010 50100

INPUT FREQUENCY (MHz)

(Note)

OperatingGuarantee Range



VDD=4.5~5.5v,Ta = -40 ~ 85)

Standard Characteristics(V

40

DD

=5V,Ta=25)

FMIN(LF) Frequency Characteristics

1414
1000

500

200
106

71
50

20
10

5

INPUT LEVEL (mVrms)

2
1

020

40 60 80 100 120 140 160 180 200

INPUT FREQUENCY (MHz)

IFIN(LF) Frequency Characteristics

1414
1000

500

200
106

71
50

20
10

5

INPUT LEVEL (mVrms)

2
1

0.05 0.1 0.2 0.5 1 2 5 10 501520

INPUT FREQUENCY (MHz)

(Note)

+

FMIN:FM
FMIN:FM

Standard Characteristics(VDD=5V,Ta=25)

H

OperatingGuarantee Range

DD

=4.5~5.5v,Ta = -40 ~ 85)

(V

L

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APPLICATION CIRCUIT

C

Micro­Controller

PERIOD

CLOCK
DATA

CX'tal



V

1
2
3
4
5
6
7
8

SC9256

16
15



F

0.01

14



F

0.01

13
12
11
10

9



F0.1F

4.7

0.001F

0.01F

SC9256

CC

5Vtyp.

Varator Diode

AM
VCO

AM
VCO

AM

IF

signal

FM

IF

signal

3

Output Port

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PACKAGE OUTLINE

DIP-16-300-2.54 UNIT: mm

2.54

0.25

B

6.35

7.62(300)

SC9256

0.05

B

0.25

0.5MIN

19.55B0.3

0.5B0.1

1.52

4.36MAX3.00MIN

1.27MAX

15 degree

SOP-16-300-1.27 UNIT:mm

0.45

B

1.27

0.10

10.15B0.25

0.40

B

7.80

2.25MAX

0.30

B

5.30

0.15

+0.05

-0.02

7.62(300)

8.89




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