Datasheet SC84502AP, SC84502BP Datasheet (SILAN)

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Semiconductors

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PS/2 MOUSE CONTROLLER

DESCRIPTION

The SC84502 Mouse Controller is specially designed to control
PS/2 mouse device. This single chip can interface three key­switches and f our photo-couples direct to 8042. SC84502 can
receive command and echo status or data format which are
compatible with IBM PS/2 mode mouse. Key debouncing circuit is
provided to prevent false entry and improve the accuracy.

In the conventional mouse, a great number of noises are
generated when the grid is partially closed or opened. These noise
are usually mistaken for movement signals by conventional mouse
controller and the cursor of the display screen is thus moved
frequently up and down or back and forth. This will consumes a great
amount of energy. The SC84502 PS/2 mouse controller provides
noise immunity circuits to eliminate these noise In order to reduce
energy consumption.

SC84502

DIP-14

DIP-16

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FEATURES

* Being compatible with PS/2 mouse mode
* Built-in noise immunity circuit
* Low power dissipation
* RC oscillation
* Three key-switches and four photo-couples inputs
* Both key-press and key-release debounce interval 12ms
* Through three key-switches input, SC84502 can exert seven

different output

* The motion detector of the SC84502 could sense 8m/sec

maximum with 200 DPI wheels

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ORDERING INFORMATION

SC84502AP DIP-14 PACKAGE

DIP-16 PACKAGESC84502BP

APPLICATIONS

* Optical mouse or pen-mouse
* Mechanical mouse or pen-mouse
* Optomechanical mouse or pen-mouse
* Mechanical track ball
* Optomechanical track ball

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PIN CONFIGURATIONS

VDD

1

OP

2

OSC OUT

3

CLK

4

DATA

5

VSS

6

R

7

BLOCK DIAGRAM

( Refer to SC84502BP )

OP

2

X1

12

X2

13

Y1

14

Y2

15

SC84502AP

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14
13
12
11
10

MOTION DETECTORDEBOUNCE

9
8

OSCR

Y2

Y1

X2

X1

L

M

NOISE IMMUNTY

COUNTER

VDD

OSC OUT

CLK

DATA

VSS

SC84502

SC84502BP

1
8
3
4

OSCR

16

Y2

15

Y1

14

X2

13

X1

12

L

11

M

10

R

9

V

DD

V

SS

NC

NC

1

OP

2

NC

3

NC

4
5
6
7
8

L

OSCR

OSC OUT

11

M

10

R

9

16

5

TIMING

CONTROLLER

SYSTEM

CLOCK

GENERATOR

DATA CONVERTER

DATA

I/O

COMMAND DECODER

7 6

DC ELECTRICAL CHARACTERISTICS

DATA CLK

(Tamb=25~70°C)

Parameter Symbol Condition Min Typ Max Unit

Operating Voltage V

-- 4.5 5 5.5 V

DD

Operating Current Iop No Load -- -- 1.2 mA
X1,X2,Y1,Y2
Low Input reference current
X1,X2,Y1,Y2
High Input reference current

Ipl

Iph

--

--

70 -- --

-- -- 106

µA

µA

(to be continued)

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(continued)

Parameter Symbol Condition Min Typ Max Unit

Schmitt trigger input, Ipl=76µA

X1,X2,Y1,Y2 input current V

CLK, DATA positive-going
threshold voltage
CLK, DATA negative-going
threshold voltage
Low Input Voltage, Other Pins Vail -- -- -- 1.5 V
High Input Voltage, Other Pins Vaih -- 3.5 -- -- V
L,M,R Input Current Imi Pull Up Resistor, Vin=5V 16.6 -- 50
PS/2 mouse mode
DATA,CLK input Current
PS/2 mouse mode
DATA,CLK low output Voltage
L,M,R,X1,X2,Y1,Y2
Input Leakage Current
Note: All voltages in above table are compared with VSS.

All parameters in above table are tested under VDD=5V.
CLK & DATA output gates are open drains that connect to pull up resistors.

pl

Comparator input, Ipl=80µA
Comparator input, Ipl=500µA

Vt+ -- 3.2 -- 3.8 V

Vt- -- 1.2 -- 1.9 V

Idc Vin = 0V 0.56 -- 1.86 mA

Vprl Iprl = -2 mA -- -- 0.4 V

Iil Vin = 0V 0 -- 1.0

SC84502

0.8 -- 1.2 V

0.8 -- 1.2 V

1.5 -- 2.1 V

µA

µA

AC ELECTRICAL CHARACTERISTICS

(Tamb=0~70°C)

Parameter Symbol Min Typ Max Unit

Oscillating Frequency Fosc 34.3-10% 34.3 34.3+10% kHz
Key Debounce Tkd -- 12 -- ms
Rising Edge Crossed Width Fosc=35 kHz Tr 14.3 -- -­Falling Edge Crossed Width Fosc=35 kHz Tf 14.3 -- -­Mouse CLK Active Time Tmca -- 42.9 -­Mouse CLK Inactive Time Tmci -- 42.9 -­Time that Mouse Sample DATA from CLK rising Edge Tmdc -- 14.3 -­System CLK Active Time Tsca -- 42.9 -­System CLK Inactive Time Tsci -- 42.9 -­Time from DATA Transition to Falling Edge of CLK Tsdc -- 14.3 -­Time from rising Edge of CLK to DATA Transition Tscd -- 28.6 -­Time to mouse Inhibit after the 11th CLK to
ensure mouse does not start another Transmission
Note: The AC timings are measured under using 35kHz system clock signal.

Tpi 0 -- 50

µs
µs
µs
µs
µs
µs
µs
µs
µs

µs

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X1, X2, Y1, Y2 INPUT IMPEDANCE

PIN DESCRIPTION

Pin No. Pin Name I/O Description

1VDD-- Positive Power Supply.

2OPI

3 NC -- No Connection
4 NC -- No Connection
5 OSCOUT O Clock output.
6 CLK I/O 8042 auxiliary port CLK line.
7 DATA I/O 8042auxiliary port DATA line.
8VSS-- Negative Power Supply

9R

10 M

11 L
12 X1

13 X2
14 Y1
15 Y2
16 OSCR I

(refer to SC84502BP)

I

I

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UNIT:KΩ

MAX.

16.0

15.0

14.0
TYP.

13.0

12.0

MIN.

11.0

10.0

9.0

8.0

7.0

6.0

5.0

4.0

3.0

2.0

1.0
0 1.0 2.0 3.0 4.0 5.0

INPUT VOLTAGE

X, Y inputs: Floating: Comparator input.

GND: Schmitt trigger input.
Short to OSC OUT: Testing Mode.

Three key-switches esert seven different combinations totally. Both key-pressed
and key-released signals will be sent accompanied with horizontal and vertical
state. The status of the key-switches will be preserved, whenever the value of
horizontal or vertical counters will present at DATA. And the debounce interval for
both key-press and key release is 12ms.

Four photo-couple signal denote UP, DOWN, LEFT and RIGHT state.
During the scanning period, as long as the photo-couples change their states, the
value of vertical or horizontal, counter will increase or decrease accordingly.

50kΩ±5% pull low for 35kHz oscillation

SC84502

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FUNCTION DESCRIPTIONS

1. OPERATING MODE

There are four operating modes in PS/2 mouse:

i) Reset Mode:

In this mode a self-test is initiated during power-on or by a Reset command. After reset signal, PS/2 mouse
will send:

1) Completion code AA&ID code 00.

2) Set default:
sampling rate: 100 reports/s
non-autospeed
stream mode
2 dot/count
disable

ii) Stream Mode:

The maximum rate of transfer is the programmed sample rate.
Data report is transmitted if

1) switch is pressed

2) movement has been detect

SC84502

iii) Remote Mode:

Data is transmitted only in response to a Read Data command.

iv) Wrap Mode:

Any byte of data sent by the system, except hex EC(Reset wrap mode) or hex FF(Reset), is returned by
SC84502.

2. PS/2 MOUSE DATA REPORT

i) In stream mode: A data report is sent at the end of a sample interval.

ii)In remote mode: A data report is sent in response to Read Data command.

iii) Data report format:

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Byte Bit Description

1 0 Left button status; 1 = pressed

1 Right button status; 1 = pressed
2 Middle button status; 1 = pressed
3 Reserve
4 X data sign; 1 = negative
5 Y data sign; 1 = negative
6 X data overflow; 1 = overflow

7 Y data overflow; 1 = overflow
2 0-7 X data(D0 ~ D7)
3 0-7 Y data(D0 ~ D7)

3.PS/2 MOUSE DATA TRANSMISSION

i) SC84502 generates the clocking signal when sending data to and receiving data from the system.

ii) The system requests SC84502 receive system data output by forcing the DATA line to an inactive level and

allowingCLKlinetogotoanactivelevel.

iii) Data transmission frame:

Bit Function

1 Start bit(always 0)

2~9 Databits(D0~D7)

10 Parity bit(odd parity)
11 Stop bit (always 1)

SC84502

iv) Data Output (data from SC84502 to system)

If CLK is low (inhibit status), data is no transmission.

If CLK is high and DATA is low(request-to-send), data is updated. Data is received from the system and no
transmission are started by SC84502 until CLK and DATA both high. If CLK and DATA are both high, the
transmission is ready. DATA is valid prior to the falling edge of CLK and beyond the rising edge of CLK.
During transmission, SC84502 check for line contention by checking for an inactive level on CLK at
intervals not to exceed 100µ sec. Contention occurs when the system lowers CLK to inhibit SC84502
output after SC84502 has started a transmission. If this occurs before the rising edge of the contention

does not occur by the tenth clock, the transmission is complete.

Following a transmission, the system inhibits SC84502 by holding CLK low until it can service the input or

until the system receives a request to send a response from SC84502.

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v) Data Input (from system to SC84502)

System first check if SC84502 is transmitting data. If SC84502 is transmitting, the system can override the
output forcing CLK to an inactive level prior to the tenth clock. If SC84502 transmission is beyond the tenth
clock, the system receives the data. If SC84502 is not transmitting or if the system choose to override the
output, the system force CLK to an inactive level for a period of not less than 100m sec while preparing for
output. When the system is ready to output start bit (0), it allows CLK go to active level. If request-to-send is
detected, SC84502 clocks 11 bits. Following the tenth clock SC84502 checks for an active level on the
DATA line, and if found, force DATA low , and clock once more. If occurs framing error, SC84502 continue
to clock until DATA is high, then clocks the line control bit and request a Resend. When the system sends
out a command or data transmission that requires a response, the system waits for SC84502 to response

before sending its next output.

4. PS/2 MOUSE ERROR HANDLING

i) A Resend command ( FE ) following receipt of an invalid input or any input with incorrect parity.

ii) If two invalid input are received in succession, an error code of hex FC send to the system.

iii) The counter accumulators are cleared after receiving any command except “Resend”.

SC84502

iv) SC84501 receives a Resend command ( FE ), it transmit its last packet of data.

v

In the stream mode “Resend” is received by SC84502 following a 3-byte data packet transmission to the

system. SC84502 resend the 3-byte data packet prior to clearing the counter.

vi) A response is sent within 25 ms if

a). The system requires a response
b). An error is detected in the transmission

vii). When a command requiring a response is issued by the system ,another command should not be issue until

either the response is received or 25ms has passed.

5. PS/2 MOUSE COMMANDS DESCRIPTION

There are 16 valid commands that transmits between the system and SC84502. The “FA” code is always the
first response to any valid input received from the system other than a Set Wrap Mode or Resend command.
The following table list the commands:

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Hex Code Command SC84502 echo code

FF Reset FA, AA, 00
FE Resend XX, (XX, XX)
F6 Set Default FA
F5 Disable FA
F4 Enable FA
F3, XX Set Sampling Rate FA, FA
F2 Read Device Type FA, 00
F0 Set Remote Mode FA
EE Set Wrap Mode FA
EC Reset Wrap Mode FA
EB Read Data FA, XX, XX, XX
EA Set Stream Mode FA
E9 Status Request FA, XX, XX, XX
E8, XX Set Resolution EA, FA
E7 Set Autospeed FA
E6 Reset Autospeed FA

The following describes valid commands:

a). Reset ( FF )

SC84502 operation:

i). Completion the reset.
ii). Transmitted FA,AA,00 to the system.
iii). Set default:

sampling rate: 100 reports/s
non-autospeed
stream mode
2 dots/count
disable

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SC84502

b). Resend ( FE )

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i). Any time SC84502 receives an invalid command, it returns a Resend command to the system.
ii). When SC84502 receives a Resend command, it retransmits its last packet of data. If the last packet

was a Resend command, it transmits the packet just prior to the Resend command.

iii). In stream mode, if a Resend command is received by SC84502 immediately following a 3-byte data

packet transmission to the system.

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c). Set Default (F6)

The command reinitializes all conditions to the power-on defaults.

d). Disable (F5)

This command is used in the stream mode to stop transmissions from SC84502.

e). Enable (F4)

Begins transmissions, if in stream mode.

f). Set Sampling Rate (F3, XX)

In the stream mode, this command sets the sampling rate to the value indicated by byte hex XX, shown in
following:

Second byte XX Sample Rate

0A 10/sec
14 20/sec

28 40/sec
3C 60/sec
50 80/sec
64 100/sec
C8 200/sec

g). Read Device Type (F2)

SC84502 always echoes “FA, 00 “ following this command.

h). Set Remote Mode (F0)

Data values are reported only in response to a Read Data command.

i). Set Wrap Mode (EE)

Wrap mode remains until Reset (FF) or Reset Wrap Mode (EC) is received.

j). Reset Wrap Mode (EC)

SC84502 returns to the previous mode of operation after receiving this command.

k). Read Data (EB)

This command is executed in either remote or stream mode. The data is transmitted even if there has been
no movement since the last report or the button status is unchanged. Following a Read Data command, the
registers are cleared after a data transmission.

l). Set Stream Mode (EA)

This command sets SC84502 in stream mode.

m). Status Request (E9)

When this command is issued by the system, SC84502 respond with a 3-byte status report as follows:

SC84502

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n). Set Resolution ( E8,XX )

SC84502 provides four resolutions selected by the second byte of this command as follows:

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Byte Bit Description

1 0 1=Right button pressed

1 1=Middle button pressed
2 1= Left button pressed
3 Reserved
4 0=Normal speed, 1=Autospeed
5 0=Disabled, 1=Enabled
6 0=Stream mode, 1=Remote mode

7 Reserved
2 0–7 Current resolution setting (D0-D7)
3 0-7 Current sampling rate (D0-D7)

Second Byte XX Resolution

00 8 dot/count
01 4 dot/count
02 2 dot/count
03 1 dot/count

SC84502

o). Set Autospeed ( E7 )

At the end of a sample interval in the stream mode, the current X and Y data values are converted new
values. The sign bits are not involved in this conversion. The conversion is only in stream mode. The

relationship between the input and output count follows:

Input Output

00
11
21
33
46
59

N(≥6) 2.0*N

p). Reset Autospeed ( E6 )

This command restore normal speed.

6.TESTING MODE

Whenever OPT is connected to OSC OUT, the chip will enter buyer's testing mode. The X direction output signals
of comparators will present to L and M pin. Pressing "R" key can toggle the output from X direction to Y direction.

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TIMING DIAGRAM

(1) Photo-couples pulse width

X1(Y1)



SC84502

(2) PS/2 Mouse

(A) Receiving Data

(B) Sending Data

AC TIMING POINT

Output:

DATA

(PS/2 mouse mode)

CLK PIN

Input:

X1, X2, Y1, Y2 PIN

CLK, DATA PIN

L, M, R PIN

X2(Y2)

CLK

DATA

CLK

DATA

Tr Tf

Inhibit

Tmca

Tmdc

Start

Bit

1st

CLK

Tscl Tsca

Start

Bit

1st

CLK

TscdTsdc

2rd

CLK

Tmci

Bit0-Bit7

2nd

CLK

Bit0-Bit7

9th

CLK

Parity

Bit

10th
CLK

10th
CLK

Parity

Bit

Stop

Bit

11th
CLK

Tpi

11th
CLK

Stop

Bit

Line

Control

Bit

VDD-2.6 VSS+0.4

SS

+1.6

V

V

SS

DD

-0.8

V
VSS+0.8

V

DD

V

SS

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SC84502 I/O PIN EQUIVALENT CIRCUITS

CLK: X1,X2,Y1,Y2:



SC84502

X1,X2,Y1,Y2

V

PS/2 MOUSEENABLE

DATA INPUT SIGNAL

DATA INPUT SIGNAL

CC

CLK

V

CC

V

PP/4

R, M, L: DATA:

(R,M,L)

(R,L,M)

INTERNAL SIGNAL

10kΩ

PS/2 MOUSE ENABLE

DATA INPUT SIGNAL

13.2kΩ

V

CC

13.2kΩ

MOUSE DIGITAL SIGNAL

V

CC

CC

V

V

CC

DATA

DATA INPUT SIGNAL

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APPLICATIONS CIRCUITS



SC84502

V

DD

1

Y2

15

Y1

14

X2

13

X1

12

L

11

M

10

R

98

510¡510

¡

+5V

µ

f

10

CLK

DATA

GROUND

50k

OP

2

OSC DR

16

NC

3

NC

¡

4

OSC OUT

5

CLK

6

DATA

7

Vss

SC84502AP

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PACKAGE OUTLINE

DIP-14-300-2.54 UNIT:mm

2.54

SC84502

0.25

6.40

1.50

19.4

3.51

0.46

7.62

15 degree

5.083.30

DIP-16-300-2.54 UNIT:mm

2.54

0.25

6.40

19.4

1.50

7.62

15 degree

3.51

0.46

5.083.30

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