Datasheet SC480IMLTRT Datasheet (Semtech) [ru]

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

SC480

Complete DDR1/2/3

Memory Power Supply

Description

The SC480 is a combination switching regulator and
linear source/sink regulator intended for DDR1/2/3
memory systems. The purpose of the switching regulator
is to generate the supply voltage, VDDQ, for the memory
system. It is a pseudo-fi xed frequency constant on-
time controller designed for high effi ciency, superior DC
accuracy, and fast transient response. The purpose of the
linear source/sink regulator is to generate the memory
termination voltage, VTT, with the ability to source and
sink a 3A peak current.

For the VDDQ regulator, the switching frequency is constant
until a step in load or line voltage occurs at which time the
pulse density, i.e., frequency, will increase or decrease to
counter the transient change in output or input voltage.
After the transient, the frequency will return to steady-state
operation. At lighter loads, the selectable Power-Save
Mode enables the PWM converter to reduce its switching
frequency and improve effi ciency. The integrated gate
drivers feature adaptive shoot-through protection and
soft-switching. Additional features include cycle-by-cycle
current limiting, digital soft-start, over-voltage and under­voltage protection and a power good fl ag.

For the VTT regulator, the output voltage tracks REF,
which is ½ VDDQ to provide an accurate termination
voltage. The VTT output is generated from a 1.2V to VDDQ
input by a linear source/sink regulator which is designed
for high DC accuracy, fast transient response, and low
external component count. All three outputs (VDDQ, VTT
and REF) are actively discharged when VDDQ is disabled,
reducing external component count and cost. The SC480
is available in a 24-pin MLPQ (4x4 mm) package.

Typical Application Circuit

Features

Constant On-Time Controller for Fast Dynamic



Response on VDDQ

DDR1/DDR2/DDR3 Compatible



VDDQ = Fixed 1.8V or 2.5V, or Adjustable from



1.5V to 3.0V
1% Internal Reference (2% System Accuracy)



Resistor Programmable On-Time for VDDQ



VCCA/VDDP Range = 4.5V to 5.5V



VIN Range = 2.5V to 25V



VDDQ DC Current Sense Using Low-Side R



Sensing or External R

in Series with Low-Side

SENSE

DS(ON)

FET
Cycle-by-Cycle Current Limit for VDDQ



Digital Soft-Start for VDDQ



Analog Soft-Start for VTT/REF



Smart Over-Voltage VDDQ Protection Against Source-



Current Loads
Combined EN and PSAVE Pin for VDDQ



Over-Voltage/Under-Voltage Fault Protection



Power Good Output



Separate VCCA and VDDP Supplies



VTT/REF Range = 0.75V – 1.5V



VTT Source/Sink 3A Peak



Internal Resistor Divider for VTT/REF



VTT is High Impedance in S3



VDDQ, VTT, REF Are Actively Discharged in S4/S5



24 Lead MLPQ (4x4 mm) Lead-Free Package



Fully WEEE and RoHS Compliant



Applications

¡ Notebook Computers
¡ CPU I/O Supplies
¡ Handheld Terminals and PDAs
¡ LCD Monitors
¡ Network Power Supplies

5V

D1

20DL19

22DH21

23

1
2
3
4
5
6

PGND2
VTTS
VSSA
TON
REF
VCCA

0.1uF

24

LX

BST

VTT

VTTIN

U1

SC480

FB

EN/PSV

VDDQS

VTTEN

NC

7

9

8

10

11

C8

C1
1uF

VBAT

VTT

R1
1Meg

REF

VDDQ

VDDQVDDQ

C5

C4

10uF

10uF

VTTSNS

C7
1nF

R6
10R

C10
1uF

C9

1uF

November 3, 2006

PGND1
PGND1

ILIM
VDDP
VDDP

PGD

PAD

NC

12

R7 10R

VTT_EN

EN/PSV

C2

0.1uF

18
17
16
15
14
13

PAD

VBAT

C3
2x10uF

Q1

VDDQ

+

C6

PGOOD

5V

RILIM

L1

R4

C11
1uF

Q2

www.semtech.com1

SC480

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

POWER MANAGEMENT

POWER MANAGEMENT

Absolute Maximum Ratings

Exceeding the specifi cations below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specifi ed in the
Electrical Characteristics section is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability.

Parameter Symbol Maximum Units

TON to VSSA -0.3 to +25.0 V

DH, BST to PGND1 -0.3 to +31.0 V

BST, DH to LX -0.3 to +6.0 V

LX to PGND1 -2.0 to +25.0 V

DL, ILIM, VDDP to PGND1 -0.3 to +6.0 V

VDDP to DL -0.3 to +6.0 V

VTTIN to PGND2; VTT to PGND2; VTTIN to VTT -0.3 to +6.0 V

EN/PSV, FB, PGD, REF, VCCA, VDDQS, VTTEN, VTTS to VSSA -0.3 to +6.0 V

VCCA to EN/PSV, FB, REF, VDDQS, VTT, VTTEN, VTTIN, VTTS -0.3 to +6.0 V

PGND1 to PGND2; PGND1 to VSSA; PGND2 to VSSA -0.3 to +0.3 V

Thermal Resistance Junction to Ambient

Operating Junction Temperature Range T

Storage Temperature Range T

Peak IR Refl ow Temperature, 10s - 40s T

ESD Protection Level

Notes:

1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.

2) Tested according to JEDEC standard JESD22-A114-B.

(2)

(1)

θ

JA

J

STG

PKG

V

ESD

29 °C/W

-40 to +150 °C

-65 to +150 °C

260 °C

2kV

Electrical Characteristics

TEST CONDITIONS: VIN = 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, R

Parameter Conditions

Input Supplies

S0 State (VTT on);

VCCA Operating Current

FB > Regulation Point, IVDDQ = 0A

VCCA Operating Current

FB > Regulation Point, IVDDQ = 0A

VCCA Operating Voltage 5 4.5 5.5 V

VDDP Operating Current FB > Regulation Point, IVDDQ = 0A 70 150 μA

TON Operating Current RTON = 1MΩ 15 μA

VTTIN Operating Current IVTT = 0A 1 5 μA

VCCA + VDDP + TON
Shutdown Current

VTTIN Shutdown Current EN/PSV = VTTEN = 0V 1 μA

EN/PSV = VCCA;

S3 State (VTT off);

EN/PSV = VCCA;

EN/PSV = VTTEN = 0V 5 11 μA

= 1MΩ. T

TON

Min Typ Max Min Max

= -40 TO +85C.

AMB

25°C -40°C to 85°C

1500 2500 μA

800 1400 μA

2© 2006 Semtech Corp. www.semtech.com

Units

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Electrical Characteristics (Cont.)

TEST CONDITIONS: VIN = 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, R

Parameter Conditions

VDDQ Controller

FB Error Comparator Threshold

(1)

With Adjustable Resistor Divider 1.500 1.485 1.515 V

= 1MΩ. T

TON

Min Typ Max Min Max

= -40 TO +85C.

AMB

25°C -40°C to 85°C

SC480

Units

VDDQS Regulation Threshold

RTON = 1MΩ, VDDQ = 1.8V 460 368 552

On-Time

RTON = 500kΩ, VDDQ = 1.8V 265 212 318

Minimum Off-Time 425 550 ns

VDDQS Input Resistance

VDDQS Shutdown
Discharge Resistance

FB Leakage Current -1.0 1.0 μA

VDDQ Smart Psave Threshold 8 %

VTT Controller

REF Source Current 10 mA

REF Sink Resistance 50 kΩ

REF Output Accuracy IREF = 0 to 10mA 900 882 918 mV

Shutdown Discharge Resistance
(EN/PSV = GND)

VTT Output Accuracy
(with respect to REF)

VTTS Leakage Current -1.0 1.0 μA

FB = AGND 2.5 2.475 2.525 V

FB = VCCA 1.8 1.782 1.818 V

ns

FB < 0.3V 80 kΩ

FB > 0.3V 91 kΩ

EN/PSV = GND 16 Ω

VTT 0.25 Ω

REF 8 Ω

VTT

< 2A

(9)

0 -40 +40 mV

-2A < I

Current Sensing

ILIM Current DL High 10 9 11 μA

Current Comparator Offset PGND1 - ILIM -10 10 mV

Zero-Crossing Threshold PGND1 - LX, EN/PSV = 5V 5 mV

VDDQ Fault Protection

PGND1 - LX, RLIM = 5kΩ 50 35 65

Current Limit (Positive)

Current Limit (Negative) PGND1 - LX -125 -160 -90 mV

Output Under-Voltage Fault With Respect to FB Regulation Point -30 -35 -25 %

(2)

PGND1 - LX, RLIM = 20kΩ 200 170 230

3© 2006 Semtech Corp. www.semtech.com

mVPGND1 - LX, RLIM = 10kΩ 100 80 120

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

POWER MANAGEMENT

Electrical Characteristics (Cont.)

TEST CONDITIONS: VIN = 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, R

Parameter Conditions

= 1MΩ. T

TON

Min Typ Max Min Max

= -40 TO +85C.

AMB

25°C -40°C to 85°C

SC480

Units

Under-Voltage Fault Delay FB Forced Below UV V

Under-Voltage Blank Time From EN High 440 clks

Output Over-Voltage Fault With Respect to FB Regulation Point +16 +12 +20 %

Over-Voltage Fault Delay FB Above Over-Voltage Threshold 5 μs

PGD Low Output Voltage Sink 1mA 0.1 V

PGD Leakage Current FB in Regulation, PGD = 5V 1 μA

PGD UV Threshold With Respect to FB Regulation Point -10 -12 -8 %

PGD Fault Delay FB Forced Outside PGD Window 5 μs

VCCA Under-Voltage (UVLO) Falling Edge (Hysteresis 100 mV) 4 3.70 4.35 V

VTT Fault Protection

UV Lower Threshold VTT w/rt REF -12 -16 -8 %

OV Upper Threshold VTT w/rt REF +12 +8 +16 %

Fault Shutdown Delay VTT Outside OV/UV Window 50 μs

Thermal Shutdown

(4)(5)

TH

8 clks

160 150 170 °C

(3)

(3)

Inputs/Outputs

EN/PSV Low/Low (Disabled) 1.2

Logic Input Low Voltage

VTTEN Low (VTT Disabled) 0.6

EN/PSV Low/High

Logic Input High Voltage

Logic Input High Voltage

EN/PSV Input Resistance

VTTEN Leakage Current -1 +1 μA

Soft-Start

VDDQ Soft-Start Ramp Time EN/PSV High to PGD High 440 clks

VTT Soft-Start Ramp Rate

(6)

(Enabled, Psave Disabled)

VTTEN High (VTT Enabled) 2.4

EN/PSV High/High

(Enabled, Psave Enabled)

Sourcing 1.5 MΩ

Sinking 1.0 MΩ

5.5 mV/μs

1.2 2.4

3.1 V

4© 2006 Semtech Corp. www.semtech.com

V

V

(3)

SC480

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

POWER MANAGEMENT

Electrical Characteristics (Cont.)

TEST CONDITIONS: VIN = 15V, VCCA = VDDP = VTTEN = EN/PSV = 5V, VDDQ = VTTIN = 1.8V, R

Parameter Conditions

FB Input Thresholds

FB Logic Input Low VDDQ Set for 2.5V (DDR1) 0.3 V

FB Logic Input High VDDQ Set for 1.8V (DDR2)

Gate Drives

Shoot-Thru Protection Delay

DL Pull-Down Resistance DL Low 0.8 Ω

DL Sink Current VDL = 2.5V 3.1 A

DL Pull-Up Resistance DL High 2 Ω

(4)(7)

DH or DL Rising 30 ns

= 1MΩ. T

TON

Min Typ Max Min Max

= -40 TO +85C.

AMB

25°C -40°C to 85°C

VCCA

- 0.7

Units

V

DL Source Current VDL = 2.5V 1.3 A

DH Pull-Down Resistance DH Low, BST - LX = 5V 2 Ω

DH Pull-Up Resistance

DH Sink/Source Current VDH = 2.5V 1.3 A

VTT Pull-Up Resistance VTTS < REF 0.25 Ω

VTT Pull-Down Resistance VTTS > REF 0.25 Ω

VTT Peak Sink/Source Current

Notes:

1) The VDDQ DC regulation level is higher than the FB error comparator threshold by 50% of the ripple voltage.

2) Using a current sense resistor, this measurement relates to PGND1 minus the source of the low-side MOSFET.

3) clks = switching cycles, consisting of one high side and one low side gate pulse.

4) Guaranteed by design.

5) Thermal shutdown latches both outputs (VTT and VDDQ) off, requiring VCCA or EN/PSV cycling to reset.

6) VTT soft-start ramp rate is limited to 5.5mV/μs typical. If the VDDQ/2 ramp rate is slower than 5.5mV/μsec, the VTT soft-start ramp will follow the VDDQ/2
ramp.

7) See Shoot-Through Delay Timing Diagram on Page 6.

8) Semtech’s SmartDriver™ FET drive fi rst pulls DH high with a pull-up resistance of 10Ω (typ.) until LX = 1.5V (typ.). At this point, an additional pull-up device is
activated, reducing the resistance to 2Ω (typical). This creates a softer turn-on with minimal power loss, eliminating the need for an external gate or boost
resistor.

9) Provided operation below T
increases with temperature, and by available source voltage (typically VDDQ/2).

(8)

(9)

is maintained. VTT output current is also limited by internal MOSFET resistance which is typically 0.25Ω at 25°C and which

J(MAX)

DH High, BST - LX = 5V 2 Ω

3.6 2.0 A

5© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

POWER MANAGEMENT

Shoot-Through Delay Timing Diagram

LX

DL

tplhDL tplhDH

SC480

DH

DL

6© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Pin Confi guration Ordering Information

SC480

SC480 MLP24 Pin Out

VTT

VTTIN

BST

DH

PGND2

VTTS

VSSA

TON

REF

VCCA

23

24

1

2

3

4

5

6

7

8

NC

VDDQS

21

22

T

9

10

FB

VTTEN

Pin Description

Pin # Pin Name Pin Function

LX

20

11

EN/PSV

DL

12

19

NC

18

17

16

15

14

13

PGND1

PGND1

ILIM

VDDP

VDDP

PGD

Device

(2)

Package

(1)

SC480IMLTRT MLPQ-24

SC480EVB Evaluation Board

Notes:

1) Only available in tape and reel packaging. A reel contains 3000 devices.

2) This product is fully WEEE and RoHS compliant.

1 PGND2 Power ground for VTT output. Connect to thermal pad and ground plane.

2 VTTS Sense pin for VTT. Connect to VTT at the load.

3 VSSA Ground reference for analog circuitry. Connect to thermal pad.

4TON

5 REF

This pin is used to sense VBAT through a pull-up resistor, RTON, which sets the top MOSFET
on-time. Bypass this pin with a 1nF capacitor to VSSA.

Reference output. An internal resistor divider from VDDQS sets this voltage to 50% VDDQ (nomi­nal). Bypass this pin with a series 10Ω/1μF to VSSA.

6 VCCA Analog supply voltage input. Use a 10Ω/1μF RC fi lter from +5V to VSSA.

7 NC No Connect.

8 VDDQS Sense input for VDDQ. Used to set the on-time for the top MOSFET and also to set REF/VTT.

9 FB Feedback select input for VDDQ. See FB Confi guration Table.

10 VTTEN

Enable pin for VTT. Pull this pin low to disable VTT (REF remains present as long as VDDQ is
present).

Enable/Power Save input pin. Tie to ground to disable VDDQ. Tie to +5V to enable VDDQ and

11 EN/PSV

activate PSAVE mode. Float to enable VDDQ and activate continous conduction mode. If fl oated,
bypass to VSSA with a 10nF capacitor.

12 NC No Connect.

13 PGD

Power good output for VDDQ. PGD is low if VDDQ is outside the power good thresholds. This
pin is an open drain NMOS output and requires an external pull-up resistor.

14,15 VDDP +5V supply voltage input for the VDDQ gate drivers.

7© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

POWER MANAGEMENT

Pin Description (Cont.)

SC480

16 ILIM

Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source
for resistor sensing through a threshold sensing resistor.

17,18 PGND1 Power ground for VDDQ switching circuits. Connect to thermal pad and ground plane.

19 DL Gate drive output for the low side MOSFET switch.

20 LX Phase node - the junction between the top and bottom FETs and the output inductor.

21 DH Gate drive output for the high side MOSFET switch.

22 BST Boost capacitor connection for the high side gate drive.

23 VTTIN

24 VTT

THERMAL

T

PAD

Input supply for the high side switch for VTT regulator. Decouple with a 1μF capacitor to
PGND2.

Output of the linear regulator. Decouple with two (minimum) 10μF ceramic capacitors to
PGND2, locating them directly across pins 24 and 1.

Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected
internally.

Enable Control Logic

Enable Pin Status Output Status

EN/PSV

(1)

VTTEN VDDQ

(3)

VTT

(2)

REF

(2)

00

01

OFF, Discharged

OFF, Discharged

(2)(3)

(2)(3)

OFF, Discharged

OFF, Discharged

(2)

(2)

OFF, Discharged

OFF, Discharged

(2)

(2)

1 0 ON OFF, High Impedance ON

1 1 ON ON ON

Notes:

1) EN/PSV = 1 = EN/PSV high or fl oating.

2) Typical discharge resistances: VTT = 0.25Ω. REF = 8Ω.

3) VDDQ is discharged via external series resistance which must be added to SC480 internal discharge resistance to calculate discharge times.

This is separate from any external load on VDDQ.

FB Confi guration Table

The FB pin can be confi gured for fi xed or adjustable output voltage as shown.

FB VDDQ(V) VREF & VTT (V) Note

GND 2.5 VDDQS/2 DDR1

VCCA 1.8 VDDQS/2 DDR2

FB Resistors Adjustable VDDQS/2 1.5V < VDDQ < 3.0V

8© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Block Diagram

SC480

REF

VCCA

EN/PSV

TON

VDDQS

-10%

+16%

-30%

VDDQS

+12%

-12%

VDDQS

DSCHG

DSCHG

VMON

VCCA

VTTRUN

TON/TOFF

1.5V

VTTEN

POR/SS

1.5V
REF

VTTIN

OTSD

VTTPGD

DSCHG

DRVH

DRVL

SHOOT

LX

DL

THRU

FEDLY

OTSD

POR/SS

CONTROL

OV

SD

DRVH

NOVLP

DRVL

+12%

-12%

HI

LO

VTT

PGND2

VTTS

BST

DH

LX

VDDP

DL

FB

-10%

UV

OV

+16%

PWM

-30%

SD

VSSA

Figure 1

9© 2006 Semtech Corp. www.semtech.com

PGND1

SENSE

ILIM

PGD

FAULTMON

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

POWER MANAGEMENT

Application Information

Application Information

SC480

+5V Bias Supplies

The SC480 requires an external +5V bias supply in addition
to the battery. If stand-alone capability is required, the
+5V supply can be generated with an external linear
regulator. To minimize crosstalk, the controller has seven
supply pins: VDDP (2 pins), PGND1 (2 pins), PGND2,
VCCA and AGND.

The controller requires its own AGND plane which should
be tied by a single trace to the negative terminal of the
output capacitor. All external components referenced
to AGND in the schematic should then be connected to
the AGND plane. The supply decoupling capacitor should
be tied between VCCA and AGND. A single 10Ω resistor
should be used to decouple the VCCA supply from the
main VDDP supply. PGND can then be a separate plane
which is not used for routing analog traces. All PGND
connections should connect directly to this plane with
special attention given to avoiding indirect connections
between AGND and PGND which will create ground loops.
As mentioned above, the AGND plane must be connected
to the PGND plane at the negative terminal of the output
capacitor. The VDDP input provides power to the upper
and lower gate drivers. A decoupling capacitor for the
VDDP supply and PGND is recommended. No series
resistor between VDDP and the 5 volt bias is required.

Pseudo-Fixed Frequency Constant On-Time
PWM Controller

The PWM control method is a constant-on-time, pseudo­fi xed frequency PWM controller, see Figure 1. The ripple
voltage seen across the output capacitor’s ESR provides
the PWM ramp signal, eliminating the need for a current
sense resistor. The on-time is determined by a one-shot
whose period is proportional to output voltage, and
inversely proportional to input voltage. A separate one­shot sets the minimum off-time (typically 425ns).

On-Time One-Shot (TON)

The on-time one-shot comparator has two inputs. One
input looks at the output voltage, while the other input
samples the input voltage and converts it to a proportional
current. This current charges an internal on-time capacitor.
The TON time is the time required for this capacitor to
charge from zero volts to VOUT, thereby making the on­time of the high-side switch directly proportional to output
voltage and inversely proportional to input voltage. This
implementation results in a nearly constant switching
frequency without the need of a clock generator.

T 

RTON is a resistor connected between the input supply and
the TON pin.

VDDQ/VTT Enable & Power-Save

The EN/PSV pin controls the VDDQ supply and the REF
output (1/2 of VDDQ). VTTEN enables the VTT supply. The
VTT and VDDQ supplies may be enabled independently.
When EN/PSV is tied to VCCA the VDDQ controller is
enabled in power-save mode. When the EN/PSV pin is
fl oated, an internal resistor divider activates the VDDQ
controller with power-save disabled. If PSAVE is enabled,
the SC480 PSAVE comparator looks for inductor current
to cross zero on eight consecutive cycles. Once observed,
the controller enters power-save and turns off the low­side MOSFET when the current crosses zero. To improve
the effi ciency and add hysteresis, the on-time is increased
by 20% in power-save. The effi ciency improvement at light
loads more than offsets the disadvantage of slightly higher
output ripple. If the inductor current does not cross zero
on any switching cycle, the controller immediately exits
power-save. Since the controller counts zero crossings,
the converter can sink current as long as the current does
not cross zero on eight consecutive cycles. This allows the
output voltage to recover quickly in response to negative
load steps even when power-save is enabled.

VDDQ Voltage Selection

VDDQ voltage is set using the FB pin. Grounding FB sets
VDDQ to fi xed 2.5V. Connecting FB to +5V sets VDDQ to
fi xed 1.8V. VDDQ can also be adjusted from 1.5 to 3.0V
using external resistors, see Figure 2. The voltage at FB is
then compared to the internal 1.5V reference.

3.3x10

ON

To SC480 FB (pin 9)

10© 2006 Semtech Corp. www.semtech.com

12



To VDDQ output capacitor

37x10(RTON

R2

R3

Figure 2

V

OUT
V

IN

·
¸

ns50

¸
¹

§

3

¨

)

xx

¨
©

C

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Application Information

SC480

Referencing Figure 2, the equation for setting the output
voltage is:

R

2

1V )(UTO x

5.1

R3

Current Limit Circuit

Current limiting of the SC480 can be accomplished in two
ways. The on-state resistance of the low-side MOSFETs
can be used as the current sensing element, or a sense
resistor in the low-side source can be used if greater ac­curacy is desired. RDSON sensing is more effi cient and
less expensive. In both cases, the R

resistor between

ILIM

the ILIM pin and LX sets the over-current threshold. This
resistor R

is connected to a 10μA current source within

ILIM

the SC480 which is turned on when the low-side MOSFET
turns on. When the voltage drop across the sense resistor
or low-side MOSFET equals the voltage across the R

ILIM

resis­tor, current limit will activate. The high-side MOSFET will
not be allowed to turn on until the voltage drop across the
sense element (resistor or MOSFET) falls below the voltage
across the R

resistor.

ILIM

The current sensing circuit actually regulates the inductor
valley current, see Figure 3. This means that if the current
limit is set to 10A, the peak current through the inductor
would be 10A plus the peak ripple current, and the average
current through the inductor would be 10A plus 1/2 the
peak-to-peak ripple current.

I

PEAK

+5V +VIN

+

C1

Q1

L1

D2

Q2

+

C3

Vout

BST

DH

ILIM

VDDP

PGND

SC480

D1

C2

LX

DL

R1

Figure 4

The schematic of RDSON sensing circuit is shown in Figure
4 with R

= R1 and RDS

ILIM

of Q2.

ON

Similarly, for resistor sensing, the current through the lower
MOSFET and the source sense resistor develops a voltage
that opposes the voltage developed across R
voltage developed across the R
drop across R

an over-current exists and the high-side

ILIM,

resistor reaches voltage

SENSE

. When the

ILIM

MOSFET will not be allowed to turn on. The over-current
equation when using an external sense resistor is:

R



IL x

OC

Aƫ10Valley

ILIM

R

SENSE

Schematic of resistor sensing circuit is shown in Figure 5
with R

= R1 and R

ILIM

= R4.

SENSE

+5V

+VIN

I

LOAD

I

LIMIT

INDUCTOR CURRENT

TIME

Valley Current

- Limit Threshold Point

Figure 3

11© 2006 Semtech Corp. www.semtech.com

BST

DH

ILIM

VDDP

PGND

SC480

+

D1

C2

LX

DL

R1

C1

Q1

L1

D2

Q2

R4

+

C3

Vout

Figure 5

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

POWER MANAGEMENT

Application Information (Cont.)

SC480

Power Good Output

The VDDQ controller has a power good (PGD) output.
Power good is an open-drain output and requires a pull­up resistor. When the output voltage is +16%/-10% from
its nominal voltage, PGD gets pulled low. It is held low
until the output voltage returns to within +16%/-10% of
nominal. PGD is also held low during start-up and will not
be allowed to transition high until soft-start is over and the
output reaches 90% of its set voltage. There is a 5μs delay
built into the PGD circuit to prevent false transitions.

Output Over-Voltage Protection

When the VDDQ output exceeds 16% of its set voltage,
the low-side MOSFET is latched on. It stays latched and
the SMPS stays off until the EN/PSV input is toggled or
VCCA is recycled. There is a 5μs delay built into the OV
protection circuit to prevent false transitions. During a
VDDQ OV shutdown, VTT is alive until VDDQ falls to typically

0.4V, at which point VTT is tri-stated.

When VTT exceeds 12% above its set voltage, the VTT
regulator will tristate. There is a 50μs delay to prevent false
OV trips due to transients or noise. The VDDQ regulator
continues to operate after VTT OV shutdown. The VTT OV
condition is removed by toggling VTTEN or EN/PSV, or by
recycling VCCA.

Smart Over-Voltage Protection

In some applications, the active loads on VDDQ can
actually leak current into VDDQ. If PSAVE mode is enabled
at very light loading, this leak can cause VDDQ to slowly
rise and reach the OV threshold, causing a hard shutdown.
To prevent this, the SC480 uses Smart OVP to prevent
this. When VDDQ exceeds 8% above nominal, DL drives
high to turn on the low-side MOSFET, which starts to draw
current from VDDQ via the inductor. When VDDQ drops
to the FB trip point, a normal TON switching cycle begins.
This prevents a hard OV shutdown.

Output Under-Voltage Protection

When VDDQ falls 30% below its set point for eight clock
cycles, the VDDQ output is shut off; the DL/DH drives are
pulled low to tristate the MOSFETS, and the SMPS stays
off until the Enable input is toggled or VCCA is recycled.
When VTT is 12% below its set voltage the VTT output is
tristated. There is a 50μs delay for VTT built into the UV
protection circuits to prevent false transitions.

POR, UVLO and Soft-Start

An internal power-on reset (POR) occurs when VCCA ex­ceeds 3V, resetting the fault latch and soft-start counter,
and preparing the PWM for switching. VCCA under-voltage
lockout (UVLO), circuitry inhibits switching and tristates the
drivers until VCCA rises above 4.2V. At this time the circuit
will come out of UVLO and begin switching and the soft­start circuit will progressively limit the output current over
a pre-determined time period. The ramp occurs in four
steps: 25%, 50%, 75% and 100%, thereby limiting the slew
rate of the output voltage. There is 100mV of hysteresis
built into the UVLO circuit and when VCCA falls to 4.1V the
output drivers are shutdown and tristated.

MOSFET Gate Drivers

The DH and DL drivers are optimized for moderate, high­side, and larger low-side power MOSFETs. An adaptive
dead-time circuit monitors the DL output and prevents the
high-side MOSFET from turning on until DL is fully off, and
conversely, monitors the DH output and prevents the low­side MOSFET from turning on until DH is fully off. (Note:

be sure there is low resistance and low inductance between the
DH and DL outputs to the gate of each MOSFET.)

Design Procedure

Prior to designing a switch mode supply for a notebook com­puter, the input voltage, load current, switching frequency
and inductor ripple current must be specifi ed.

Input Voltage Range

The maximum input voltage (VIN
highest AC adaptor voltage. The minimum input voltage
(VIN

) is determined by the lowest battery voltage after

MIN

accounting for voltage drops due to connectors, fuses and
battery selector switches.

Maximum Load Current

There are two values of load current to consider: continu­ous load current and peak load current. Continuous load
current has more to do with thermal stresses and there­fore drives the selection of input capacitors, MOSFETs
and commutation diodes. Peak load current determines
instantaneous component stresses and fi ltering require-
ments such as, inductor saturation, output capacitors and
design of the current limit circuit.

) is determined by the

MAX

12© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Application Information (Cont.)

SC480

Switching Frequency

Switching frequency determines the trade-off between
size and effi ciency. Higher frequency increases switch-
ing losses in the MOSFETs, since losses are a function of
F*VIN2. Knowing the maximum input voltage and budget
for MOSFET switches usually dictates the fi nal design.

Inductor Ripple Current
Low inductor values result in smaller size, but create high­er ripple current and are less effi cient because of the high
AC current fl owing in the inductor. Higher inductor values
do reduce the ripple current and are more effi cient, but
are larger and more costly. The selection of the ripple cur­rent is based on the maximum output current and tends
to be between 20% to 50% of the maximum load current.
Again, cost, size and effi ciency all play a part in the selec-
tion process.

Stability Considerations

Unstable operation shows up in two related but distinctly
different ways: double pulsing and fast-feedback loop in­stability. Double-pulsing occurs due to noise on the output
or because the ESR is too low, causing insuffi cient voltage
ramp in the output signal. This causes the error amplifi er to
trigger prematurely after the 400ns minimum off-time has
expired. Double-pulsing will result in higher ripple voltage at
the output, but in most cases is harmless. In some cases,
however, double-pulsing can indicate the presence of loop
instability, which is caused by insuffi cient ESR. One simple
way to solve this problem is to add some trace resistance
in the high current output path. A side effect of doing this
is output voltage droop with load. Another way to eliminate
doubling-pulsing is to add a 10pF capacitor across the
upper feedback resistor divider network. This is shown in
Figure 6, by capacitor C4 in the schematic. This capacitance
should be left out until confi rmation that double-pulsing ex-
ists. Adding this capacitance will add a zero in the transfer
function and should eliminate the problem. It is best to
leave a spot on the PCB in case it is needed.

Loop instability can cause oscillations at the output as a
response to line or load transients. These oscillations can
trip the over-voltage protection latch or cause the output
voltage to fall below the tolerance limit.

The best way for checking stability is to apply a zero to
full load transient and observe the output voltage ripple
envelope for overshoot and ringing. Over one cycle of
ringing after the initial step is a sign that the ESR should
be increased.

BST

DH

ILIM

VDDP

DL

PGND

SC480

+5V

14
13
12

LX

11
10
9
8

+VIN

+

D1

C2

R1

C1

Q1

L1

D2

Q2

FBK

+

C3

R2

R3

C4
10pF

0.5V - 5.5V

Figure 6

SC480 ESR Requirements

The constant on-time control used in the SC480 regulates
the ripple voltage at the output capacitor. This signal
consists of a term generated by the output ESR of the
capacitor and a term based on the increase in voltage
across the capacitor due to charging and discharging
during the switching cycle. The minimum ESR is set to
generate the required ripple voltage for regulation. For most
applications the minimum ESR ripple voltage is dominated
by PCB layout and the properties of SP or POSCAP type
output capacitors. For applications using ceramic output
capacitors, the absolute minimum ESR must be considered.
If the ESR is low enough the ripple voltage is dominated
by the charging of the output capacitor. This ripple voltage
lags the on-time due to the LC poles and can cause double
pulsing if the phase delay exceeds the off-time of the
converter. Referring to Figure 5 on Page 11, the equation
for the minimum ESR as a function of output capacitance
and switching frequency and duty cycle is:

!

§

ESR

¨
©

VOUT

1.5V

§
¨

·

¨

x

¸

¨

¹

¨
©

200000-Fs

§

x

31

¨

Fs

©

FsCoutƯ2



·

·
¸

¸
¹

¸

2

¸

xxxx

D1

¸
¹

13© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

POWER MANAGEMENT

Application Information (Cont.)

SC480

Dropout Performance

The output voltage adjust range for continuous-conduction
operation is limited by the fi xed 400nS (typical) Minimum
Off-time One-shot. For best dropout performance, use the
slowest on-time setting of 200KHz. When working with
low input voltages, the duty-factor limit must be calculated
using worst-case values for on and off times. The IC duty-

factor limitation is given by:

DUTY 

Be sure to include inductor resistance and MOSFET on­state voltage drops when performing worst-case dropout
duty-factor calculations.

SC480 System DC Accuracy (VDDQ Controller)

Three IC parameters affect VDDQ accuracy: the internal

1.5V reference, the error comparator offset voltage, and
the switching frequency variation with line and load.

The internal 1%, 1.5V reference contains two error
components, a 0.5% DC error and a 0.5% supply and
temperature error. The error comparator offset is trimmed
so that it trips when the feedback pin is nominally 1.5
volts +/-1% at room temperature. The comparator offset
trim compensates for any DC error in the reference. Thus,
the percentage error is the sum of the reference variation
over supply and temperature and the offset in the error
comparator, or 1.5% total.

The on-time pulse in the SC480 is calculated to give a
pseudo-fi xed frequency. Nevertheless, some frequency
variation with line and load can be expected. This variation
changes the output ripple voltage. Because constant on­time converters regulate to the valley of the output ripple,
½ of the output ripple appears as a DC regulation error.
For example, If the output ripple is 50mV with VIN = 6
volts, then the measured DC output will be 25mV above
the comparator trip point. If the ripple increases to 80mV
with VIN = 25 volts, then the measured DC output will
be 40mV above the comparator trip. The best way to
minimize this effect is to minimize the output ripple.

To compensate for valley regulation it is often desirable
to use passive droop. Take the feedback directly from the
output side of the inductor, incorporating a small amount

(MIN)TON

(MAX)TOFF(MIN)TON

of trace resistance between the inductor and output
capacitor. This trace resistance should be optimized
so that at full load the output droops to near the lower
regulation limit. Passive droop minimizes the required
output capacitance because the voltage excursions due
to load steps are reduced.

Board components and layout also infl uence DC accuracy.
The use of 1% feedback resistors contributes up to 1%
error. If tighter DC accuracy is required use 0.1% feedback
resistors.

The output inductor value may change with current. This
will change the output ripple and thus the DC output
voltage (it will not change the frequency).

Switching frequency variation with load can be minimized
by choosing lower RDS
will cause the switching frequency to increase as the load
current increases. This will reduce the ripple and thus
the DC output voltage. This inherent droop should be
considered when deciding if passive droop is required, or
if passive droop is desired in order to further reduce the
output capacitance.

Output DC Accuracy (VTT Output)

The VTT accuracy compared to VDDQ is determined by
two parameters: the REF output accuracy, and the VTT
output accuracy with respect to REF. The REF output
is generated internally from the VDDQS (sense input),
and tracks VDDQS with 2% accuracy. This REF output
becomes the reference for the VTT regulator. The VTT
regulator then tracks REF within +/-40mV (typically zero).
The total VTT/VDDQ tracking accuracy is then:

DDR Reference Buffer

The reference buffer is capable of sourcing 10mA. The
reference buffer has a class A output stage and therefore
will not sink signifi cant current; there is an internal 50 kΩ
(typical) pulldown to ground. If higher current sinking is
required, an external pulldown resistor should be added.
Make sure that the ground side of this pulldown is tied to
the VTT ground plane near the PGND2 pin.

MOSFETs. High RDSON MOSFETS

ON

VDDQS

error VTT rrx

2

40mV 0.02

14© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

t

t

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Application Information (Cont.)

SC480

For stability, place a 10Ω/1μF series combination from
REF to VSSA. If REF load capacitance exceeds 1μF, place
at least 10Ω in series with the load capacitance to prevent
instability. It is possible to use only one 10Ω resistor, by
connecting the load capacitors in parallel with the 1μF,
and connecting the load REF to the capacitor side of the
10Ω resistor. (See the Typical Application Circuit on Page

1.) Note that this resistor creates an error term when REF
has a DC load. In most applications this is not a concern
since the DC load on REF is negligible.

Design Procedure

Prior to designing a switching output and making com­ponent selections, it is necessary to determine the input
voltage range and output voltage specifi cations. To dem-
onstrate the procedure, the output for the schematic in

Figure 7 on page 18 will be designed.

The maximum input v

oltage (V

) is determined by the

BAT(MAX)

highest AC adaptor voltage. The minimum input voltage
(V

) is determined by the lowest battery voltage af-

BAT(MIN)

ter accounting for voltage drops due to connectors, fuses
and battery selector switches. For the purposes of this
design example we will use a VBAT range of 8V to 20V to
design VDDQ.

ª

t

«

N)ON_VBAT(MI

«
¬

12





10 3.3

x

R

tON

3



1037

xxx

V

V

OUT

º
»
»

)MIN(BAT

¼

9



s

1050

x

and,

ª

t

«

X)ON_VBAT(MA

«
¬

12





10 3.3

x

R

tON

3



1037

xxx

V

From these values of tON we can calculate the nominal
switching frequency as follows:

V

x

OUT

t

f

(MIN)SW_VBAT

§

V

¨

BAT(MIN)

©

V

OUT

º
»
»

)MAX(BAT

¼

Hz

·
¸

N)ON_VBAT(MI

¹

9



s

1050

x

and,

V

f

(MAX)SW_VBAT

§

V

¨

BAT(MAX)

©

tON is generated by a one-shot comparator that samples
V

via R

BAT

, converting this to a current. This current is

tON

used to charge an internal 3.3pF capacitor to V
equations above refl ect this along with any internal com-
ponents or delays that infl uence tON. For our example we
select R

= 1MΩ:

tON

OUT

x

t

Hz

·

¸

X)ON_VBAT(MA

¹

. The

OUT

Four parameters are needed for the design:

Nominal output voltage, V

1.

. We will use 1.8V with

OUT

internal feedback resistors (FB pin tied to VCCA).
Static (or DC) tolerance, TOLST (we will use +/-2%).

2.
Transient tolerance, TOLTR and size of transient (we

3.
will use +/-8% for a 10A to 5A load release for this
demonstration).
Maximum output current, I

4.

(we will design for 10A).

OUT

Switching frequency determines the trade-off between
size and effi ciency. Increased frequency increases
the switching losses in the MOSFETs, and losses are a
function of VBAT2. Knowing the maximum input voltage
and budget for MOSFET switches usually dictates where
the design ends up. The default R

values of 1MΩ and

tON

715k Ω are suggested only as a starting point.

The fi rst thing to do is to calculate the on-time, tON, at
V

BAT(MIN)

and V

, since this depends only upon V

BAT(MAX)

BAT

, V

OUT

and RtON.

t

ON_VBAT(MIN)

f

SW_VBAT(MIN)

= 820ns and, t

= 274kHz and f

ON_VBAT(MAX)

SW_VBAT(MAX)

= 358ns

= 251kHz

Now that we know tON we can calculate suitable values for
the inductor. To do this we select an acceptable inductor
ripple current. The calculations below assume 50% of I
which will give us a starting place.



L

(MIN)VBAT

V

BAT(MIN)

V

OUT

x

§

¨
©

(MIN)ON_VBAT

H

·

I0.5

x

¸

OUT

¹

and,

x

I0.5

OUT

X)ON_VBAT(MA

·

¸
¹



L

(MAX)VBAT

V

BAT(MAX)

V

OUT

x

§

¨
©

For our example:

L

= 1.02μH and L

VBAT(MIN)

VBAT(MAX)

= 1.30μH,

OUT

H

15© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

PP

A

L

)MIN(VBATON_

t

OUT

V

)MIN(BAT

V

)MIN(BATRIPPLE_V

I



x

¸
¹

·

¨
©

§



PP

A

L

)MAX(VBATON_

t

OUT

V

)MAX(BAT

V

)MAX(BATRIPPLE_V

I



x

¸
¹

·

¨
©

§



(MIN)

A

2

)MAX(TRIPPLE_VBA

I

)MAX(OUT

I

)MIN(INDUCTOR

I 





Ohms

)MAX(BATV_RIPPLE

I

2

DC

ERR

ST

ERR

)MAX(ST_ESR

R

x



Ohms

2

)MAX(TRIPPLE_VBA

I

TRANS

I

DC

ERR

TR

ERR

)MAX(TRESR_

R

¸

¸
¹

·

¨

¨
©

§


¸
¹

·

¨
©

§



NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

POWER MANAGEMENT

Application Information (Cont.)

SC480

We will select an inductor value of 1.5μH to reduce the
ripple current, which can be calculated as follows:

and,

For our example:

I

RIPPLE_VBAT(MIN)

= 3.39A

P-P

and I

RIPPLE_VBAT(MAX)

= 4.34A

P-P

From this we can calculate the minimum inductor current
rating for normal operation:

For our example:

I

INDUCTOR(MIN)

= 12.2A

(MIN)

Next we will calculate the maximum output capacitor
equivalent series resistance (ESR). This is determined by
calculating the remaining static and transient tolerance
allowances. Then the maximum ESR is the smaller of the
calculated static ESR (R
(R

ESR_TR(MAX)

Where ERR

):

is the static output tolerance and ERR

ST

ESR_ST(MAX)

) and transient ESR

is

DC

the DC error. The DC error will be 1% plus the tolerance
of the internal feedback. (Use 2% for external feedback,
which is 1% plus another 1% for the external resistors.)

For our example:

ERR

= 36mV and, ERR

ST

R

ESR_ST(MAX)

= 8.3mΩ

= 18mV, therefore,

DC

where ERRTR is the transient output tolerance. For this
case, I

is the load transient of 5A (10A - 5A).

TRANS

For our example:

ERRTR = 144mV and ERR

R

ESR_TR(MAX)

= 17.6mΩ for a full 5A load transient.

= 18mV, therefore,

DC

We will select a value of 6mΩ maximum for our design,
which would be achieved by using two 12mΩ output ca­pacitors in parallel. Now that we know the output ESR we
can calculate the output ripple voltage:

ESR

I

x

PPV)MIN(TRIPPLE_VBA



V

R

)MIN(TRIPPLE_VBA

and,

ESR

I

x

PPV)MAX(TRIPPLE_VBA



V

R

)MAX(TRIPPLE_VBA

For our example:

V

RIPPLE_VBAT(MAX)

= 20mV

and V

P-P

RIPPLE_VBAT(MIN)

= 26mV

P-P

Note that in order for the device to regulate in a controlled
manner, the ripple content at the feedback pin, VFB, should
be approximately 15mV
no smaller than 10mV

at minimum V

P-P

. Note that the voltage ripple at

P-P

, and worst case

BAT

FB is smaller than the voltage ripple at the output capaci­tor, due to the resistor divider. Also, when using internal
feedback (FB pin tied to 5V or GND), the FB resistor di­vider is actually inside the IC. If V
the FB point is less than 15mV

- whether internal or ex-

P-P

RIPPLE_VBAT(MIN)

as seen at

ternal FB is used - the above component values should be
revisited in order to improve this. For our example, since
the internal divider reduces the ripple signal by a factor of
(1.5V/1.8V), the internal FB ripple values are then 17mV
and 22mV, which is above the 15mV minimum.

When using external feedback, and with VDDQ greater
than 1.5V, a small capacitor, C
with the top feedback resistor, R
ripple at VFB is large enough. C
than 100pF. The value of C
lows, where R
calculating the value of Z

is the bottom feedback resistor. Firstly

BOT

TOP

, can be used in parallel

TOP

, in order to ensure that

TOP

should not be greater

TOP

can be calculated as fol-

TOP

required:

16© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Application Information (Cont.)

R

Z

TOP

BOT

0.015

Secondly calculating the value of C
this:



)MIN(TRIPPLE_VBA

TOP

x

Ohms0.015V

required to achieve

SC480

at its highest. The capacitance required for smaller tran­sient steps my be calculated by substituting the desired
current for the I
For our example:

C

OUT(MIN)

= 392μF.

term. In this case I

fi nal

is set for 5A.

fi nal

C

TOP

§

1

¨
¨
©

Z

xx



TOP
fƯ2

R

1

TOP

·
¸
¸
¹

F

)MIN(VBAT_SW

Since our example uses internal feedback ,this method
cannot be used, however the voltage seen at the internal
FB point is already greater than 15mV.

Next we need to calculate the minimum output capaci­tance required to ensure that the output voltage does not
exceed the transient maximum limit, POSLIMTR, starting
from the actual static maximum, V

OUT_ST_POS

, when a load

release occurs:

V 

OUT_ST_POS

V

OUT

ERR

DC

V

For our example:

V

OUT_ST_POS

= 1.818V,

POSLIM x

TR

V

OUT

TOL

TR

V

Where TOLTR is the transient tolerance. For our example:

POSLIMTR = 1.944V,

We will select 440μF, using two 220μF, 12mΩ capacitors
in parallel.

Next we calculate the RMS input ripple current, which is
largest at the minimum battery voltage:

I



VVVI xx

OUT)MIN(BATOUT)RMS(IN

OUT

V

A

RMS

MIN_BAT

For our example:

I

IN(RMS)

= 4.17A

RMS

Input capacitors should be selected with suffi cient ripple
current rating for this RMS current, for example a 10μF,
1210 size, 25V ceramic capacitor can handle approxi­mately 3A

. Refer to manufacturer’s data sheets and

RMS

derate appropriately.

Finally, we calculate the current limit resistor value. As de­scribed in the current limit section, the current limit looks
at the “valley current”, which is the average output cur­rent minus half the ripple current.

I 

VALLEY

I

OUT

I

2

)MIN(TRIPPLE_VBA

A

The minimum output capacitance is calculated as fol­lows:

I 

init

I

I

)MAX(OUT

2

)MAX(TRIPPLE_VBA

A

The ripple at low battery voltage is used because we want
to make sure that current limit does not occur under nor­mal operating conditions.

and,

Ifinal

2

F

2

For our example:

I

VALLEY

2

 

C

OUT(MIN)

L

x



Iinit

POSLIM

TR



2

V



OUT_ST_POS

This calculation assumes the condition of a full-load to no­load step transient occurring when the inductor current is

17© 2006 Semtech Corp. www.semtech.com



R

ILIM

I

VALLEY

= 8.31A, R

1.2

= 4mΩ, giving R

DS(ON)

x

(ON)DS

1010

x

1.4

6



= 5.62kΩ

ILIM

Ohms

R

xx

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

POWER MANAGEMENT

Application Information (Cont.)

SC480

Thermal Considerations

The junction temperature of the device may be calculated
as follows:

T

where TJ is the junction temperature, T
temperature, PD is the total SC480 device dissipation,

The SC480 device dissipation can be determined using:

PD = VCCA • ICCA + VDDP • IDDP + VTT • |ITT|

The fi rst two terms are losses for the analog and gate drive
circuits and generally do not present a thermal problem.
Typical ICCA (VCCA operating current) is roughly 1.5mA,
which creates 7.5mW loss from the 5V VCCA supply. The
VDDP supply current is used to drive the MOSFETs and
can be much higher, on the order of 30mA, which can
create up to 150mW of dissipation.

The last term, VTT * |ITT|, is the most signifi cant term
from a thermal standpoint. The VTT regulator is a linear
device and will dissipate power proportional to the VTT
current and the voltage drop across the regulator. If VTT
= VDDQ/2, then the voltage drop across the regulator
is always VDDQ2, regardless of whether the regulator is
sinking or sourcing current. In either case the power lost
in the VTT regulator is VTT * |ITT|. The average or long­term value for ITT should be used.

The thermal resistance of the MLPQ package is affected
by PCB layout and the available ground planes and vias
which conduct heat away. A typical value is 29°C/watt.

Example: ICCA = 1.5mA IDDP = 25mA
VCCA = VDDP = 5V
VTT = 1.25V
ITT = 0.75A (average)
Ambient = 45 degrees C
Thermal resistance = 29

PD = 5V • 0.0015 A + 5V • 0.025A + 0.9V • |0.75|A

PD = 0.808W

TJ = T

+ PD • TJA = 45 + 0.808W • 29°C/W = 68.4°C

AMB

= T

J

AMB

+ θ

JA

is the ambient

AMB

Layout Guidelines

One (or more) ground planes are recommended to
minimize the effect of switching noise and copper losses,
and maximize heat dissipation. The IC ground reference,
VSSA, should be connected to PGND1 and PGND2 as a
star connection at the thermal pad, which in connects
using 4 vias to the ground plane. All components that are
:

referenced to VSSA should connect to it directly on the
chip side, and not through the ground plane.

VDDQ: The feedback trace must be kept far away from
noise sources such as switching nodes, inductors and
gate drives. Route the feedback trace in a quiet layer if
possible, from the output capacitor back to the chip. Chip
supply decoupling capacitors (VCCA, VDDP) should be
located next to the pins (VCCA/VSSA, VDDP/PGND1) and
connected directly to them on the same side.

VTT: Because of the high bandwidth of the VTT regulator,
proper component placement and routing is essential to
prevent unwanted high-frequency oscillations which can
be caused by parasitic inductance and noise. The input
capacitors should be located at the VTT input pins (VTTIN
and PGND2), as close as possible to the chip to minimize
parasitics. Output capacitors should be directly located at
the VTT output pins (VTT and PGND2). The routing of the
feedback signal VTTS is critical. The trace from VTTS (pin

2) should be connected directly to the output capacitor
that is farthest from VTT (pin24); route this signal away
from noise sources such as the VDDQ power train or high­speed digital signals.

The switcher power section should connect directly to the
ground plane(s) using multiple vias as required for current
handling (including the chip power ground connections).
Power components should be placed to minimize loops
and reduce losses. Make all the connections on one side
of the PCB using wide copper fi lled areas if possible. Do
not use “minimum” land patterns for power components.
Minimize trace lengths between the gate drivers and the
gates of the MOSFETs to reduce parasitic impedances
(and MOSFET switching losses); the low-side MOSFET is
most critical. Maintain a length to width ratio of <20:1 for
gate drive signals. Use multiple vias as required by current
handling requirement (and to reduce parasitics) if routed
on more than one layer. Current sense connections must
always be made using Kelvin connections to ensure an

18© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Application Information (Cont.)

SC480

accurate signal. The layout can be generally considered
in three parts; the control section referenced to VSSA, the
VTT output, and the switcher power section.

Looking at the control section fi rst, locate all components
referenced to VSSA on the schematic and place these
components at the chip. Connect VSSA using a wide
(>0.020”) trace. Very little current fl ows in the chip ground
therefore large areas of copper are not needed. Connect
the VSSA pin directly to the thermal pad under the device
as the only connection from PGND1 and PGND2 from
VSSA.

Decoupling capacitors for VCCA/VSSA and VDDP/PGND1
should be placed is as close as possible to the chip. The
feedback components connected to FB, along with the
VDDQ sense components, should also be located at the
chip. The feedback trace from the VDDQ output should
route from the top of the output capacitors, in a quiet
layer back to the FB components.

Next, looking at the switcher power section, there are a
few key guidelines to follow:

Finally, connecting the control and switcher power sections
should be accomplished as follows:

Route VDDQ feedback trace in a “quiet” layer, away

1.
from noise sources.
Route DL, DH and LX (low side FET gate drive, high

2.
side FET gate drive and phase node) to the chip using
wide traces with multiple vias if using more than one
layer. These connections are to be as short as possible
for loop minimization, with a length to width ratio less
than 20:1 to minimize impedance. DL is the most
critical gate drive, with power ground as its return
path. LX is the noisiest node in the circuit, switching
between VBAT and ground at high frequencies, thus
should be kept as short as practical. DH has LX as its
return path.
BST is also a noisy node and should be kept as short

3.
as possible.
Connect PGND1 pins on the chip directly to the VDDP

4.
decoupling capacitor and then drop vias directly to
theground plane. Locate the current limit resistor at
the chip with a kelvin connection to the phase node.

There should be a very small input loop, well

1.
decoupled.
The phase node should be a large copper pour, but

2.
still compact since this is the noisiest node.
Input power ground and output power ground should

3.
not connect directly, but through the ground planes
instead.

19© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

POWER MANAGEMENT

Application Information (Cont.)

SC480

VTT

VBAT

REF

VDDQ

5V

VDDQ

C5

10uF
0805

R2 1MEG

C13
1nF

C6

10uF

0805 0805

C7
10uF

R5 10R

C14

1uF

5V

C8

0.1uF

R3 10R

C4

1uF

C15

1uF

MBR0530

1

2

3

4

5

6

D1

PGND2

VTTS

VSSA

TON

REF

VCCA

C16

0.1uF

C1 0.1uF

Q1

IRF7811

Q2

IRF7832

BST

U1

FB

20DL19

LX

ILIM

PGD

PAD

18

17

16

15

14

13

PAD

PGND1

PGND1

VDDP

VDDP

EN/PSV

VTTEN

10

NC

12

11

23

24

22DH21

VTT

VTTIN

SC480

VDDQS

NC

7

9

8

L1

1.5uH

Vishay IHLP-5050

R1

5.62K

C9*

220uF/12m

*Sanyo 4TPL220MC

C12
1uF

C2
10uF/25V

1210

+

C10*

220uF/12m

R4

10K

EN/PSV

VTT_EN

PGOOD

VDDQ

+

5V

VBAT

C3

10uF/25V
1210

C11

0.1uF

1.8V fixed: connect to 5V

2.5V fixed: connect to VSSA
Adjustable 1.5V-3.0V: connect to divider network

Figure 7 - Reference Design

20© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Typical Characteristics

SC480

1.8V Effi ciency vs. Output Current

100%

90%

VBAT = 20

80%

70%

Efficiency (%)

60%

50%

0246810

Powersave Mode

VBAT = 10

I

OUT

(A)

2.5V Effi ciency vs. Output Current

100%

VBAT = 10

90%

Powersave Mode

VBAT = 20

1.8V Effi ciency vs. Output Current

100%

90%

80%

70%

Efficiency (%)

60%

50%

0246810

Continuous Conduction Mode

VBAT = 10

VBAT = 20

I

(A)

OUT

2.5V Effi ciency vs. Output Current

100%

90%

Continuous Conduction Mode

VBAT = 10

VBAT = 20

80%

70%

Efficiency (%)

60%

50%

0246810

I

(A)

OUT

1.5V Effi ciency vs. Output Current

100%

90%

80%

70%

Efficiency (%)

60%

VBAT = 10

Powersave Mode

VBAT = 20

80%

70%

Efficiency (%)

60%

50%

0246810

I

(A)

OUT

1.5V Effi ciency vs. Output Current

100%

90%

80%

70%

Efficiency (%)

60%

Continuous Conduction Mode

VBAT = 10

VBAT = 20

50%

0246810

I

(A)

OUT

21© 2006 Semtech Corp. www.semtech.com

50%

0246810

I

OUT

(A)

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

POWER MANAGEMENT

Typical Characteristics (Cont.)

Load Transient Response, 0 to 5A, Psave Mode

SC480

Load Transient Response, 0 to 5A,

Continuous Conduction Mode

Load Transient Response, 5 to 0A, Psave Mode

Load Transient Response, 5 to 10A

Load Transient Response, 5 to 0A,

Continuous Conduction Mode

Load Transient Response, 10 to 5A

22© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Typical Characteristics (Cont.)

SC480

VTT Load Transient Response,

1A Sink/Source, Psave Mode

Startup (PSV), EN/PSV Going High

VTT Load Transient Response, 1A Sink/Source,

Continuous Conduction Mode

Startup (PSV), EN/PSV Going Low, VDDQ = 5A

23© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

POWER MANAGEMENT

Outline Drawing - MLPQ 24 (4x4mm)

SC480

A

PIN 1

INDICATOR

(LASER MARK)

A

aaa

C

NOTES:

1.

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.

2.

A1

E1

2

1

N

D/2

D

D1

e

B

E

A2

C

LxN

E/2

bxN

bbb C A B

SEATING

PLANE

DIM

MIN

.031

A

.000

A1
A2

b

.007

D

.151 .163

D1

.100

E

.151 .163

E1

.100

e
L

.011

N

aaa
bbb

DIMENSIONS

INCHES

NOM

MAX

.035

.001

-

(.008)

.010
.157
.106
.157
.106 .110 2.55

.020 BSC

.016

24
.004
.004

MILLIMETERS
MIN

.040

0.80

0.00

.002

-

0.18.012

2.55

.110

0.30

.020

NOM

0.90

0.02

-

(0.20)

0.25

4.00

2.70

4.00 4.153.85

2.70

0.50 BSC

0.40
24

0.10

0.10

MAX

1.00

0.05

-

0.30

4.153.85

2.80

2.80

0.50

24© 2006 Semtech Corp. www.semtech.com

POWER MANAGEMENT

NOT RECOMMENDED FOR NEW DESIGN

NOT RECOMMENDED

FOR NEW DESIGN

Land Pattern - MLPQ 24 (4x4mm)

K

(C)

H

SC480

DIMENSIONS

DIM

C
G

G

Z

H
K
P
X
Y
Z

(.155)

.122
.106
.106
.021
.010
.033

MILLIMETERSINCHES

(3.95)

3.10

2.70

2.70

0.50

0.25

0.85

4.80.189

X

P

NOTES:

1.

THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.

Contact Information

Semtech Corporation

Power Management Products Division

200 Flynn Road, Camarillo, CA 93012

Phone: [phone] Fax: [phone]

www.semtech.com

25© 2006 Semtech Corp. www.semtech.com