Datasheet SC4519H Datasheet (SEMTECH)

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SC4519H

600kHz, 3A Step-Down

Switching Regulator

Description

The SC4519H is a current mode switching regulator with
an integrated switch, operating at 600kHz with separate
sync and enable functions. The integrated switch allows
for cost effective low power solutions (peak switch current
3 amps). The sync function allows customers to
synchronize to a faster clock in order to avoid frequency
beating in noise sensitive applications. High frequency
of operation allows for very small passive components.
Current mode operation allows for fast dynamic response
and instantaneous duty cycle adjustment as the input
varies (ideal for CPE applications where the input is a
wall plug power).

The low shutdown current makes it ideal for portable
applications where battery life is important.

The SC4519H is a 600kHz switching regulator
synchronizable to a faster frequency from 750kHz to

1.2MHz.

Features

 Integrated 3 Amp switch
 600kHz frequency of operation
 Current mode controller
 Synchronizable to higher frequency up to 1.2MHz
 Precision enable threshold
 SO-8 EDP package. Lead free product, fully WEEE

and RoHS compliant

Applications

 XDSL modems
 CPE equipment
 DC-DC point of load applications
 Portable equipment

Typical Application Circuit

VIN

Enable

C3

2

5

8

IN

EN

SYNC

1

BST

SC4519H

GND

4

SW

FB

COMP

C4

3

6

7

R3

C1

D1

D2

L1

VOUT

R1

C2

R2

Revision: September 11, 2007

1 www.semtech.com

SC4519H

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Absolute Maximum Ratings

Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may
affect device reliability.

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V(

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BF

BF

CNYS

θ

AJ

A

J

GTS

DAEL

)1(

82+ot3.0-

V

23+ot3.0-V

42+ot3.0-V

6+ot3.0-V

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1Am

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W/C°

58+ot04-C°

051+C°

051+ot56-C°

003C°

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Notes:
(1) For proper operation of device, VIN should be within maximum Operating Input Voltage as defined in Electrical
Characteristics.
(2) ThetaJA is calculated from a package in still air, mounted to 3" x 4.5", 4 layer FR4 PCB with thermal vias under exposed
pad per JESD51 standards.

Electrical Characteristics

Unless specified: VIN = 12V, V
TA = TJ = -40°C to 125°C.

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V

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V

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tnerruCylppuSI

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= 0.8V, V

COMP

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timiLtnerruChctiwSmumixaMI

porDegatloVnOhctiwSV

tuokcoLegatlovrednUV

= VIN + 5V, EN = tied to VIN, SYNC = 0, SW = open.

BST

NI

WS

CSO

)WS(D

OLVU

Q

)FFO(Q

T

A

I

A3=022Vm

WS

V

V

V1=35Am

BF

V0=001051Aµ

NE

2 2007 Semtech Corp. www.semtech.com

)1(

42

V

%05=D,C°52=5.35.5A

005006007zHk

9.34.4V

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Electrical Characteristics (Cont.)

Unless specified: VIN = 12V, V
T

= TJ = -40°C to 125°C.

A

RETEMARAPLOBMYSSNOITIDNOCNIMPYTXAMSTINU

COMP

= 0.8V, V

= VIN + 5V, EN = tied to VIN, SYNC = 0, SW = open.

BST

SC4519H

tnerruCtupnIBFI

BF

52.0-1-Aµ

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PMOC

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PMOC

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PMOC

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)3(

niaGegatloV

tnerruCecruoSniPV

tnerruCkniSniPV

tnerruChctiwSotniP

V9.0 ≤ V

∆ I

V

≤ V0.2051053V/V

PMOC

= ± Aµ01

PMOC

V6.0=07011Aµ

BF

V0.1=07-011-Aµ

BF

PMOC

V52.1=5V/A

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A1=0151Am

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A3=0354

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7.2V

3 2007 Semtech Corp. www.semtech.com

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Electrical Characteristics (Cont.)

SC4519H

Unless specified: VIN = 12V, V

= TJ = -40°C to 125°C.

T

A

COMP

= 0.8V, V

= VIN + 5V, EN = tied to VIN, SYNC = 0, SW = open.

BST

RETEMARAPLOBMYSSNOITIDNOCNIMPYTXAMSTINU

egatloVdlohserhTtupnIelbanEV

tnerruCsaiBtuptuOelbanEI

HTE

LOE

I

HOE

dlohserhtwolebVm05=NE8Aµ

dlohserhtevobaVm05=NE01Aµ

1.172.15.1V

egatloVdlohserhTCNYS 5.1V

)4(

ycneuqerFtupnICNYS

ecnatsiseRniPCNYSV

V5.0=02kΩ

CNYS

0080021zHk

Notes:
(1) The device may not function properly outside its operating input voltage range.
(2) The required minimum input voltage for a regulated output depends on the output voltage and load condition.
(3) Guaranteed by design.
(4) Please contact factory for SYNC applications.

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Pin Configurations Ordering Information

)2()1(

TOP VIEW

rebmuNtraP

TRTESH9154CSPDE8-OS

SC4519H

egakcaP

1

2

3

4

(SO-8 EDP)

Pin Descriptions

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8

7

6

5

.V7.2si

SYNCBST

COMPIN

FBSW

ENGND

Notes:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.

(2) Lead free product. This product is WEEE and
RoHS compliant.

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Block Diagram

COMP

COMP

FB

FB

EN

EN

SYNC

SYNC

-

-

EA

EA

OSCILLATOR

OSCILLATOR

1V

1V

REFERENCE

REFERENCE

0.7V

0.7V

SLOPE COMP

SLOPE COMP

FREQUENCY

FREQUENCY

+

+

PWM

PWM

UVLO

UVLO

SLOPE

SLOPE

CLK

CLK

SLOPE

SLOPE

SC4519H

+

+

+

Is

Is

+

+

S

S

Q

Q

R

R

SOFT START

SOFT START

HICCUP

HICCUP

FB

FB

+

ISEN

ISEN

40m

40m

POWER

POWER
TRANSISTOR

TRANSISTOR

Is

Is

OL

OL

IN

IN

BST

BST

SW

SW

GND

GND

Typical Characteristic - OCP Limit

SC4519H OCP Limit vs Duty Cycle

7

6.5

6

5.5

5

4.5

4

Current Limit (A)

3.5

3

2.5

2

0 20406080100

ILIM @-40C

ILIM @25C

ILIM @125C

Duty Cycle (%)

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Application Information

The SC4519H is a current mode buck converter regulator.
SC4519H has an internal fixed-frequency clock. The
SC4519H uses two feedback loops that control the duty
cycle of the internal power switch. The error amplifier
functions like that of the voltage mode converter. The
output of the error amplifier works as a switch current
reference. This technique effectively removes one of the
double poles in the voltage mode system. With this, it is
much simpler to compensate a current mode converter
to have better performance. The current sense amplifier
in the SC4519H monitors the switch current during each
cycle. Overcurrent protection (OCP) is triggered when the
current limit exceeds the upper limit of 3A, detected by a
voltage on COMP greater than about 2V. When an OCP
fault is detected, the switch is turned off and the external
COMP capacitor is discharged at the rate of dv/dt = 3

. Once the COMP voltage has fallen below 250mV,

C

comp

the part enters a normal startup cycle. C

is the total

comp

capacitance value attached to COMP. In the case of
sustained overcurrent or dead-short, the part will
continually cycle through the retry sequence as described
above, at a rate dependent on the value of Ccomp. During
start up, the voltage on COMP rises roughly at the rate of
dv/dt = 120

µA/C

. Therefore, the retry time for a

comp

sustained overcurrent can be approximately calculated
as:

CT

2V

120uA

C

compcompretry

Figure 1 shows the voltage on COMP during a sustained
overcurrent condition.

µA/

V2

•+•=

uA3

SC4519H

Oscillator

Its internal free running oscillator sets the PWM frequency
at 600kHz for the SC4519H without any external
components to program the frequency. An external clock
with a duty cycle from 20% to 80% connected to the
SYNC pin activates synchronous mode. The frequency
of the external clock can be from 700kHz to 1.2MHz.

UVLO

When the EN pin is pulled and held above 1.8V, the voltage
on Pin IN determines the operation of the SC4519H. As

increases during power up, the internal circuit senses

V

IN

VIN and keeps the power transistor off until VIN reaches

4.4V.

Load Current

The peak current I
For a specific application, the allowed load current I
will change if the input voltage drifts away from the original
design as given for continuous current mode:

Where:
fs = switching frequency,
Vo = output voltage and
D = duty ratio, VO/VI
VI = input voltage.

Figure 2 shows the theoretical maximum load current
for the specific cases. In a real application, however, the
allowed maximum load current also depends on the layout
and the air cooling condition. Therefore, the maximum
load current may need to be derated according to the
thermal situation of the application.

in the switch is internally limited.

PEAK

)D1(V

−⋅

O

3I

OMAX

−=
⋅⋅

fL2

s

OMAX

Figure 1. Voltage on COMP for Startup and OCP

Enable

Pulling and holding the EN pin below 0.4V activates the
shut down mode of the SC4519H which reduces the input
supply current to less than 150

µA. During the shut down

mode, the switch is turned off. The SC4519H is turned
on if the EN pin is pulled high.

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Application Information (Cont.)

Maximum Load Current vs Input Voltage

L=10uH

2.900

2.880

2.860

2.840

2.820

2.800

2.780

Iomax (A)

2.760

2.740

2.720

2.700
4681012141618

Vi (V)

Figure 2. Theoretical maximum load current curves

Inductor Selection

The factors for selecting the inductor include its cost,
efficiency, size and EMI. For a typical SC4519H
application, the inductor selection is mainly based on its
value, saturation current and DC resistance. Increasing
the inductor value will decrease the ripple level of the
output voltage while the output transient response will
be degraded. Low value inductors offer small size and
fast transient responses while they allow large ripple
currents, poor efficiencies and require more output
capacitance for low output ripple. The inductor should
be able to handle the peak current without saturating
and its copper resistance in the winding should be as low
as possible to minimize its resistive power loss. A good
trade-off among its size, loss and cost is to set the
inductor ripple current to be within 15% to 30% of the
maximum output current.

The inductor value can be determined according to its
operating point under its continuous mode and the
switching frequency as follows:

)V(VV

−⋅

L

=

OIO

IδfV

⋅⋅⋅

OMAXsI

Where:
fs = switching frequency,

δ = ratio of the peak to peak inductor current to the

output load current and
VO = output voltage.

Vo=2.5V

Vo=3.3V

Vo=5V

SC4519H

The peak to peak inductor current is:

OMAXLRMS

2

LRMS

IδI •=

OMAXpp

PEAK

I

−

+=

RIP ⋅=

WINDING

1

12

pp

2

PEAK

2

δ

II

OMAXPEAK

1II ⋅+⋅=

−

After the required inductor value is selected, the proper
selection of the core material is based on the peak
inductor current and efficiency specifications. The core
must be able to handle the peak inductor current I
without saturation and produce low core loss during the
high frequency operation.

The power loss for the inductor includes its core loss and
copper loss. If possible, the winding resistance should
be minimized to reduce inductor’s copper loss. The core
must be able to handle the peak inductor current I
without saturation and produce low core loss during the
high frequency operation. The core loss can be found in
the manufacturer’s datasheet. The inductor’s copper loss
can be estimated as follows:

COPPER

Where:
I

is the RMS current in the inductor. This current can

LRMS

be calculated as follows:

Output Capacitor Selection

Basically there are two major factors to consider in
selecting the type and quantity of the output capacitors.
The first one is the required ESR (Equivalent Series
Resistance) which should be low enough to reduce the
output voltage deviation during load changes. The second
one is the required capacitance, which should be high
enough to hold up the output voltage. Before the
SC4519H regulates the inductor current to a new value
during a load transient, the output capacitor delivers all
the additional current needed by the load. The ESR and
ESL of the output capacitor, the loop parasitic inductance
between the output capacitor and the load combined
with inductor ripple current are all major contributors to
the output voltage ripple. Surface mount ceramic
capacitors are recommended.

Input Capacitor Selection

The input capacitor selection is based on its ripple current
level, required capacitance and voltage rating. This

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Application Information (Cont.)

SC4519H

capacitor must be able to provide the ripple current
drawn by the converter. For the continuous conduction
mode, the RMS value of the input capacitor current
I

can be calculated from:

CIN(RMS)

−⋅

)V(VV

CIN

(RMS)

II

OMAX

⋅=

OIO

2

V

I

This current gives the capacitor’s power loss through its
R

CIN(ESR)

as follows:

CIN

2

CIN

(RMS)

RIP •=

CIN(ESR)

The input ripple voltage mainly depends on the input
capacitor’s ESR and its capacitance for a given load, input
voltage and output voltage. Assuming that the input
current of the converter is constant, the required input
capacitance for a given voltage ripple can be calculated
by:

−⋅

IC

⋅=

OMAXIN

D)(1D

⋅−∆⋅

)RIV(fs

CINOMAXI

(ESR)

Where:

∆V

= the given input voltage ripple.

I

Because the input capacitor is exposed to the large surge
current, attention is needed for the input capacitor. If
tantalum capacitors are used at the input side of the
converter, one needs to ensure that the RMS and surge
ratings are not exceeded. For generic tantalum
capacitors, it is suggested to derate their voltage ratings
at a ratio of about two to protect these input capacitors.

Boost Capacitor and its Supply Source Selection

Where:

= the boost current and

I

B

V

= discharge ripple voltage.

D

With fs = 600kHz, VD = 0.5V and IB =0.045A, the required
minimum capacitance for the boost capacitor is:

I

boost

B

f1V

sD

C

0.045

D

max

0.5

1

600k

128nF0.85

=⋅⋅=⋅⋅=

The internal driver of the switch requires a minimum 2.7V
to fully turn on that switch to reduce its conduction loss.
If the output voltage is less than 2.7V, the boost capacitor
can be connected to either the input side or an
independent supply with a decoupling capacitor. But the
Pin BST should not see a voltage higher than its maximum
rating.

Freewheeling Diode Selection

This diode conducts during the switch’s off-time. The diode
should have enough current capability for full load and
short circuit conditions without any thermal concerns.
Its maximum repetitive reverse block voltage has to be
higher than the input voltage of the SC4519H. A low
forward conduction drop is also required to increase the
overall efficiency. The freewheeling diode should be
turned on and off fast with minimum reverse recovery
because the SC4519H is designed for high frequency
applications. SS23 Schottky rectifier is recommended
for certain applications. The average current of the diode,
ID_

can be calculated by:

AVG

omaxAVG-D

)DI(II

−⋅=

The boost capacitor selection is based on its discharge
ripple voltage, worst case conduction time and boost
current. The worst case conduction time T

can be

w

estimated as follows:

1

T ⋅=

W

D

max

f

s

Where:
fs = the switching frequency and
Dmax = maximum duty ratio, 0.85 for the SC4519H.

The required minimum capacitance for the boost
capacitor will be:

I

B

C ⋅=

boost

T

W

V

D

Thermal Considerations

There are three major power dissipation sources for the
SC4519H. The internal switch conduction loss, its
switching loss due to the high frequency switching actions
and the base drive boost circuit loss. These losses can
be estimated as:

2

on

ototal

3

−

10

VI1010.8DRIP

1000

⋅⋅⋅+⋅⋅⋅+⋅⋅=

)(VDI

boostoIo

Where:
IO = load current;
R

= on-equivalent resistance of the switch;

on

V

= input voltage or output based on the boost circuit

BOOST

connection.

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Application Information (Cont.)

The junction temperature of the SC4519H can be
further determined by:

θ

is the thermal resistance from junction to ambient.

JA

Its value is a function of the IC package, the application
layout and the air cooling system.

The freewheeling diode also contributes a significant
portion of the total converter loss. This loss should be
minimized to increase the converter efficiency by using
Schottky diodes with low forward drop (VF).

PθTT ⋅+=

totalJAAJ

D)(1IVP

−⋅⋅=

oFdiode

SC4519H

SC4519H

1

2

IN

5

EN

8

SYNC

3

SW

BST

6

FB

7

GND

COMP

4

C5

C4

R3

Figure 3. Compensation network provides 2 poles and
1 zero.

L1

R1

R2

D2

Vout

C

Loop Compensation Design

The SC4519H has an internal error amplifier and requires
a compensation network to connect between the COMP
pin and GND pin as shown in Figure 3. The compensation
network includes C4, C5 and R3. R1 and R2 are used to
program the output voltage according to:

R

1

)

+•=

O

1(8.0V

R

2

Assuming the power stage ESR (equivalent series
resistance) zero is an order of magnitude higher than
the closed loop bandwidth, which is typically one tenth of
the switching frequency, the power stage control to output
transfer function with the current loop closed (Ridley
model) for the SC4519H will be as follows:

R5

⋅

(s)G

=

VD

L

s

1

+

1

⋅

CR

L

Where:
RL – Load and
C – Output capacitor.

The goal of the compensation design is to shape the loop
to have a high DC gain, high bandwidth, enough phase
margin, and high attenuation for high frequency noises.
Figure 3 gives a typical compensation network which
offers 2 poles and 1 zero to the power stage:

The compensation network gives the following
characteristics:

s

1

+

ω

ω(s)G

⋅=

1COMP

Z

s

(1s

)

+⋅

ω

P2

R

g

2

⋅⋅

m

RR

+

21

Where:

ω

ω

ω

P2

1

=

1

Z

=

CC

+

54

1

=

CR

⋅

43

CC

+

54

CCR

⋅⋅

543

The loop gain will be given by:

s

+

1

L

VDCOMP

104.25(s)G(s)GT(s)

⋅⋅⋅=⋅=

C

⋅

+

s

RR

2124

(1

1

R

R

−

3

ω

Z

s

ω

s

+⋅+

(1)

ω

P2P1

Where:

ω

1

=

p1

CR

⋅

L

One integrator is added at origin to increase the DC gain.

ωZ is used to cancel the power stage pole ω

so that the

P1

loop gain has –20dB/dec rate when it reaches 0dB line.

ω

is placed at half switching frequency to reject high

P2

frequency switching noises. Figure 4 gives the asymptotic
diagrams of the power stage with current loop closed
and its loop gain.

)

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Application Information (Cont.)

SC4519H

Mag

Loop gain T(s)

ω

p1

Power stage

ω

C

ω

P2

ω

ω

Z

Figure 4. Asymptotic diagrams of power stage with
current loop closed and its loop gain.

The design guidelines for the SC4519H applications are
as following:

1. Set the loop gain crossover corner frequency ω
given switching corner frequency ω

= 2πf

C

2. Place an integrator at the origin to increase DC and
low frequency gains.

3. Select ωZ such that it is placed at ω

to obtain a

P1

-20dB/dec rate to go across the 0dB line.

4. Place a high frequency compensator pole

ω

P2 (ωP2

= πf

) to get the maximum attenuation of

s

the switching ripple and high frequency noise with

the adequate phase lag at ω

C.

for

C

C

Layout Guidelines:

In order to achieve optimal electrical and thermal
performance for high frequency converters, special
attention must be paid to the PCB layouts. The goal of
layout optimization is to identify the high di/dt loops and
minimize them. The following guidelines should be used
to ensure proper operation of the converters.

1. A ground plane is suggested to minimize switching
noises and trace losses and maximize heat
transferring.

2. Start the PCB layout by placing the power components
first. Arrange the power circuit to achieve a clean
power flow route. Put all power connections on one
side of the PCB with wide copper filled areas if
possible.

3. The V

bypass capacitor should be placed next to

IN

the VIN and GND pins.

4. The trace connecting the feedback resistors to the
output should be short, direct and far away from any
noise sources such as switching node and switching
components.

5. Minimize the loop including input capacitor, the
SC4519H and freewheeling diode D2. This loop
passes high di/dt current. Make sure the trace width
is wide enough to reduce copper losses in this loop.

6. Maximize the trace width of the loop connecting the
inductor, freewheeling diode D2 and the output
capacitor.

7. Connect the ground of the feedback divider and the
compensation components directly to the GND pin
of the SC4519H by using a separate ground trace.

8. Connect Pin 4 to a large copper area to remove the
IC heat and increase the power capability of the
SC4519H. A few feedthrough holes are required to
connect this large copper area to a ground plane to
further improve the thermal environment of the
SC4519H. The traces attached to other pins should
be as wide as possible for the same purpose.

11 2007 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Application Information (Cont.)

Design Example: 16V to 5V at 2A

VIN=16V

VIN=16V

C3

C3

10u

10u

4.75k

4.

4.75k

R4

R4

R4

2

2

2

5

5

5

8

8

8

IN

IN

IN

SC4519H

SC4519H

SC4519H

EN

EN

EN

SYNC

SYNC

SYNC

1

1

1

4

4

4

BST

BST

BST

GND

GND

GND

SW

SW

SW

FB

FB

FB

COMP

COMP

COMP

3

3

3

6

6

6

7

7

7

C5

C5

180p

180p

C1

C1

C1

0.22u

0.22u

0.22u

R3

R3

R3

3.4k

3.4k

3.4k

C4

C4

C4

3.3n

3.3n

3.3n

SC4519H

D3

D3

D3

L1

L1

D2

D2

D2

L1

8.2uH

8.2uH

8.2uH

R1

R1

R1

52.3k

R2

R2

R2

R2

R2

R2

10k

10k

10k

k

k

k

C2

C2

C2
10u

10u

10u

Vo=5V

Vo=5V

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111CR7X,5080,V52,Fu22.0yahsiV

22 3C,2CV52,R5X,0121,u01cinosanaP

314CV52,R7X,5080,n3.3yahsiV

415CFp081

511D323-DOS,SW8414N1

612D33SS33SS:N/PdlihcriaF

711LHu2.82R8-521RD:N/PREPOOC

811RK3.25

912Rk01

0113Rk4.3

1114Rk57.4

2111UH9154CShcetmeS

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12 2007 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Application Information (Cont.)

SC4519H

(COMPONENT - TOP)

(PCB - TOP) (PCB - BOTTOM)

(COMPONENT - BOTTOM)

SC4518

88

13 2007 Semtech Corp. www.semtech.com

POWER MANAGEMENT

Outline Drawing - SOIC-8L EDP

SC4519H

A

N

D

e

E/22X

E1

E

12

ccc C

2X N/2 TIPS

e/2

B

D

SEATING
PLANE

aaa C

C

bxN

bbb C A-B D

A2

A

A1

F

EXPOSED PAD

H

SEE DETAIL

SIDE VIEW

NOTES:

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).

1.

DATUMS AND TO BE DETERMINED AT DATUM PLANE

2. -A-

DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS

3.
OR GATE BURRS.

REFERENCE JEDEC STD MS-012, VARIATION BA.

4.

-B-

DIMENSIONS

INCHES

DIM

NOM

MIN MAX MAXNOM

-

.053

A

.000

A1

.049

A2

.012

b
c

.007
.189

D

.150

E1
E
e

.116 .130

F

.085

H

.010 .020 0.50

h

.016

L
L1
N
01

aaa
bbb

ccc

0°

-

-

-

­.193
.154

.236 BSC
.050 BSC

.120
.095

­.028

(.041)

8

­.004
.010
.008

.069
.005
.065
.020 0.31
.010
.197
.157

.099

.041

8° 0°

h

H

GAGE

PLANE

0.25

DETAIL

A

-H-

MILLIMETERS

MIN

-

1.35

-

0.00

-

1.25

-

0.17

4.90

4.80

3.90

3.80

6.00 BSC

1.27 BSC

2.95

3.05

2.15

2.41

-

0.25

0.40

0.72-1.04

(1.05)

8

-

0.10

0.25

0.20

h

L

(L1)

A

1.75

0.13

1.65

0.51

0.25

5.00

4.00

3.30

2.51

01

8°

c

Land Pattern - SOIC-8L EDP

THERMAL VIA
Ø 0.36mm

Contact Information

Phone: [phone] FAX [phone]

E

D

SOLDER MASK

DIMENSIONS

(.205)

(C)

F

P

NOTES:

1.

THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.

REFERENCE IPC-SM-782A, RLP NO. 300A.2.

3. THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.

Z

G

Y

X

C
D

.134
.201

E

.101

F

.118

G

.050

P

.024

X

.087

Y

.291

Z

Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012

MILLIMETERSINCHESDIM

(5.20)

3.40

5.10

2.56

3.00

1.27

0.60

2.20

7.40

14 2007 Semtech Corp. www.semtech.com