Page 1
INTEGRATED CIRCUITS
SC26C562
CMOS dual universal serial
communications controller (CDUSCC)
Product specification
Supersedes data of 1995 May 01
IC19 Data Handbook
1998 Sep 04
Page 2
Philips Semiconductors Product specification
CMOS dual universal serial communications controller
(CDUSCC)
DESCRIPTION
The Philips Semiconductors SC26C562 Dual Universal Serial
Communications Controller (CDUSCC) is a single-chip CMOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SC26C562 interfaces to synchronous
bus MPUs and is capable of program-polled, interrupt driven,
block-move or DMA data transfers.
The SC26C562 (CDUSCC) is (PIN) hardware and (REGISTER)
software compatible with the existing SCN26562 (DUSCC).
CDUSCC will automatically configure to the NMOS DUSCC register
map (default mode) on power up.
The operating mode and data format of each channel can be
programmed independently. Each channel consists of a receiver, a
transmitter, a 16-bit multifunction counter/timer, a digital
phase-locked loop (DPLL), a parity/CRC generator and checker, and
associated control circuits. The two channels share a common bit
rate generator (BRG), operating directly from a crystal or an external
clock, which provides sixteen common bit rates simultaneously. The
operating rate for the receiver and transmitter of each channel can
be independently selected from the BRG, the DPLL, the
counter/timer, or from an external 1X or 16X clock, making the
CDUSCC well-suited for dual-speed channel applications. Data
rates up to 10Mbits per second are supported.
The transmitter and receiver each contain a sixteen-deep FIFO with
appended transmitter command and receiver status bits and a shift
register. This permits reading and writing of up to sixteen characters
at a time, minimizing the potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA overhead. In addition, a
flow control capability is provided to disable a remote transmitter
when the FIFO of the local receiving device is full.
Two modem control inputs (DCD and CTS) and three modem
control outputs (RTS and two general purpose) are provided.
Because the modem control inputs and outputs are general purpose
in nature, they can be optionally programmed for other functions.
The SC26C562 CDUSCC is optimized to interface with processors
using a synchronous bus interface, such as the 8086, and iAPX86
family. For systems using an asynchronous bus, such as the 68000
and 68010, refer to the SC68C562 documentation.
Refer to the CMOS Dual Universal Serial Communication Controller
(CDUSCC) User’s Manual for a complete operational description.
FEA TURES
General Features
•Dual full-duplex synchronous/ asynchronous receiver and
transmitter
•Multi-protocol operation
– BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
etc.
– COP: Single SYNC, dual SYNC, BiSYNC, DDCMP
– ASYNC: 5-8 bits plus optional parity
•Sixteen character receive and transmit FIFOs with interrupt
threshold control
•FIFO’ed status bits
•Watchdog timer
•0 to 10 Mbit/sec data rate
•Programmable bit rate for each receiver and transmitter selectable
from:
– 19 fixed rates: 50 to 64K baud
– One user-defined rate derived from programmable
counter/timer
– External 1X or 16X clock
– Digital phase-locked loop
•Parity and FCS (frame check sequence LRC or CRC) generation
and checking
•Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
•Programmable channel mode: full- or half-duplex, auto-echo, or
local loopback
•Programmable data transfer mode: polled, interrupt, DMA, wait
•DMA interface
– Compatible with Synchronous and Asynchronous bus DMA
controllers
– Half- or full-duplex operation
– Single or dual address data transfers
– Automatic frame termination on counter/ timer terminal count or
DMA DONE (EOPN)
•Transmit path clear status
•High speed data bus interface: 160ns bus cycle
•DPLL operation up to 312.5kHz with internal clock
•Interrupt capabilities
– Vector output (fixed or modified by status)
– Individual interrupt enable bits
– Programmable internal priorities
– Maskable interrupt conditions
– 80XX/X compatible
•Multi-function programmable 16-bit counter/timer
– Bit rate generator
– Event counter
– Count received or transmitted characters
– Delay generator
– Automatic bit length measurement
•Modem controls
– RTS, CTS, DCD, and up to four general purpose I/O pins per
channel
– CTS and DCD programmable auto-enables for Tx and Rx
– Programmable interrupt on change of CTS or DCD
•On-chip oscillator for crystal
•TTL compatible
•Single +5V power supply
Asynchronous Mode Features
•Character length: 5 to 8 bits
SC26C562
1998 Sep 04 853-1663 19973
2
Page 3
Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
CMOS dual universal serial communications controller
(CDUSCC)
•Odd or even parity, no parity, or force parity
•Up to two stop bits programmable in 1/16-bit increments
•1X or 16X Rx and Tx clock factors
•Parity, overrun and framing error detection
•False start bit detection
•Break generation with handshake for counting break characters
•Detection of start and end of received break
•Character compare with optional interrupt on match
•Transmit and receive up to 10Mbps at 1x or 1Mbps at 16x data
rates
Bit-Oriented Protocol
•Character length: 5 to 8 bits
•Detection and transmission of residual character: 0–7 bits
•Automatic switch to programmed character length for I field
•Zero insertion and deletion
•Optional opening PAD transmission
•Detection and generation of FLAG, ABORT, and IDLE bit patterns
•Transmit 7 or 8 bit ABORT
•Detection and generation of shared (single) FLAG between
frames
•Detection of overlapping (shared zero) FLAGs
•Idle in MARK or FLAGs
•Secondary address recognition including group and global
address
•Single- or dual-octet secondary address
•Extended address and control fields
•Short frame rejection for receiver
•Detection and notification of received end of message
•CRC generation and checking
•SDLC loop mode capability
Character-Oriented Protocols
•Character length: 5 to 8 bits
•Odd or even parity, no parity, or force parity
•LRC or CRC generation and checking
•Optional opening PAD transmission
•One or two SYN characters
•External sync capability
•SYN detection and optional stripping
•SYN or MARK line-fill or underrun
•Idle in MARK or SYNs
•Parity, FCS, overrun and underrun error detection
•Optional SYNC exclusion from FCS
•BISYNC features
– EBCDIC or ASCII header, text and control messages
– SYN, DLE stripping
– EOM (end of message) detection and transmission
– Auto transparency mode switching
– Auto hunt after receipt of EOM sequence (with closing PAD
check after EOT or NAK)
– Control character sequence detection for both transparent and
normal text
– Parity generation for data and LRC characters
SC26C562
ORDERING INFORMATION
COMMERCIAL INDUSTRIAL
DESCRIPTION
48-Pin Plastic Dual In-Line Package (DIP) SC26C562C1N Not available SOT240-1
52-Pin Plastic Leaded Chip Carrier (PLCC) Package SC26C562C1A SC26C562A8A SOT238-3
ABSOLUTE MAXIMUM RATINGS
T
A
T
STG
V
CC
V
S
1998 Sep 04
Operating ambient temperature
Storage temperature -65 to +150 -65 to +150 °C
Voltage from VCC to GND
Voltage from any pin to ground
1
2
3
3
Serial Data Rate =
10Mbps Maximum
RATING
COMMERCIAL INDUSTRIAL
0 to +70 -40 to +85 °C
–0.5 to +7.0 –0.5 to +7.0 V
–0.5 to VCC +0.5 –0.5 to VCC +0.5 V
3
Serial Data Rate =
8Mbps Maximum
DWG #
Page 4
Philips Semiconductors Product specification
CMOS dual universal serial communications controller
(CDUSCC)
PIN CONFIGURATIONS
IACKN
RTxDAKBN/
GPI1BN
IRQN
RDYN
RTSBN/
SYNOUTBN
TRxCB
RTxCB
DCDBN/
SYNIBN
RxDB
TxDB
TxDAKBN/
GPI2BN
RTxDRQBN/
GPO1BN
TxDRQBN/
GPO2BN/RTSBN
CTSBN/LCBN
RDN
RESETN
GND
1
2
A3
3
A2
4
A1
5
6
7
8
9
10
11
12
13
14
15
16
17
18
D7
19
D6
20
D5
21
D4
22
23
24
N PACKAGE
DIP
48
V
CC
47
A4
46
A5
45
A6
RTxDAKAN/
44
GPI1AN
43
X1/CLK
42
X2
RTSAN/
41
SYNOUTAN
40
TRxCA
39
RTxCA
DCDAN/
38
SYNIAN
37
RxDA
36
TxDA
TxDAKAN/
35
GPI2AN
RTxDRQAN/
34
GPO1AN
TxDRQAN/
33
GPO2AN/RTSAN
32
CTSAN/LCAN
31
D0
30
D1
29
D2
28
D3
27
EOPN
26
WRN
25
CEN
INDEX
CORNER
7
8
20
21
PIN FUNCTION PIN FUNCTION
1 IACKN 27 CEN
2 A3 28 WRN
3 A2 29 EOPN
4A1 30D3
5 RTxDAKBN/ 31 D2
GPI1BN 32 D1
6 IRQN 33 D0
7NC 34NC
8 RDYN 35 CTSAN/LCAN
9 RTSBN/ 36 TxDRQAN/
SYNOUTBN GPO2AN/RTSAN
10 TRxCB 37 RTxDRQAN/
11 RTxCB GPO1AN
12 DCDBN/ 38 TxDAKAN/
SYNIBN GPI2AN
13 NC 39 TxDA
14 RxDB 40 RxDA
15 TxDB 41 NC
16 TxDAKBN/ 42 DCDAN/
GPI2BN SYNIAN
17 RTxDRQBN/ 43 RTxCA
GPO1BN 44 TRxCA
18 TxDRQBN/ 45 RTSAN/
GPO2BN/RTSBN SYNOUTAN
19 CTSBN/LCBN 46 X2
20 D7 47 X1/CLK
21 D6 48 RTxDAKAN/
22 D5 GPI1AN
23 D4 49 A6
24 RDN 50 A5
25 RESETN 51 A4
26 GND 52 V
A PACKAGE
1
PLCC
TOP VIEW
SC26C562
47
46
34
33
CC
SD00203
1998 Sep 04
Figure 1. Pin Configurations
4
Page 5
Philips Semiconductors Product specification
CMOS dual universal serial communications controller
(CDUSCC)
BLOCK DIAGRAM
D0–D7
RDYN
WRN
RDN
A1–A6
CEN
RESETN
RTxDRQAN/GPO1AN
RTxDRQBN/GPO1BN
TxDRQAN/GPO2AN
TxDRQBN/GPO2BN
RTxDAKAN/GPI1AN
RTxDAKBN/GPI1BN
TxDAKAN/GPI2AN
TxDAKBN/GPI2BN
EOPN
TRxCA/B
RTxCA/B
CTSAN/LCAN
CTSBN/LCBN
DCDBN/SYNIBN
DCDAN/SYNIAN
RTSBN/SYNOUTBN
RTSAN/SYNOUTAN
IRQN
IACKN
X1/CLK
X2
BUS
BUFFER
A7 CONTROL
LOGIC
MPU
INTERFACE
DMA
INTERFACE
SPECIAL
FUNCTION
PINS
INTERRUPT
CONTROL
ICRA/B
IERA/B
IVRM
IER1 A/B
IER2 A/B
IER3 A/B
OSCILLATOR
A7
CDUSCC
LOGIC
INTERFACE/
OPERATION
CONTROL
ADDRESS
DECODE
R/W
DECODE
DMA
CONTROL
CCRA/B
PCRA/B
RSRA/B
TRSRA/B
ICTSRA/B
GSR
CMR1A/B
CMR2A/B
OMRA/B
TRCR A/B
FTLR A/B
TRMR A/B
CID
CONTROL
INTERNAL BUS
CHANNEL
MODE AND
TIMING A/B
DPLL CLK
MUX A/B
DPLLA/B
BRG
COUNTER
TIMER A/B
C/T CLK
MUX A/B
CTCRA/B
CTPRHA/B
CTPRLA/B
CTHA/B
CTLA/B
TRANSMIT
A/B
TRANS CLK
MUX
TPRA/B
TTRA/B
TX SHIFT
REG
TRANSMIT
16 DEEP
FIFO
TELR
A/B
CRC
GENERATOR
SPEC CHAR
GEN LOGIC
RECEIVER
A/B
RCVR CLK
MUX
RPRA/B
RTRA/B
S1RA/B
S2RA/B
RCVR
SHIFT REG
RECEIVER
16 DEEP
FIFO
RFLR
A/B
CRC
ACCUM
BISYNC
COMPARE
LOGIC
SC26C562
TxD A/B
RxD A/B
1998 Sep 04
SD00239
Figure 2. Block Diagram
5
Page 6
Philips Semiconductors Product specification
MNEMONIC
TYPE
NAME AND FUNCTION
CMOS dual universal serial communications controller
(CDUSCC)
PIN DESCRIPTION
PIN NO.
DIP PLCC
A1–A6 4-2,
47-45
D0–D7 31-28,
21-18
RDN 22 24 I Read Strobe: Active-low input. When active and CSN is also active, causes the content
WRN 26 28 I Write Strobe: Active-low input. When active and CSN is also active, the content of the
CSN 25 27 I Chip Select: Active-low input. When active, data transfers between the CPU and the
RDYN 7 8 O Ready: Active-low, open drain. Used to synchronize data transfers between the CPU and
IRQN 6 6 O Interrupt Request: Active-low, open-drain. This output is asserted upon occurrence of
IACKN 1 1 I Interrupt Acknowledge: Active-low. When IACKN is asserted, the CDUSCC responds
X1/CLK 43 47 I Crystal or External Clock: When using the crystal oscillator, the crystal is connected
X2 42 46 O Crystal 2: Connection for other side of crystal. When a crystal is used, a capacitor must
RESETN 23 25 I Master Reset: Active-low. A low on this pin resets the transmitters and receivers and
RxDA, RxDB 37, 12 40, 14 I Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If
TxDA, TxDB 36, 13 39, 15 O Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted
RTxCA, RTxCB 39, 10 43, 11 I/O Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to
TRxCA, TRxCB 40, 9 44, 10 I/O Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver,
4-2,
51-49
33-30,
23-20
I Address Lines: Active-high. Address inputs which specify which of the internal registers
is accessed for read/write operation.
I/O Bidirectional Data Bus: Active-high, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All
data, command and status transfers between the CPU and the CDUSCC take place over
this bus. The data bus is enabled when CSN and RDN, or CSN and WRRN are low during
interrupt acknowledge cycles and single address DMA acknowledge cycles.
of the addressed register to be present on the data bus. RDN is ignored unless CSN is
active.
data bus is loaded into the addressed register. The transfer occurs on the rising edge of
WRN. WRN is ignored unless CEN is active.
CDUSCC are enabled on D0–D7 as controlled by RDN or WRN and A1–A6 inputs. When
CSN is high, the data lines are placed in the 3-State condition (except during interrupt
acknowledge cycles and single address DMA transfers).
the CDUSCC. It is valid only during read and write cycles where the CDUSCC is
configured in ‘wait on Rx’, ‘wait on Tx’ or ‘wait on Tx or Rx’ modes, otherwise it is always
inactive. RDYN becomes active on the leading edge of RDN and WRN if the requested
operation cannot be performed (viz, no data in RxFIFO in the case of a read or no room in
the TxFIFO in the case of a write).
any enabled interrupting condition. The CPU can read the general status register to
determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle
to cause the CDUSCC to output an interrupt vector on the data bus.
by either forcing the bus into high-impedance, placing a vector number, call instruction or
zero on the data bus. The vector number can be modified or unmodified by the status. If
no interrupt is pending, IACKN is ignored and the data bus placed in high-impedance.
between pins X1 and X2. If a crystal is not used, an external clock is supplied at this input.
This clock is used to drive the internal bit rate generator, as an optional input to the
counter/timer or DPLL, and to provide other required clocking signals. When a crystal is
used, a capacitor must be connected from this pin to ground.
be connected from this pin to ground. If an external clock is used on X1, this pin should be
left floating.
resets the registers shown in Table 1 of the CDUSCC Users’ Guide. Reset is
asynchronous, i.e., no clock is required.
external receiver clock is specified for the channel, the input is sampled on the rising edge
of the clock.
first. This output is in the marking (high) condition when the transmitter is disabled or when
the channel is operating in local loopback mode. If external transmitter clock is specified
for the channel, the data is shifted on the falling edge of the clock.
supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply
the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock
(1X).
transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X),
the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system
clock (X1 ÷ 2).
SC26C562
1998 Sep 04
6
Page 7
Philips Semiconductors Product specification
MNEMONIC
TYPE
NAME AND FUNCTION
CMOS dual universal serial communications controller
(CDUSCC)
PIN DESCRIPTION (Continued)
PIN NO.
DIP PLCC
Channel A (B) Clear-to-Send Input or Loop Control Output: Active-low. The signal
can be programmed to act as an enable for the transmitter when not in loop mode. The
CTSA/BN,
LCA/BN
DCDA/BN,
SYNIA/BN
RTxDRQA/BN,
GPO1A/BN
TxDRQA/BN,
GPO2A/BN,
RTSA/BN
RTxDAKA/BN,
GPI1A/BN
TxDAKA/BN,
GPI2A/BN
EOPN 27 29 I/O
RTSA/BN,
SYNOUTA/BN
V
CC
GND 24
32, 17 35, 19 I/O
38, 11 42, 12 I
34, 15 37, 17 O
33, 16 36, 18 O
44, 5 48, 5 I
35, 14 38, 16 I
41, 8 45, 9 O
48 34, 52 I +5V Power Input
26, 13,
41, 7
CDUSCC detects logic level transitions on this input and can be programmed to generate
an interrupt when a transition occurs. When operating in the BOP loop mode, this pin becomes a loop control output which is asserted and negated by CDUSCC commands. This
output provides the means of controlling external loop interface hardware to go on-line and
off-line without disturbing operation of the loop.
Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-low input, it acts as an enable for the receiver or can be
used as a general purpose input. For the DCD function, the CDUSCC detects logic level
transitions on this pin and can be programmed to generate an interrupt when a transition
occurs. As an active-low external sync input, it is used in COP mode to obtain character
synchronization for the receiver without receipt of a SYN character. This mode can be
used in disc or tape controller applications or for the optional byte timing lead in X.21.
Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose
Output: Active-low. For half-duplex DMA operation, this output indicates to the DMA
controller that one or more characters are available in the receiver FIFO (when the
receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled).
For full-duplex DMA operation, this output indicates to the DMA controller that data is
available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that
can be asserted and negated under program control.
Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send: Active-low. For full-duplex DMA operation, this output indicates to the
DMA controller that the transmit FIFO is not full and can accept more data. When not in
full-duplex DMA mode, this pin can be programmed as a general purpose or a
Request-to-Send output, which can be asserted and negated under program control.
Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input:
Active-low. For half-duplex single address operation, this input indicates to the CDUSCC
that the DMA controller has acquired the bus and that the requested bus cycle (read
receiver FIFO when the receiver is enabled or load transmitter FIFO when the transmitter
is enabled) is beginning. For full-duplex single address DMA operation, this input indicates
to the CDUSCC that the DMA controller has acquired the bus and that the requested read
receiver FIFO bus cycle is beginning. Because the state of this input can be read under
program control, it can be used as a general purpose input when not in single address
DMA mode.
Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-low.
When the channel is programmed for full-duplex single address DMA operation, this input
is asserted to indicate to the CDUSCC that the DMA controller has acquired the bus and
that the requested load transmitter FIFO bus cycle is beginning. Because the state of this
input can be read under program control, it can be used as a general purpose input when
not in full-duplex single address DMA mode.
Done (EOP): Active-low, open-drain. EOPN can be used and is active in both DMA and
non-DMA modes. As an input, EOPN indicates the last DMA transfer cycle to the TxFIFO.
As an output, EOPN indicates either the last DMA transfer from the RxFIFO or that the
transmitted character count has reached terminal count.
Channel A (B) Sync Detect or Request-to-Send: Active-low. If programmed as a sync
output, it is asserted one bit time after the specified sync character (COP or BISYNC
modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send
modem control signal, it functions as described previously for the TxDRQN/RTSN pin.
I Signal and Power Ground Input
SC26C562
1998 Sep 04
7
Page 8
Philips Semiconductors Product specification
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
–150
I
IL
–15
CMOS dual universal serial communications controller
(CDUSCC)
DC ELECTRICAL CHARACTERISTICS
4,5
T
= 0°C to +70°C, VCC = 5.0V +10%
A
Input low voltage:
V
IL
All except X1/CLK 0.8 V
X1/CLK 0.8 V
V
IH
Input high voltage except X1/CLK
0 to 70C
–40 to +85C
X1/CLK 0.8 x V
V
OL
Output low voltage:
All except IRQN
7
IOL=5.3mA(Comm), 4.8mA(Ind) V
IRQN IOL=8.8mA(Comm), 7.8mA(Ind) 0.5 V
V
OH
Output high voltage: 0.5
(Except open drain outputs) IOH = –400µA VCC–0.5 V
I
ILX1
I
IHX1
I
SCX2
X1/CLK input low current
X1/CLK input high current
X2 short circuit current
10
10
VIN = 0, X2 = open
VIN = VCC, X2 = GND
X1 = open, VIN = 0
VIN = V
Input low current
RESETN, TxDAKN, RxDAKN VIN = 0
I
I
I
OZH
I
OZL
I
ODL
Input leakage current
Output off current high, 3-State data bus
Output off current low , 3-State data bus
Open drain output low current in off
VIN = 0 to V
–40 to +85C
VIN = V
–40 to +85C
VIN = 0
–40 to +85C
CC,
0 to 70C
CC,
0 to 70C
,
0 to 70C
state: EOPN, RDYN –15 –0.5 µA
IRQN VIN = 0 –1 µA
I
ODH
I
CC
C
C
C
13
IN
OUT
I/O
Open drain output high current in off
state: EOPN, IRQN, RDYN VIN = V
Power supply current
(see Figure 19 for graphs)
Input capacitance
Output capacitance
9
9
Input/output capacitance
9
0 to 70C
–40 to +85C
VCC = GND = 0 10 pF
VCC = GND = 0 15 pF
VCC = GND = 0 20 pF
CC
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.
2. Clock may be stopped (DC) for testing purposes, or when CDUSCC is in non-operational modes.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range.
5. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.2V and 3.0V with a transition time of 20ns maximum. For X1/CLK, this swing is between 0.2V and 4.4V . All time measurements are referenced at input volta ges of
0.2V and 3.0V and output voltages of 0.8V and 2.0V , as appropriate.
6. See Figure 20 for test conditions for outputs.
7. Tests for open drain outputs are intended to guarantee switching of the output transistor. Measurement of this response is referenced from
midpoint of the switching signal to a point 0.2V above the actual output signal level. This point represents noise margin that assures true
switching has occurred.
8. Execution of the valid command (after it is latched) requires 3 rising edges of X1 (see Figure 15).
9. These values were not explicitly tested; they are guaranteed by design and characterization data.
10.X1/CLK and X2 are not tested with a crystal installed.
11.X1/CLK frequency must be at least the faster of the receiver or transmitter serial data rate.
12.Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CSN as the ‘strobing’ input. CSN
and RDN (also CSN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
= 0 to VCC, Rx and Tx clocks at 10MHz, X1 clock at 10MHz.
13.V
O
4,5
LIMITS
Min Typ Max
2.0 V
2.3 V
CC
–
CC
–
–1
–10
–1
–10
–1 1 µA
SC26C562
25
V
CC
V
0.0 µA
150 µA
–15
+15
mA
mA
–0.5 µA
+1
+10
+1
+10
µA
µA
µA
80
95
mA
1998 Sep 04
8
Page 9
Philips Semiconductors Product specification
CMOS dual universal serial communications controller
(CDUSCC)
t
RDLDDV
t
RDLDLZ
t
RDLRYL
4,5,6,7
T
= 0°C to +70°C, –40 to +85C, VCC = 5V ±10%
A
t
RELREH
SD00205
Figure 3. Reset Timing
LIMITS
Min Max Min Max
t
RDHCEH
t
RDLADI
t
RDLRDH
t
RYZDDV
A
Figure 4. Read Cycle
12
t
RDHDDF
t
RDHDDI
t
RDHRDL
t
CEHCEL
AC ELECTRICAL CHARACTERISTICS
RESETN
SYMBOL PARAMETER INDUSTRIAL SC26C562 COMMERCIAL SC26C562 UNIT
t
RELREH
RESETN low to RESETN high 200 200 ns
A6–A1
t
ADVRDL
CSN (CEN)
t
CELRDL
RDN
D0–D7
RDYN
NOTE:
Wait on Rx. Receiver FIFO empty.
A
SC26C562
SD00240
SYMBOL PARAMETER
t
ADVRDL
t
CELRDL
t
RDLADI
t
RDLRYL
t
RDLDDV
t
RDLRDH
t
RYZDDV
t
RDHCEH
t
CEHCEL
t
RDHDDI
t
RDHRDL
t
RDHDDF
t
RDLDLZ
Address valid to RDN low 10 5 ns
CEN low to RDN low 10 0 ns
RDN low to address invalid 60 50 ns
RDN low to RDYN low 160 150 ns
RDN low to read data valid 150 130 ns
RDN low to RDN high 150 130 ns
RDYN high impedance to read data valid
RDN high to CEN high 10 0 ns
CEN high to CEN low 50 30 ns
RDN high to read data invalid 5 5 ns
RDN high to RDN low 50 30 ns
RDN high to data bus floating 50 40 ns
RDN low to data bus low impedance
1998 Sep 04
LIMITS
INDUSTRIAL SC26C562 COMMERCIAL SC26C562
UNIT
Min Max Min Max
9
9
5 10 ns
90 90 ns
9
Page 10
Philips Semiconductors Product specification
CMOS dual universal serial communications controller
(CDUSCC)
AC ELECTRICAL CHARACTERISTICS (Continued)
A6–A1
t
CSN (CEN)
WRN
D0–D7
RDYN
NOTE:
A
Wait on Tx. Transmitter FIFO full.
t
CELWRL
ADVWRL
t
WRLRYL
t
WRLWRH
A
Figure 5. Write Cycle
t
WRLADI
t
WDVWRH
t
WRHCEH
12
t
RYHZWRH
t
WRHWDI
t
WRHWRL
t
CEHCEL
SC26C562
SD00241
SYMBOL PARAMETER
t
ADVWRL
t
CELWRL
t
WRLRYL
t
WRHCEH
t
WRLWRH
t
WDVWRH
t
CEHCEL
t
WRLADI
t
WRHWRL
t
WRHWDI
t
RYHZWRH
Address valid to WRN low 10 5 ns
CSN low to WRN low 10 0 ns
WRN low to RDYN low ns
WRN high to CSN high 10 0 ns
WRN low to WRN high 110 100 ns
Write data valid to WRN high 65
CEN high to CEN low 50
WRN low to address invalid 60 50 ns
WRN high to WRN low 50 30 ns
WRN high to write data invalid 10 5 ns
RDYN hi impedance to WRN high
LIMITS
INDUSTRIAL SC26C562 COMMERCIAL SC26C562
UNIT
Min Max Min Max
160
9
10 0 ns
30
150
60
ns
ns
1998 Sep 04
10
Page 11
Philips Semiconductors Product specification
CMOS dual universal serial communications controller
(CDUSCC)
AC ELECTRICAL CHARACTERISTICS (Continued)
IRQN
IACKN
t
IALDDV
D7–D0
NOTES:
A
ICR[5:4] = 01 or 10 (mode 1 or mode 2)
Call instruction (mode 2)
B
ICR[5:4] = 11 (mode 3)
C
INTERRUPT REQUEST LOCKED
VECTOR SETTLING
B
t
IAHDDI
Figure 6. Interrupt Acknowledge Cycle
VECTOR
LOCKED
C
t
IAHDDF
SC26C562
A
A
A
C
SERVICE
ROUTINE
Cleared
through
software
SD00208
SYMBOL PARAMETER
t
IALDDV
t
IAHDDF
t
IAHDDI
t
IALDLZ
t
IAHIAL
IACKN low to data bus valid ns
IACKN high to data bus floating 140 130 ns
IACKN high to data bus invalid 5 60 5 60 ns
IACKN low to data bus low impedance
IACKN high to low 40 30 ns
CEN
WRN
GPO1_N
AND/OR
GPO2_N
SYMBOL PARAMETER
t
WRHGOV
WRN high to GPO output data valid 100 100 ns
LIMITS
INDUSTRIAL SC26C562 COMMERCIAL SC26C562
Min Max Min Max
9
OLD DATA NEW DATA
5 10 ns
t
WRHGOV
Figure 7. Output Port Timing
LIMITS
INDUSTRIAL SC26C562 COMMERCIAL SC26C562
Min Max Min Max
UNIT
SD00209
UNIT
1998 Sep 04
11
Page 12
Philips Semiconductors Product specification
56
56
14.7456
14.7456
CMOS dual universal serial communications controller
(CDUSCC)
AC ELECTRICAL CHARACTERISTICS (Continued)
CSN (CEN)
RDN
t
GIVRDL
GPI1N
AND/OR
GPI2N
SYMBOL PARAMETER
t
GIVRDL
t
RDLGII
GPI input valid to RDN low 20 20 ns
RDN low to GPI input invalid 40 40 ns
Figure 8. Input Port Timing
t
RDLGII
INDUSTRIAL SC26C562 COMMERCIAL SC26C562
Min Max Min Max
SC26C562
SD00242
LIMITS
UNIT
*Pull-up resistor is not required when using CMOS levels
t
CLHCLL
t
CCHCCL
t
RCHRCL
t
X1/CLK
CTCLK
RxC
TxC
TCHTCL
SYMBOL PARAMETER
t
CLHCLL
t
CLLCLH
t
CCHCCL
t
CCLCCH
t
RCHRCL
t
RCLRCH
t
TCHTCL
t
TCLTCH
f
CL
f
CC
f
RC
f
TC
f
RTC
X1/CLK high to low time 25 25 ns
X1/CLK low to high time 25 25 ns
C/T CLK high to low time 50 45 ns
C/T CLK low to high time 50 45 ns
RxC high to low time 55 50 ns
RxC low to high time 55 50 ns
TxC high to low time 55 50 ns
TxC low to high time 55 50 ns
X1/CLK frequency
11
C/T CLK frequency 0
RxC frequency (16X or 1X @ 50% duty cycle) 0
TxC frequency (16X or 1X @ 50% duty cycle) 0 8 0 10 MHz
Tx/Rx frequency for FM/Manchester encoding 4 5 MHz
TTL
DRIVING
FROM EXTERNAL
SOURCE
V
CC
470Ω
*
X2 OPEN WHEN
IS DRIVEN
X
1
t
CLLCLH
t
CCLCCH
t
RCLRCH
t
TCLTCH
Figure 9. Clock Timing
INDUSTRIAL SC26C562 COMMERCIAL SC26C562
Min Typ Max Min Typ Max
0 16.0 0 16.0 MHz
X
1
X
2
X
C
L1
C
L2
1
C
P1
X
2
C
P2
NOTE: CL1 AND CL2 VALUES DEPEND ON
CRYSTAL
MANUFACTURER’S REQUIREMENTS, AND SHOULD
INCLUDE C
P1
AND C
50-150kΩ
C
P1
C
P2
P2
= 7-12pF
= 12-17pF
÷2
SC26C562
TO
CDUSCC
CIRCUITS
SD00243
LIMITS
UNIT
14.74
8 0
8 0
14.74
10 MHz
10 MHz
1998 Sep 04
12
Page 13
Philips Semiconductors Product specification
t
*
t
CMOS dual universal serial communications controller
(CDUSCC)
AC ELECTRICAL CHARACTERISTICS (Continued)
1 BIT TIME
(1 OR 16 CLOCKS)
TxC
(INPUT)
t
CILTXV
TxD
t
TxC
(1X OUTPUT)
COLTXV
a. Transmit Timing NRZ b. Transmit Timing FM0/1, Manchester Encoding
Figure 10.
SYMBOL PARAMETER
CILTXV
COLTXV
TxC input low (1X) to TxD output 120 120 ns
TxC input low (16X) to TxD output 120 120 ns
TxC output low to TxD output9(NRZ, NRZI) 25 20 ns
FM, MAN 35 30 ns
INDUSTRIAL SC26C562 COMMERCIAL SC26C562
*Characterized with no loads on TxD and TxC outputs. Tester load is approximately 50pF.
TxC
(INPUT)
TxD
TxC
(1X OUTPUT)
Min Max Min Max
t
CILTXV
t
COLTXV
LIMITS
t
CILTXV
t
COLTXV
SC26C562
SD00244
UNIT
SYNOUTN
t
SILRCH
SYNIN
RXC (1X)
INPUT
RxD
t
RXVRCH
a. Receive Timing NRZ b. Receive Timing FM0/1, Manchester Encoding
SYMBOL PARAMETER
t
RXVRCH
RxD data valid to RxC high:
For NRZ data 25 20 ns
For NRZI, Manchester, FM0, FM1 data 30 30 ns
t
RCHRXI
RxC high to RxD data invalid:
For NRZ data 25 20 ns
For NRZI, Manchester, FM0, FM1 data 30 30 ns
t
SILRCH
t
RCHSIH
t
RCHSOL
SYNIN low to RxC high 50 50 ns
RxC high to SYNIN high 20 20 ns
RxC high to SYNOUT low 110 100 ns
t
RCHSIH
t
RCHSOL
t
RCHRXI
RXC
(INPUT)
RxD
t
RXVRCH
t
RCHRXI
t
RXVRCH
Figure 11.
LIMITS
INDUSTRIAL SC26C562 COMMERCIAL SC26C562
Min Max Min Max
t
RCHRXI
SD00245
UNIT
1998 Sep 04
13
Page 14
Philips Semiconductors Product specification
CMOS dual universal serial communications controller
(CDUSCC)
AC ELECTRICAL CHARACTERISTICS (Continued)
EOPN
(OUTPUT)
RTxDRQN OR
TxDRQN
CSN (CEN)
WRN
D7–D0
EOPN
(INPUT)
t
WRLEOL
t
WRLTRH
t
EILWRH
SC26C562
t
WRHEOZ
A
t
WRHEIH
A The TxFIFO is addressed during this write cycle.
SYMBOL PARAMETER
t
WRLTRH
t
WRLEOL
t
WRHEOZ
t
EILWRH
t
WRHEIH
WRN low to Tx DMA REQN high ns
WRN low to EOPN output low 110 100 ns
WRN high to EOPN output high impedance 110 100 ns
EOPN input low to WRN high 35 70 30 60 ns
WRN high to EOPN input high 30 25 ns
Figure 12. Transmit Dual Address DMA T iming
INDUSTRIAL SC26C562 COMMERCIAL SC26C562
Min Max Min Max
SD00246
LIMITS
UNIT
1998 Sep 04
14
Page 15
Philips Semiconductors Product specification
CMOS dual universal serial communications controller
(CDUSCC)
AC ELECTRICAL CHARACTERISTICS (Continued)
RTxDRQN
CEN
RDN
D7–D0
t
EOPN
(OUTPUT)
RDLEOL
t
RDLRRH
SC26C562
A
t
RDHEOZ
A The RxFIFO is addressed during this read cycle.
SYMBOL PARAMETER
t
RDLRRH
t
RDLEOL
t
RDHEOZ
RDN low to Rx DMA REQN high 110 100 ns
RDN low to EOPN output low 110 100 ns
RDN high to EOPN output high impedance 70 60 ns
Figure 13. Receive Dual Address DMA Timing
INDUSTRIAL SC26C562 COMMERCIAL SC26C562
Min Max Min Max
SD00247
LIMITS
UNIT
1998 Sep 04
15
Page 16
Philips Semiconductors Product specification
CMOS dual universal serial communications controller
(CDUSCC)
AC ELECTRICAL CHARACTERISTICS (Continued)
TxRQN
t
TALTRH
TxDAKN
WRN
MEMRN
EOPN
(INPUT)
t
TALTAH
t
TAHTAL
A
B
t
WDVTAH
t
TAHWDI
SC26C562
A
B
t
EILTAH
t
TAHEIH
D7–D0
EOPN
(OUTPUT)
NOTES:
A
Ignored by the CDUSCC since CEN is not asserted, but it can be used externally to qualify TxDAKN.
Memory read signal; not seen by CDUSCC.
B
Figure 14. DMA-Transmit Single Address Mode
SYMBOL PARAMETER
t
TAHTAL
t
TALTAH
t
TALTRH
t
WDVTAH
t
TAHWDI
t
TALEOL
t
TAHEOF
t
EILTAH
t
TAHEIH
Transmit DMA ACKN high to low time 40 30 ns
Transmit DMA ACKN low to high time 110 100 ns
Tx DMA ACKN low to Tx DMA REQN high ns
Write data valid to Tx DMA ACKN high 60 110 40 100 ns
Tx DMA ACKN high to write data invalid 15 10 ns
Tx DMA ACKN low to EOPN output low ns
Tx DMA ACKN high to EOPN output float 100 80 ns
EOPN input low to Tx DMA ACKN high 40 70 30 60 ns
Tx DMA ACKN high to EOPN input high 30 25 ns
INDUSTRIAL SC26C562 COMMERCIAL SC26C562
t
TALEOL
LIMITS
Min Max Min Max
t
TAHEOF
SD00248
UNIT
1998 Sep 04
16
Page 17
Philips Semiconductors Product specification
CMOS dual universal serial communications controller
(CDUSCC)
AC ELECTRICAL CHARACTERISTICS (Continued)
RxDRQN
t
RALRRH
RxDAKN
RDN
MEMWN
EOPN
(OUTPUT)
t
RALDDV
t
RALRAH
A
B
t
RAHRAL
t
RAHDDI
t
RALEOL
SC26C562
A
B
t
RAHEOF
D7–D0
NOTES:
A
Ignored by the CDUSCC bit; it can be used to qualify RxDAKN.
Memory read signal; not seen by CDUSCC.
B
SYMBOL
t
RAHRAL
t
RALRAH
t
RALRRH
t
RALEOL
t
RAHEOF
t
RALDDV
t
RAHDDI
t
RAHDDF
Receive DMA ACKN high to low time 50 30 ns
Receive DMA ACKN low to high time 140 130 ns
Rx DMA ACKN low to Rx DMA REQN high 100 100 ns
Rx DMA ACKN low to EOPN output low 100 100 ns
Rx DMA ACKN high to EOPN output float 70 60 ns
Rx DMA ACKN low to read data valid 140 130 ns
Rx DMA ACKN high to read data invalid 5 5 ns
Rx DMA ACKN high to data bus float 60 60 ns
PARAMETER INDUSTRIAL SC26C562 COMMERCIAL SC26C562 UNIT
t
RAHDDF
Figure 15. DMA-Receive Single Address Mode
Min Max Min Max
SD00249
LIMITS
1998 Sep 04
17
Page 18
Philips Semiconductors Product specification
SYMBOL
PARAMETER
UNIT
CMOS dual universal serial communications controller
(CDUSCC)
AC ELECTRICAL CHARACTERISTICS (Continued)
RDN/WRN
t
RWHIRH
IRQN
Figure 16. Interrupt Timing
INDUSTRIAL SC26C562 COMMERCIAL SC26C562
SYMBOL PARAMETER Min Max Min Max UNIT
RDN/WRN high to IRQN high for:
Read RxFIFO (RxRDY interrupt) 100 90 ns
Write TxFIFO (TxRDY interrupt) 100 90 ns
t
RWHIRH
Write RSR (Rx condition interrupt) 100 90 ns
Write TRSR (Rx/Tx interrupt) 100 90 ns
Write ICTSR (counter/timer interrupt) 100 90 ns
Write TRMSR (Tx Path, Patt. Det.) 100 90 ns
V
M
LIMITS
VOL +0.2V
SD00218
V
OL
SC26C562
X1/CLK
COMMAND
RxC
RxD
LCN
a. Loop Control Output Assertion
RxC
RxD
WRN
VALID
SD00219
Figure 17. Command Timing
12345678
12345678
9
LCN
1998 Sep 04
b. Loop Control Output Negation
SD00220
Figure 18. Relationship Between Received Data and the Loop Control Output
18
Page 19
Philips Semiconductors Product specification
CMOS dual universal serial communications controller
(CDUSCC)
50
40
30
I
CC
20
10
0
4 4.5 5 5.5 6
V
CC
0°C
25°C
70°C
Test Condition: Tx/Rx and X1 Frequency @ 10MHz
IRQN
Figure 19.
2.7K
50pF
50
40
30
I
CC
20
10
0
46810
Tx/Rx Clk and X1 Frequency
Test Condition: VCC = 5V @ 25°C
V
DD
TRxC
RTxC
SC26C562
SD00250
50pF
RDYN
150pF
EOPN
50pF
ALL OTHER
OUTPUTS
150pF
NOTE:
All CL includes 50pF stray capacitance,
i.e., CL = 150pF = 100pF discrete +50pF stray.
Figure 20. Test Conditions for Outputs
820Ω
1K
+5.0V
V
DD
710
+5.0V
SD00251
1998 Sep 04
19
Page 20
Philips Semiconductors Product specification
CMOS dual universal serial communications controller
(CSUSCC)
DIP48: plastic dual in-line package; 48 leads (600 mil) SOT240-1
SC26C562
1998 Sep 04
20
Page 21
Philips Semiconductors Product specification
CMOS dual universal serial communications controller
(CSUSCC)
PLCC52: plastic leaded chip carrier; 52 leads; pedestal SOT238-3
SC26C562
1998 Sep 04
21
Page 22
Philips Semiconductors Product specification
CMOS dual universal serial communications controller
(CSUSCC)
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
SC26C562
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Date of release: 08-98
Document order number: 9397 750 04355
1998 Sep 04
22
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