Datasheet SC16232 Datasheet (SILAN)

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Semiconductors

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SC16232

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HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

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Rev: 2.0 2002.04.26.

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1

RAM MAPPING 32x4 LCD
CONTROLLER FOR I/O µC

DESCRIPTION

The SC16232 is a 128 pattern(32x4), memory mapping, and multi­function LCD driver. The S/W configuration feature of the SC16232
makes it suitable for multiple LCD applications including LCD
modules and display subsystems. Only three or four lines are
required for the interface between the host controller and the
SC16232. The SC16232 contains a power down command to reduce
power consumption.

FEATURES

* Operating voltage: 2.4V ~ 5.2V
* Built-in 256kHz RC oscillator
* External 32.768kHz crystal or 256kHz frequency source input
* Selection of 1/2 or 1/3 bias, and selection of 1/2 or 1/3 or 1/4 duty

LCD applications
* Internal time base frequency sources
* Two selectable buzzer frequencies(2kHz/4kHz)
* Power down command reduces power consumption
* Built-in time base generator and WDT
* Time base or WDT overflow output
* 8 kinds of time base/WDT clock sources
* 32x4 LCD driver
* Built-in 32x4 bit display RAM
* 3-wire serial interface
* Internal LCD driving frequency source

Chip Topography

ORDERING INFORMATION

Device Package

SC16232 COB

* Software configuration feature
* Data mode and command mode

instructions
* R/W address auto increment
* Three data accessing modes
* VLCD pin for adjusting LCD operating

voltage

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SC16232

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HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

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Rev: 2.0 2002.04.26.

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2

PAD ASSIGNMENT

SEG 0

SEG 1

SEG 2

DATA

V

SS

OSCO

V

DD

OSCI

SEG 3

SEG 4

SEG 5

SEG 6

SEG 8

SEG 9

SEG 10

SEG 11

SEG 12

SEG 13

SEG 14

SEG 15

SEG 7

SEG 16

SEG 17

SEG 18

SEG 19

SEG 20

SEG 21

SEG 22

SEG 23

SEG 24

SEG 25

SEG 26

SEG 27

SEG 28

COM2

COM3

SEG31

SEG30

SEG29

COM0

COM1

VLCD

WR

RD

IRQ

BZ

BZ

CS

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

2 3 4

5 6 7 8 9

12

13

14

15

16

17

18

19

32 31 30 29 28 27 26 25 24 23 22 21 20

11

SC16232

10

Note: The IC substrate should be connected to VDDin the PCB layout artwork.

BLOCK DIAGRAM

14
16

9
10
11
12

17
13

19
20

Control

and
Timing
Circuit

Tone Frequency

Generator

Display RAM

LCD Driver/
Bias Circuit

21

24

8

25

16

Watchdog Timer

and

Time BaseGenerator

18

COM0

COM3

SEG0

SEG31

V

LCD

BZ

V

SS

V

DD

DATA

OSCI

OSCO

CS

RD

WR

BZ

IRQ

Notes:CS: Chip selection ; BZ,BZ: Tone outputs ;WR,RD, DATA: Serial interface

COM0 ~ COM3; SEG) ~ SEG31: LCD outputs ;

IRQ

: Time base or WDT overflow output

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3

ABSOLUTE MAXIMUM RATING

Characteristic Symbol Value Unit

Supply Voltage V

DD

-0.3 ~ 5.5 V

Input Voltage V

IN

Vss-0.3~VDD+0.3 V

Storage temperature T

STG

-50 ~ +125

°C

Operating Temperature T

OPR

-25~+75

°C

D.C. ELECTRICAL CHARACTERISTICS

(Tamb=25°C, Unless otherwise specified)

Test conditions

Parameter Symbol

V

DD

Conditions

Min Typ Max Unit

Operating Voltage V

DD

-- -- 2.4 -- 5.2 V

3V -- 150 300

µA

I

DD1

5V

No load/LCD ON
On-chip RC oscillator

-- 300 600

µA

3V -- 60 120

µA

I

DD2

5V

No load/LCD ON

Crystal oscillator

-- 120 240

µA

3V -- 100 200

µA

Operating Current

I

DD3

5V

No load/LCD ON
External clock source

-- 200 400

µA

3V -- 0.1 5

µA

Standby Current I

STB

5V

No load
Power down mode

-- 0.3 10

µA

3V 0 -- 0.6 V

Input Low Voltage V

IL

5V

DATA,

WR,CS,RD

0--1.0V

3V 2.4 -- 3.0 V

Input High Voltage V

IH

5V

DATA,

WR,CS,RD

4.0 -- 5.0 V

3V VOL=0.3V 0.5 1.2 -- mA

DATA, BZ,BZ,

IRQ

I

OL1

5V VOL=0.5V 1.3 2.6 -- mA
3V VOH=2.7V -0.4 -0.8 -- mA

DATA, BZ,

BZ

I

OH1

5V VOH=4.5V -0.9 -1.8 -- mA
3V VOL=0.3V 80 150 --

µA

LCD Common Sink Current I

OL2

5V VOL=0.5V 150 250 --

µA

3V VOH=2.7V -80 -120 --

µA

LCD Common Source Current I

OH2

5V VOH=4.5V -120 -200 --

µA

3V VOL=0.3V 60 120 --

µA

LCD Segment Sink Current I

OL3

5V VOL=0.5V 120 200 --

µA

3V VOH=2.7V -40 -70 --

µA

LCD Segment Source Current I

OH3

5V VOH=4.5V -70 -100 --

µA

3V 40 80 150

kΩ

Pull-high Resistor R

PH

5V

DATA,

WR,CS,RD

30 60 100

kΩ

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SC16232

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4

A.C. ELECTRICAL CHARACTERISTICS

(Tamb=25°C, Unless otherwise specified)

Test conditions

Parameter Symbol

V

DD

Conditions

Min Typ Max Unit

3V -- 256 -- kHz

System Clock f

SYS1

5V

On-chip RC oscillator

-- 256 -- kHz

3V -- 32.768 -- kHz

System Clock f

SYS2

5V

Crystal oscillator

-- 32.768 -- kHz

3V -- 256 -- kHz

System Clock f

SYS3

5V

External clock source

-- 256 -- kHz

-- On-chip RC oscillator -- f

SYS1

/1024 -- Hz

-- Crystal oscillator -- f

SYS2

/128 -- Hz

LCD Clock f

LCD

-- External clock source -- f

SYS3

/1024 -- Hz

LCD Common Period t

COM

-- n: Number of COM -- n/f

LCD

-- S

3V -- -- 150 kHz

Serial Data Clock (WRpin)

f

CLK1

5V

Duty cycle 50%

-- -- 300 kHz

3V -- -- 75 kHz

Serial Data Clock (RDpin)

f

CLK2

5V

Duty cycle 50%

-- -- 150 kHz

Tone Frequency f

TONE

-- On-chip RC oscillator -- 2.0 or 4.0 -- kHz
Serial Interface Reset Pulse Width
(Figure 3)

t

CS

--

CS

-- 250 -- nS

Write mode 3.34 -- --

3V

Read mode 6.67 -- --

µS

Write mode 1.67 -- --

WR,RD

Input Pulse Width

(Figure 1)

t

CLK

5V

Read mode 3.34 -- --

µS

3V

Rise/Fall Time Serial Data Clock
Width (Figure 1)

t

R,tF

5V

-- -- 120 -- nS

3V

SetupTimeforDATAtoWR,

RD

Clock Width (Figure 2)

t

su

5V

-- -- 120 -- nS

3V

Hold Time for DATA toWR,

RD

Clock Width (Figure 2)

t

h

5V

-- -- 120 -- nS

3V

SetupTimeforCStoWR,

RD

Clock Width (Figure 3)

t

su1

5V

-- -- 100 -- nS

3V

Hold Time forCStoWR,RDClock
Width (Figure 3)

t

h1

5V

-- -- 100 -- nS

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SC16232

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5

WR,RD

Clock

90%

50%

10%

t

F

t

R

t

CLK

t

CLK

V

DD

GND

Figure 1

50%

GND

V

DC

GND

V

DC

Clock

WR,RD

DB

VALID DATA

50%

t

h

t

SL

Figure 2

50%

CS

WR,RD

Clock

50%

LAST
Clock

FIRST

Clock

GND

V

DC

GND

V

DC

t

CS

t

h1

t

su1

Figure 3

PAD DESCRIPTION

Pad No. Symbol I/O Description

1

CS

I

Chip selection input with pull-high resistor.
When the

CS

is logic high, the data and command read from or

written to the SC16232 are disabled. The serial interface circuit is also
reset. But if

CS

is at logic low level and is input to theCSpad, the

data and command transmission between the host controller and the
SC16232 are all enabled.

2

RD

I

READ clock input with pull-high resistor.
Data in the RAM of the SC16232 are clocked out on the falling edge of
the

RD

signal. The clocked out data will appear on the DATA line.
The host controller can use the next rising edge to latch the clocked
out data.

(to be continued)

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SC16232

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PAD DESCRIPTION (continued)



Pad No. Symbol I/O Description

3

WR

I

WRITE clock input with pull-high resistor.
Data on the DATA line are latched into the SC16232 on the rising
edge of the

WR

signal.
4 DATA I/O Serial data input/output with pull-high resistor.
5VSS-- Negative power supply, GND.

7OSCII

6OSCOO

The OSCI and OSCO pads are connected to a 32.768kHz crystal in
order to generate a system clock. If the system clock comes from an
external clock source, the external clock source should be connected
to the OSCI pad. But if an on-chip RC oscillator is selected instead,
the OSCI and OSCO pads can be left open,

8V

LCD

I LCD power supply.

9VDD-- Positive power supply.

10

IRQ

O Time base or WDT overflow flag, NMOS open drain output.

11,12

BZ,

BZ

O 2kHz or 4kHz tone frequency output pair.
13 ~16 COM0 ~ COM3 O LCD common outputs.
48 ~17 SEG0 ~ SEG31 O LCD segment outputs.

FUNCTIONAL DESCRIPTION

1. DISPLAY MEMORY – RAM

The static display memory(RAM) is organized into 32x4 bits and stores the displayed data. The contents of the
RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by the READ, WRITE
and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD pattern:

COM3 COM2 COM1 COM0

SEG0

0

SEG1

1

SEG2

2

SEG3

3

SEG31

31

D3 D2 D1 D0

Addr

Data

Address 6 bits
(A5,A4,…,A0)

Data 4 bits (D3,D2,D1,D0)

RAM mapping

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SC16232

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2. SYSTEM OSCILLATOR

The SC16232 system clock is used to generate the time base/watchdog timer(WDT) clock frequency, LCD driving
clock, and tone frequency. The source of the clock may be from an on-chip RC oscillator(256 kHz), a crystal
oscillator(32.768 kHz), or an external 256kHz clock by the S/W setting. The configuration of the system oscillator is
as shown. After the SYS DIS command is executed, the system clock will stop and the LCD bias generator will turn
off. That command is, however, available only for the on-chip RC oscillator or for the crystal oscillator. Once the
system clock stops, the LCD display will become blank, and the time base/WDT lose its function as well.

The LCD OFF command is used to turn the LCD bias generator off. After the LCD bias generator switches off by
issuing the LCD OFF command, using the SYS DIS command reduces power consumption, serving as a system
power down command. But if the external clock source is chosen as the system clock, using the SYS DIS command
can neither turn the oscillator off nor carry out the power down mode. The crystal oscillator option can be applied to
connect an external frequency source of 32kHz to the OSCI pin. In this case, the system fails to enter the power
down mode, similar to the case in the external 256kHz clock source operation. At the initial system power on, The
SC16232 is at the SYS DIS state.

Crystal Oscillator

32768Hz

Extemal Clock Source

256kHz

On-chip RC Oscillator

256kHz

1/8

OSCO

OSCI

System

Clock

System oscillator configuration

3. TIME BASE AND WATCHDOG TIMER (WD T)

The time base generator is comprised by an 8-stage count-up ripple counter and is designed to generate an
accurate time base. The watch dog timer (WDT), on the other hand, is composed of an 8-stage time base generator
along with a 2-stage count-up counter, and is designed to break the host controller or other subsystems from
abnormal states such as unknown or unwanted jump, execution errors, etc. The WDT time-out will result in the
setting of an internal WDT time-out flag. The outputs of the time base generator and of the WDT time-out flag can be
connected to the

IRQ

output by a command option. There are totally eight frequency sources available for the time

base generator and the WDT clock. The frequency is calculated by the following equation.

f

WDT=

n

2

32kHz

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Where the value of n ranges from 0 to 7 by command options. The 32kHz in the above equation indicates that the
source of the system frequency is derived from a crystal oscillator of 32.768kHz, an on-chip oscillator(256kHz), or an
external frequency of 256kHz.

If an on-chip oscillator(256kHz) or an external 256kHz frequency is chosen as the source of the system frequency,
the frequency source is by default prescaled to 32kHz by a 3-stage prescaler. Employing both the time base
generator and the WDT related commands, one should be careful since the time base generator and WDT share the
same 8-stage counter. For example, invoking the WDT DIS command disables the time base generator whereas
executing the WDT EN command not only enables the time base generator but activates the WDT time-out flag
output (connect the WDT time-out flag to the

IRQ

pin). After the TIMER EN command is transferred, the WDT is

disconnected from the

IRQ

pin, and the output of the time base generator is connected to the

IRQ

pin. The WDT
can be cleared by executing the CLR WDT command, and the contents of the time base generator is cleared by
executing the CLR WDT or CLR TIMER command. The CLR WDT or the CLR TIMER command should be executed
prior to the WDT EN or the TIMER EN command respectively. Before executing the

IRQ

EN command the CLR
WDT or CLR TIMER command should be executed first. The CLR TIMER command has to be executed before
switching from the WDT mode to the time base mode. Once the WDT time-out occurs, the

IRQ

pin will stay at a

logic low level until the CLR WDT or the

IRQ

DIS command is issued. After the

IRQ

output is disable the

IRQ

pin

will remain at the floating state. The

IRQ

output can be enabled or disabled by executing the

IRQ

EN or the

IRQ

DIS command, respectively. The

IRQ

EN makes the output of the time base generator or of the WDT time-out flag

appear on the

IRQ

pin. The configuration of the time base generator along with the WDT are as shown. In the case
of on-chip RC oscillator or crystal oscillator, the power down mode can reduce power consumption since the
oscillator can be turned on or off by the corresponding system commands. At the power down mode the time
base/WDT loses all its functions.

On the other hand, if an external clock is selected as the source of system frequency the SYS DIS command
turns out invalid and the power down mode fails to be carried out. That is, after the external clock source is selected,
the SC16232 will continue working until system power fails or the external clock source is removed. After the system
power on, the

IRQ

will be disabled.

Timer/WDT

Clock Sources

/

2

n

n=0 ~ 7

/

256

/4

V

DD

R

CK

DQ

TIMEREN/DIS

WDT EN/DIS

IRQ EN/DIS

IRQ

CLR WDT

System Clock

f=32kHz

Timer and WDT configuration

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4. TONE OUTPUT

A simple tone generator is implemented in the SC16232. The tone generator can output a pair of differential
driving signals on the BZ and

BZ

, which are used to generate a single tone. By executing the TONE4K and
TONE2K commands there are two tone frequency outputs selectable. The TONE4K and TONE2K commands set
the tone frequency to 4kHz and 2kHz, respectively. The tone output can be turned on or off by invoking the TONE

ON or the TONE OFF command. The tone outputs, namely BZ and

BZ

, are a pair of differential driving outputs

used to drive a piezo buzzer. Once the system is disabled or the tone output is inhibited, the BZ and the

BZ

outputs

will remain at low level.

5. LCD DRIVER

The SC16232 is a 128(32x4) pattern LCD driver. It can be configured as 1/2 or 1/3 bias and 2 or 3 or 4 commons
of LCD driver by the S/W configuration. This feature makes the SC16232 suitable for multiply LCD applications. The
LCD driving clock is derived from the system clock. The value of the driving clock is always 256Hz even when it is at
a 32.768kHz crystal oscillator frequency, an on-chip RC oscillator frequency, or an external frequency. The LCD
corresponding commands are summarized in the table below.

Name Command Code Function

LCD OFF

10000000010X

Turn off LCD outputs

LCD ON

10000000011X

Turn on LCD outputs

BIAS & COM

1000010abXcX

c=0: 1/2 bias option
c=1: 1/3 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option

The bold form of 1 0 0, namely 100, indicates the command mode ID. If successive commands have been issued,
the command mode ID except for the first command, will be omitted. The LCD OFF command turns the LCD display
off by disabling the LCD bias generator. The LCD ON command, on the other hand, turns the LCD display on by
enabling the LCD bias generator. The BIAS and COM are the LCD panel related commands. Using the LCD related
commands, the SC16232 can be compatible with most types of LCD panels.

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6.COMMAND FORMAT

The SC16232 can be configured by the S/W setting. There are two mode commands to configure the SC16232
resources and to transfer the LCD display data. The configuration mode of the SC16232 is called command mode,
and its command mode ID is 100. The command mode consists of a system configuration command, a system
frequency selection command, a LCD configuration command, a tone frequency selection command, a timer/WDT
setting command, and an operating command. The data mode, on the other hand, includes READ, WRITE, and
READ-MODIFY-WRITE operations. The following are the data mode IDs and the command mode ID:

Operation Mode ID

READ Data 1 1 0
WRITE Data 101
READ-MODIFY-WRITE Data 1 0 1
COMMAND Command 1 0 0

The mode command should be issued before the data or command is transferred. If successive commands have
been issued, the command mode ID, namely 100, can be omitted. While the system is operating in the non-
successive command or the non-successive address data mode, the

CS

pin should be set to “1” and the previous

operation mode will be reset also. Once the

CS

pin returns to “0”, a new operation mode ID should be issued first.

7. INTERFACING

Only four lines are required to interface with the SC16232. The

CS



line is used to initialize the serial interface

circuit and to terminate the communication between the host controller and the SC16232. If the

CS

pin is set to 1,
the data and command issued between the host controller and the SC16232 are first disabled and then initialized.
Before issuing a mode command or mode switching, a high level pulse is required to initialize the serial interface of
the SC16232. The DATA line is the serial data input/output line. Data to be read or written or commands to be

writtenhavetobepassedthroughtheDATAline.The

RD

line is the READ clock input. Data in the RAM are

clocked out on the falling edge of the

RD

signal, and the clocked out data will then appear on the DATA line. It is

recommended that the host controller read in correct data during the interval between the rising edge and the next
falling edge of the

RD

signal. The

WR

line is the WRITE clock input. The data, address, and command on the

DATA line are all clocked into the SC16232 on the rising edge of the

WR

signal. There is an optional

IRQ

line to

be used as an interface between the host controller and the SC16232. The

IRQ

pin can be selected as a timer
output or a WDT overflow flag output by the S/W setting. The host controller can perform the time base or the WDT
function by being connected with the

IRQ

pin of the SC16232.

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TIMING DIAGRAMS

Read mode (command code : 1 1 0)

CS

WR

RD

DATA

Memory Address 1 (MA1) Data(MA1) Memory Address 2 (MA2) Data(MA2)

01 1 A5 A4 A3 A1A2 A0 D0 D1 D2 D3 1 1 0 A5 A4 A3 A1A2 A0 D0 D1 D2 D3

READ mode (successive address reading)

1 1 0 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0A5

CS

WR

RD

DATA

Memory Address (MA)

Data (MA)

Data (MA+1)

Data (MA+2)

Data (MA+3)

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TIMING DIAGRAMS

(continued)

WRITE mode (command code : 1 0 1)

CS

WR

DATA

0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 01 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3

1

Memory Address 2(MA2)Data (MA1) Data (MA2)Memory Address 1(MA1)

WRITE mode (successive address writing)

CS

WR

DATA

0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D2D1 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0

1

MemoryAddress (MA) Data (MA) Data (MA+3)

D0

Data (MA+1) Data (MA+2)

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TIMING DIAGRAMS

(continued)

READ-MODIFY-WRITE MODE (command code : 1 0 1)

1 0 1 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 1 0 1 A4 A3 A2 A1 A0 D0 D1 D2 D3A5

DATA

CS

RD

WR

Memory Address(MA1)

Data(MA1) Data(MA1)

Memory Address(MA2)

Data(MA2)

READ-MODIFY-WRITE mode (successive address accessing)

1 0 1 A5A4A3A2A1A0D0D1D2D3D0D1D2D3D0D1D2D3D0D1D2D3D0D1D2D3D0

Memory Address(MA) Data (MA) Data (MA) Data (MA+1) Data (MA+1) Data (MA+2)

DATA

RD

WR

CS

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TIMING DIAGRAMS

(continued)

Command mode (command code : 1 0 0)

1 0 0 C8C7C6C5 C8 C3C2C1C0C4 C3 C2 C1 C0 C7 C6 C5 C4

Command 1 Command or Data ModeCommand ... Commandi

DATA

CS

WR

Mode (data and command mode)

DATA

CS

WR

RD

Command

or

Data Mode

Address &Data

Command

or

Data Mode

Address &Data Address &Data

Command

or

Data Mode

Note: It is recommended that the host controller should read in the data from the DATA line between the rising edge

of the

RD

line and the falling edge of the nextRDline.

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TYPICAL APPLICATION CIRCUITS

SC16232

9
10
11
12

18
16
14

21 24 8 25

20

19

17

16



C

*R

ExternalClock 1
ExternalClock 2

On-chip OSC

Crystal

32768Hz

Clock Out

DATA

OSCI

OSCO

CS

RD

WR

IRQ

COM0 ~ COM3 SEG0 ~ SEG31

BZ

BZ

V

LCD

V

DD

LCD Panel

Piezo

VR

1/2 or1/3 Bias; 1/2,1/3 or1/4 Duty

Notes: The connection of

IRQ

andRDpin can be selected depending on the requirement of the µC.

The voltage applied to V

LCD

pin must be lower than VDD.

Adjust V

R

to fit LCD display, at VDD=5V,

V

LCD

=4V,VR=15kΩ±20%, Adjust R(external pull-high resistance) to fit user’s time base clock.

Silan
Semiconductors



SC16232



HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD



Rev: 2.0 2002.04.26.



16

COMMAND SUMMARY

Name ID Command Code D/C Function Def.

READ

110

A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM

WRITE

101

A5A4A3A2A1A0D0D1D2D3 D Write data to the RAM

READ-MODIFY-WRITE

101

A5A4A3A2A1A0D0D1D2D3 D READ and WRITE to the RAM

SYS DIS

100

0000-0000-X C

Turn off both system oscillator
and LCD bias generator

Yes

SYS EN

100

0000-0001-X C Turn on system oscillator

LCD OFF

100

0000-0010-X C Turn off LCD bias generator Yes

LCD ON

100

0000-0011-X C Turn on LCD bias generator

TIMER DIS

100

0000-0100-X C Disable time base output

WDTDIS

100

0000-0101-X C Disable WDT time-out flag output

TIMER EN

100

0000-0110-X C Enable time base output

WDTEN

100

0000-0111-X C Enable WDT time-out flag output

TONE OFF

100

0000-1000-X C Turn off tone outputs Yes

TONE ON

100

0000-1001-X C Turn on tone outputs

CLR TIMER

100

0000-11XX-X C

Clear the contents of time base
generator

CLR WDR

100

0000-111X-X C Clear the contents of WDT stage

XTAL 32K

100

0001-01XX-X C

System clock source, crystal
oscillator

RC 256K

100

0001-10XX-X C

System clock source, on-chip RC
oscillator

Yes

EXT 256K

100

0001-11XX-X C

System clock source, external
clock source

BIAS 1/2

100

0010-abX0-X C

LCD 1/2 bias option
ab=00:2 commons option
ab=01:3 commons option
ab=10:4 commons option

BIAS 1/3

100

0010-abX1-X C

LCD 1/3 bias option
ab=00:2 commons option
ab=01:3 commons option
ab=10:4 commons option

TONE 4K

100

010X-XXXX-X C Tone frequency, 4kHz

TONE 2K

100

011X-XXXX-X C Tone frequency, 2kHz

IRQ

DIS

100

100X-0XXX-X C

Disable

IRQ

output

Yes

(to be continued)

Silan
Semiconductors



SC16232

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HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD



Rev: 2.0 2002.04.26.



17

COMMAND SUMMARY (continued)

Name ID Command Code D/C Function Def.

IRQ

EN

100

100X-1XXX-X C

Enable

IRQ

output

F1

100

101X-X000-X C

Time base/WDT clock
Output: 1Hz
The WDT time-out flag after: 4s

F2

100

101X-X001-X C

Time base/WDT clock
Output: 2Hz
The WDT time-out flag after: 2s

F4

100

101X-X010-X C

Time base/WDT clock
Output: 4Hz
The WDT time-out flag after:1s

F8

100

101X-X011-X C

Time base/WDT clock
Output: 8Hz
The WDT time-out flag after:1/2s

F16

100

101X-X100-X C

Time base/WDT clock
Output: 16Hz
The WDT time-out flag after:1/4s

F32

100

101X-X101-X C

Time base/WDT clock
Output: 32Hz
The WDT time-out flag after:1/8s

F64

100

101X-X110-X C

Time base/WDT clock
Output: 64Hz
The WDT time-out flag after:1/16s

F128

100

101X-X111-X C

Time base/WDT clock
Output: 128Hz
The WDT time-out flag after:1/32s

Yes

TOPT

100

1110-0000-X C Test mode

TNORMAL

100

1110-0011-X C Normal mode Yes

Notes: X: Don’t care, A5 ~ A0: RAM addresses, D3 ~ D0: RAM data, D/C: Data/command mode,

Def.: Power on reset default.

All the bold forms, namely 110, 101, and 100, are mode commands. Of these, 100indicates the
command mode ID. If successive command have been issued, the command mode ID except for the first
command will be omitted. The source of the tone frequency and of the time base/WDT clock frequency can
be derived from an on-chip 256kHz RC oscillator, a 32,768kHz crystal oscillator, or an external 256kHz clock.
Calculation of the frequency is based on the system frequency sources as stated above. It is recommended
that the host controller should initialize the SC16232 after power on reset, for power on reset may fail, which

in turn leads to the malfunctioning of the SC16232.

Silan
Semiconductors



SC16232



HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD



Rev: 2.0 2002.04.26.



18

CHIP TOPOGRAPHY

48

1

47

46

45

44

43

42

41

40

39

38

37

36

35

34

32 3031 29 28 27 26 25 24 23 22 21 20

19
18
17
16
15
14
13

12

11

1098

6542333 7

Chip size: 2.25 x 2.42(mm2)

Silan
Semiconductors



SC16232



HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD



Rev: 2.0 2002.04.26.



19

PAD COORDINATES

(Unit: µm)

PAD NO. X Y PAD NO. X Y

1 -1000 -1080 25 300 1080
2 -320 -1080 26 150 1080
3 -190 -1080 27 15 1080
4 -60 -1080 28 -125 1080
5 70 -1080 29 -265 1080
6 200 -1080 30 -405 1080
7 575 -1080 31 -545 1080
8 705 -1080 32 -685 1080

9 835 -1080 33 -1000 1080
10 1000 -1080 34 -1000 945
11 1000 -865 35 -1000 810
12 1000 -670 36 -1000 675
13 1000 -530 37 -1000 540
14 1000 -400 38 -1000 405
15 1000 -270 39 -1000 270
16 1000 -140 40 -1000 135
17 1000 -10 41 -1000 0
18 1000 120 42 -1000 -135
19 1000 250 43 -1000 -270
20 995 1080 44 -1000 -405
21 855 1080 45 -1000 -540
22 715 1080 46 -1000 -675
23 575 1080 47 -1000 -810
24 435 1080 48 -1000 -945

Note: The original point of the coordinate is the die center.

Silan
Semiconductors



SC16232



HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD



Rev: 2.0 2002.04.26.



20

Attach

Revision History

Data REV Description Page

2000.12.31 1.0 Original

2002.04.26 2.0

Add the “ ORDERING INFORMATION”
The “SC1621” change to “SC16232”

1