Datasheet SC1545CSTR Datasheet (Semtech Corporation)

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

500mA SmartLDOTM With Power Up
Signal Sequencing

SC1545

PRELIMINARY - January 17, 2000

1

TEL:[phone] FAX:[phone] WEB:http://www.semtech.com

DESCRIPTION

The SC1545 was designed for instantly available moth­erboard applications. As part of the Semtech family of
SmartLDO’s it provides additional control functions not
available in a standard LDO.

The device provides the capability to control three sep­arate supplies. There is an on-board 500mA, 2.5V
LDO with current limit protection, and drive pins for an
N-channel MOSFET and a P-channel MOSFET. Inter­nal logic circuitry ensures that the system starts up in a
controlled manner, and that the correct outputs are en­abled during specific sequences of BF_CUT and SLP.

The LDO draws its power from the 5V standby supply,
and the N-channel MOSFET drive is derived from the
12V supply.

The SC1545 is available in the surface mount SO-8
package.

FEATURES

•

500mA LDO with Over Current Protection (OCP)

•

±2.5% LDO regulation over line, load and
temperature

•

Power sequencing for three supplies

APPLICATIONS

•

Instantly available motherboards

•

Embedded systems

•

Desktop computers

ORDERING INFORMATION

Part Number

(1)

Package

SC1545CS SO-8
Note:

(1) Add suffix ‘TR’ for tape and reel packaging.

TYPICAL APPLICATION CIRCUIT

2.5V OUT

5V STANDBY
12V IN
BF_CUT
SLP

2.5V IN

2.5V OUT

3.3V IN

3.3V OUT

U1

SC1545

1
2
3
4 5

6

7

8

VO
GND
PDR
NDR SLP

BF_CUT

12VIN

5VSTBY

C5
10uF

C6
1uF

C7

0.1uF

C1
2 x 100uF

Q1

Si4410

Q2

IRLMS6802
C2
100uF

C3
2 x 100uF

C4
100uF

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

500mA SmartLDOTM With Power Up
Signal Sequencing

SC1545

PRELIMINARY - January 17, 2000

2

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Maximum Units

12V Input Voltage Range 12VIN -0.3 to +15 V
5V Input Voltage Range 5VSTBY -0.3 to +7 V
P-channel MOSFET Gate Drive PDR -0.3 to 5VSTBY V
N-channel MOSFET Gate Drive NDR -0.3 to 12VIN V
Input Pins -0.3 to +7 V
Operating Ambient Temperature Range T

A

0 to +70 °C

Operating Junction Temperature Range T

J

0 to +125 °C

Storage Temperature Range T

STG

-65 to +150 °C

Lead Temperature (Soldering) 10 Sec T

LEAD

300 °C

Thermal Impedance Junction to Case

θ

JC

47 °C/W

Thermal Impedance Junction to Ambient

(1)

θ

JA

65 °C/W

ESD Rating ESD 2 kV

ELECTRICAL CHARACTERISTICS

Unless specified, 12V I N = 12V, 5VSTBY = 5V, CO = 100µF min., TA = 25°C. Values in

bold

apply over full operating temperat ure range.

Parameter Symbol Test Conditions MIN TYP MAX Units
12VIN

Supply Voltage 12VIN

11.28

12.00

12.72

V

Quiescent Current I

Q12

800 1000 µA

1200

5VSTBY

Supply Voltage 5VSTBY

4.7

5.0

5.3

V

Quiescent Current I

Q5

LDO ON 9.5 11

12

mA

LDO OFF 3.0 4.0

5.0

Undervoltage Lockout (5V)

UVLO Threshold UVLO 5VSTBY rising

4.1

4.3

4.5

V

5VSTBY falling

3.9

4.1

4.3

V
Hysteresis HYST 200 mV
Logic Reset Threshold RST

1.5

2.0

2.5

V

Note:
(1) 2 inch square of 1/16” FR-4, double sided, 1 oz. minimum copper weight.

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

500mA SmartLDOTM With Power Up
Signal Sequencing

SC1545

PRELIMINARY - January 17, 2000

3

ELECTRICAL CHARACTERISTICS (Cont.)

Unless specified, 12V I N = 12V, 5VSTBY = 5V, CO = 100µF min., TA = 25°C. Values in

bold

apply over full operating temperat ure range.

Parameter Symbol Test Conditions MIN TYP MAX Units
VO

LDO Output Voltage V

O

4.7V

≤

5VSTBY ≤ 5.3V,

-1.5% 2.525 +1.5% V

1mA ≤ I

O

≤ 500mA

-2.5% +2.5%

LDO Output Voltage During
Load Transients

(1)

V

O(T)

Load step between 0mA and 500mA at

8A/µs max.

-3.0%

2.525

+3.0%

V

Time To Regulation

(2)

t

REG

5

µs

Inputs (BF_CUT & SLP)

Input Resistance R

IN

BF_CUT = SLP = 5V

1.0

10.0

M

Ω

High Level Input Voltage V

IH

2.0

V
Low Level Input Voltage V

IL

0.8

V

NDR

Peak Drive Current I

NDR(PK)

Sinking: NDR = 0.5V

Sourcing: NDR = 10V

30

mA

Output Voltage V

NDR

Full ON, I

NDR

= 100µA

10

12 V

Drive Low Delay t

DL(N)

Measured from BF_CUT threshold to

90% of NDR

150

ns

Fall Time t

f(N)

Measured from 90% to 10%

1.0

µs

Drive High Delay t

DH(N)

Measured from BF_CUT/SLP threshold

to 10% of NDR

300

ns

Rise Time t

r(N)

Measured from 10% to 90%

1.0

µs

PDR

Peak Drive Current I

PDR(PK)

Sinking: PDR = 0.5V

Sourcing: PDR = 3.5V

30

mA

Output Voltage V

PDR

Full ON, I

PDR

= 100µA

3.5

5V

Drive Low Delay t

DL(P)

Measured from BF_CUT threshold to

90% of PDR

150

ns

Fall Time t

f(P)

Measured from 90% to 10%

1.0

µs

Drive High Delay t

DH(P)

Measured from BF_CUT/SLP threshold

to 10% of PDR

300

ns

Rise Time t

r(P)

Measured from 10% to 90%

1.0

µs

Overcurrent Protection

Current Limit Threshold I

CL

VO = 0V

550

mA

NOTES:

(1) The LDO will bring the output back to within the regular V

O

limits in less than 10µs.

(2) External 2.5V ± 2.5% applied at output, turning off when NDR goes low. C

O

= 100µF to 400µF, IO = 50mA to

200mA.

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

500mA SmartLDOTM With Power Up
Signal Sequencing

SC1545

PRELIMINARY - January 17, 2000

4

BLOCK DIAGRAM

PIN DESCRIPTION

Pin Pin Name Pin Function

1 VO LDO 2.5V output.
2 GND Logic and power ground.
3 PDR Gate drive signal for P-channel MOSFETs.
4 NDR Gate drive signal for N-channel MOSFETs.
5 SLP Control input #1.
6 BF_CUT Control input #2.
7 12VIN +12V input supply. Used for generating NDR only.
8 5VSTBY +5V input supply.

PIN CONFIGURATION

Top View

SOIC-8

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

500mA SmartLDOTM With Power Up
Signal Sequencing

SC1545

PRELIMINARY - January 17, 2000

5

TYPICAL CHARACTERISTICS

0

100

200

300

400

500

600

700

800

900

1000

0 255075100125

T

J

(°C)

I

Q12

(µA)

12VIN = 12V

12VIN Quiescent Current vs.

Junction Temperature

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

0 255075100125

T

J

(°C)

I

Q5(ON)

(mA)

5VSTBY = 5V

5VSTBY Quiescent Current (ON) vs.

Junction Temperature

4.0

4.1

4.1

4.2

4.2

4.3

4.3

4.4

4.4

4.5

4.5

0255075100125

T

J

(°C)

UVLO (V)

5VSTBY RISING

5VSTBY FALLING

5VSTBY Under Voltage Lockout vs.

Junction Temperature

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 255075100125

T

J

(°C)

I

Q5(OFF)

(mA)

5VSTBY = 5V

5VSTBY Quiescent Current (OFF) vs.

Junction Temperature

0

1

2

3

4

5

6

7

8

9

10

0255075100125

T

J

(°C)

REG

LINE

(mV)

5VSTBY = 4.7V to 5.3V

LDO Line Regulation vs.

Junction Temperature

2.500

2.505

2.510

2.515

2.520

2.525

2.530

2.535

2.540

2.545

2.550

0 255075100125

T

J

(°C)

V

O

(V)

IO = 1mA

I

O

= 500mA

5VSTBY = 5V

LDO Output Voltage vs.

Junction Temperature

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

500mA SmartLDOTM With Power Up
Signal Sequencing

SC1545

PRELIMINARY - January 17, 2000

6

TIMING DIAGRAMS

Power up signal sequencing is shown in Figure 1. BF_CUT, PDR and NDR follow the power rails up to their final
values. SLP goes to its high value when the power rails have stabilized, ~25msec after power on. BF_CUT is
pulled low a period T1 after SLP goes high. T1 can be as short as 1msec. Typical measured values are
~200msec. The 2.5V LDO output stays OFF through this sequence.

Figure 1: Power Up Signal Sequencing

TYPICAL CHARACTE RIS TICS (Cont.)

0

100

200

300

400

500

600

700

800

900

1000

0 255075100125

T

J

(°C)

I

CL

(mA)

VO = 0V

VDO Current Limit vs.
Junction Temperature

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

500mA SmartLDOTM With Power Up
Signal Sequencing

SC1545

PRELIMINARY - January 17, 2000

7

Signal sequencing for the second possible sequence is shown in Figure 3. BF_CUT goes from LOW to HIGH and
SLP goes from HIGH to LOW, 30µsec to 65µsec (T3) later. When BF_CUT goes HIGH, PDR and NDR go LOW
and the 2.5V LDO turns ON. When SLP goes LOW, PDR and NDR return to HIGH and the 2.5V LDO turns OFF.
BF_CUT will stay HIGH and SLP will stay low for an undetermined time, after which SLP will go HIGH. A minimum
of 1msec (T4) later, BF_CUT will go LOW and the system is back at the end of the power up sequence. Typical
measured values of T4 are ~250msec. During all transitions, the propagation delays, rise and fall times, and going
into regulation times for PDR, NDR and 2.5V LDO are described in Electrical Characteristics on page 3. The sec­ond sequence can start at any time after the end of the power up sequence.

TIMING DIAGRAMS (Cont.)

After power up, there are two possible signal sequences that the device will see. The first sequence is with SLP
staying HIGH and BF_CUT transitioning from LOW to HIGH, remaining HIGH for an undetermined period and then
going back to LOW. At this point, the system state is back to where it was at the end of the power up sequence.
The sequence is shown in Figure 2 (below). During these BF_CUT transitions, the propagation delays, rise and fall
times and going into regulation times for PDR, NDR and VO are described in Electrical Characteristics on page 3.
The first sequence can start at any time after the end of the power up sequence.

Figure 2: 1st Sequence Timing

Figure 3: 2nd Sequence Timing

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

500mA SmartLDOTM With Power Up
Signal Sequencing

SC1545

PRELIMINARY - January 17, 2000

8

OUTLINE DRAWING

JEDEC

REF: MS-012AA

MINIMUM LAND PATTERN - SO-8

ECN99-694
ECN00-831