Datasheet SC1532CS.TR Datasheet (Semtech Corporation)

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

400mA SmartLDO

TM

with Internal Pass

MOSFET

SC1532

January 3, 2000

1

TEL:[phone] FAX:[phone] WEB:http://www.semtech.com

DESCRIPTION

Intended for applications such as Power Managed PCI,
the SC1532 is designed to maintain a glitch-free 3.3V
output when at least one of two inputs, 5V (VIN1) and

3.3V (VIN2), is present.
The SC1532 combines a 5V to 3.3V linear regulator

with an integral 3.3V bypass switch, along with logic
and detection circuitry to control which supply provides
the power for the output.

Whenever VIN1 exceeds a predetermined threshold
value, the internal 3.3V PMOS linear regulator is en­abled, and the internal pass NMOS is turned off.
When VIN1 falls below a lower threshold value, the
NMOS pass device is turned on and the PMOS linear
regulator is turned off. This ensures an uninterrupted

3.3V output even if VIN1 falls out of specification.
When both supplies are simultaneously available, the

PMOS linear regulator will be turned on, and the
NMOS pass will be turned off, thus preferentially sup­plying the output from the 5V supply.

The internal 5V detector has its upper threshold (for
VIN1 rising) set to 4.18V (typical) while the lower
threshold (for VIN falling) is at 4.1V (typical) giving a
hysteresis of approximately 80mV.

The SC1532 is available in the popular SO-8 surface
mount package.

FEATURES

•

Glitch-free transition between input sources

•

Internal logic selects input source

•

5V detector with hysteresis

•

1% regulated output voltage accuracy

•

400mA load current capability

APPLICATIONS

•

Desktop Computers

•

Network Interface Cards (NICs)

•

PCMCIA/PCI Interface Cards

•

Peripheral Cards

ORDERING INFORMATION

Part Number

(1)

Package

SC1532CS SO-8

Note:
(1) Add suffix ‘TR’ for tape and reel packaging.

TYPICAL APPLICATION CIRCUIT

3.3VAUX IN
5V IN

3.3V OUT

U1

SC1532

1
2
3
4 5

6

7

8

VIN2
VIN1
VO
CP GND

GND

GND

GND

C4
1nF

C1

4.7uF

C2

4.7uF

C3

4.7uF

NOTES:

(1) Ceramic capacitors are recommended - see Applications Information for further details.
(2) Output capacitor C3 needs to be 1.0uF or greater for stability. Additional capacitance (tantalum or ceramic) will
improve overall performance.

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

400mA SmartLDO

TM

with Internal Pass

MOSFET

SC1532

January 3, 2000

2

NOTE:

(1) 1 inch square of 1/16” FR-4, double sided, 1 oz. minimum copper weight.

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Maximum Units

Input Supply Voltages VIN1, VIN2 -0.5 to +7 V
Charge Pump Capacitor Pin Voltage CP -0.5 to +16 V
Output Current I

O

400 mA

Operating Ambient Temperature Range T

A

-5 to +70 °C

Operating Junction Temperature Range T

J

-5 to +125 °C

Storage Temperature Range T

STG

-65 to +150 °C

Lead Temperature (Soldering) 10 Sec T

LEAD

300 °C

Thermal Impedance Junction to Ambient

(1)

θ

JA

65 °C/W

ESD Rating (Human Body Model) ESD 4 kV

ELECTRICAL CHARACTERISTICS

Unless specified, TA = 25°C, VIN1 = 5V, VIN2 = 3.3V , IO = 400mA, CIN1 = 4.7uF, CIN2 = 4.7uF, CO = 4.7uF, Cp=1nF.
Values in

bold

apply over full operating temperat ure range.

Parameter Symbol Test Conditions MIN TYP MAX Units
VIN1

Supply Voltage VIN1 VIN2 = 0V 4.3 5.0 5.5 V
Quiescent Current I

Q1

VIN1 = 5V, 0V ≤ VIN2 ≤ 3.6V, IO = 0mA

2.0 3.0 mA

4.0

Reverse Leakage From VIN2

(1)

I

VIN1

VIN1 = 0V, VIN2 = 3.6V, IO = 0mA 0

1

µA

VIN2

Supply Voltage VIN2 3.0 3.3 3.6 V
Quiescent Current I

Q2

VIN2 = 3.3V, 0V ≤ VIN1 ≤ 5.5V, IO = 0mA

650 1300 µA

2000

Reverse Leakage From VIN1

(1)

I

VIN2

VIN1 = 5.5V, VIN2 = 0V, IO = 0mA 0

1

µA

5V Detect

(1)(2)

Low Threshold Voltage V

TH(LO)

VIN1 Falling, IO = 20mA

3.90

4.10 V

Hysteresis V

HYST

IO = 20mA 60 80 150 mV

High Threshold Voltage V

TH(HI)

VIN1 Rising, IO = 20mA 4.18

4.30

V

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

400mA SmartLDO

TM

with Internal Pass

MOSFET

SC1532

January 3, 2000

3

NOTES:

(1) Guaranteed by design.
(2) Recommended source impedance for 5V supply: ≤ 0.125Ω. This will ensure clean transitions between supplies
with no “chattering” (see Applications Information).
(3) Refer to block diagram.

ELECTRICAL CHARACTERISTICS (Cont.)

Unless specified, TA = 25°C, VIN1 = 5V, VIN2 = 3.3V , IO = 400mA, CIN1 = 4.7uF, CIN2 = 4.7uF, CO = 4.7uF, Cp=1nF.
Values in

bold

apply over full operating temperat ure range.

Parameter Symbol Test Conditions MIN TYP MAX Units
VO

LDO Voltage Accuracy VO I

O

= 20mA -1 +1 %

4.3V ≤ VIN1 ≤ 5.5V, 0mA ≤ I

O

≤ 400mA

(1)

-2 +2

3.90V ≤ VIN1 ≤ 4.3V, VIN2 = 3.3V,
0mA ≤ I

O

≤ 400mA

(1)

3.000

V

VIN2 Pass Device On Resis- R

DS(ON)

VIN1 < 3.9V, 0mA ≤ IO ≤ 400mA

360

500

m

Ω

tance

(Aux. NMOS)

(1)(3)

Line Regulation REG

(LINE)

VIN1 = 4.3V to 5.5V 0.3 0.6 %

0.7

Load Regulation REG

(LOAD)

IO = 20mA to 400mA 0.3 0.6 %

0.7

Current Limit (LDO)

Output Current I

LIM

VIN1 = 5V, VIN2 = 0V, VO = 0V 600 975 1200 mA

1400

Over Temperature Protection

High Trip Level T

HI

VIN1=5V 175 ºC

Hysteresis T

HYS

VIN1=5V 10 ºC

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

400mA SmartLDO

TM

with Internal Pass

MOSFET

SC1532

January 3, 2000

4

Top View

(SO-8)

PIN DESCRIPTIONS

Pin Pin Name Pin Function

1 VIN2 Secondary input supply, nominally 3.3V.
2 VIN1 Main input supply for the IC, nominally 5V.
3 VO 3.3V out.
4 CP Charge pump capacitor connection.
5 GND Ground pin.
6 GND Ground pin.
7 GND Ground pin.
8 GND Ground pin.

PIN CONFIGURATION

BLOCK DIAGRAM

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

400mA SmartLDO

TM

with Internal Pass

MOSFET

SC1532

January 3, 2000

5

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

-25 0 25 50 75 100 125

T

J

(°C)

REG

(LOAD)

(%)

VIN1 = 5V
VIN2 = 3.3V
IO = 20mA to 400mA

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

-25 0 25 50 75 100 125

T

J

(°C)

REG

(LINE)

(%)

VIN1 = 4.3V to 5.5V
IO = 400mA

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

-25 0 25 50 75 100 125

T

J

(°C)

I

Q1

(mA)

VIN1 = 5V
IO = 0mA

VIN2 = 3.6V

VIN2 = 0V

TYPICAL CHARACTERISTICS

Quiescent Current (IQ1) vs.

Junction Temperature vs. VIN2

0

100

200

300

400

500

600

700

800

-25 0 25 50 75 100 125

T

J

(°C)

I

Q2

(µA)

VIN1 = 0V

VIN1 = 5.5V

VIN2 = 3.3V
I

O

= 0mA

Quiescent Current (IQ2) vs.

Junction Temperature vs. VIN1

LDO Line Regulation vs.

Junction Temperature

LDO Load Regulation vs.

Junction Temperature

3.270

3.275

3.280

3.285

3.290

3.295

3.300

3.305

3.310

-25 0 25 50 75 100 125

T

J

(°C)

V

O

(V)

IO = 0mA

I

O

= 200mA

I

O

= 400mA

VIN1 = 5V
VIN2 = 3.3V

LDO Output Voltage vs. Junction

Temperature vs. Output Current

0

200

400

600

800

1000

1200

-25 0 25 50 75 100 125

T

J

(°C)

I

LIM

(mA)

VIN1 = 5V
VIN2 = 0V
VO = 0V

LDO Current Limit vs.
Junction Temperature

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

400mA SmartLDO

TM

with Internal Pass

MOSFET

SC1532

January 3, 2000

6

0

50

100

150

200

250

300

350

400

450

500

-25 0 25 50 75 100 125

T

J

(°C)

R

DS(ON)

(m

Ω

ΩΩ

Ω

)

VIN1 = 0V
VIN2 = 3.3V
IO = 400mA

TYPICAL CHARACTERISTICS (Cont.)

VIN2 Pass Device On Resistance vs.

Junction Temperature

3.90

3.95

4.00

4.05

4.10

4.15

4.20

4.25

4.30

-25 0 25 50 75 100 125

T

J

(°C)

V

TH

(V)

VIN2 = 3.3V
IO = 20mA

V

TH(HI)

V

TH(LO)

5V Detect Threshold Voltage vs.

Junction Temperature

VO

(MIN)

With VIN1 Rising

(1)(2)

Trace 1: VO, offset 3.3V, 100mV/div.
Trace 2: VIN1 rising through V

TH(HI)

, 2V/div.

VO

(MIN)

= 3.11V

VO

(MIN)

With VIN1 Falling

(1)(2)

Trace 1: VO, offset 3.3V, 100mV/div.
Trace 2: VIN1 falling through V

TH(LO)

, 2V/div.

VO

(MIN)

= 3.05V

NOTES:

(1) In Application Circuit on page 1.
(2) R

L

= 8.2

Ω.

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

400mA SmartLDO

TM

with Internal Pass

MOSFET

SC1532

January 3, 2000

7

TYPICAL CHARACTERISTICS (Cont.)

Transient Load Response

(1)

Trace 1: VO, offset 3.3V, 50mV/div.
Trace 2: I

O

stepping from 0mA to 400mA

NOTES:

(1) In Application Circuit on page 2.

APPLICATIONS INFORMATION

Introduction

The SC1532 is intended for applications such as power
managed PCI and network interface cards (NICs),
where operation from a 3.3V VAUX supply may be re­quired when the 5V supply has been shut down. It pro­vides a simple, low cost solution that uses very little
pcb real estate. During regular operation, 3.3V power
for the PCI card is provided by the SC1532’s on-board
low dropout regulator, generated from the 5V supply.
When the 5V supply is removed and 3.3V VAUX is
available, the SC1532 connects this supply directly to
its output using an internal NMOS pass device.

Component Selection

Output capacitors - Semtech recommends a 4.7µF or
greater ceramic capacitor at the output for the best
combination of performance and cost effectiveness.
Increasing the capacitance value improves transient
response and glitch performance. The SC1532 is very
tolerant of output capacitor value and ESR variations,
in fact any combination of capacitors with C ≥ 1µF and

ESR < 1Ω is sufficient for stability. This target is easily
met using surface mount ceramic or tantalum capaci­tors.

Input capacitors - Semtech recommends the use of a

4.7µF ceramic capacitor at both inputs. This allows for
the device being some distance from any bulk capaci­tance on the rail. Additionally, input droop due to load
transients is reduced, improving load transient re­sponse and aiding smooth supply transitions. Tanta­lum capacitors should not be used.

Charge pump capacitor - Semtech recommends the
use of a 1nF ceramic capacitor between CP and GND.

Thermal Considerations

When operating from the 5V supply, the power dissipa­tion in the SC1532 is approximately equal to the prod­uct of the output current and the input to output voltage
differential:

The absolute worst-case dissipation is given by:

Note that the VIN2

(MAX)

x I

Q2(MAX)

term does not apply if

VIN2 is not supplied.

()

OD

IVO1VINP

•−≈

()

)MAX(2Q)MAX(

)MAX(1Q)MAX()MAX(O)MIN()MAX()MAX(D

I2VIN

I1VINIVO1VINP

•+

•+•−=

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

400mA SmartLDO

TM

with Internal Pass

MOSFET

SC1532

January 3, 2000

8

APPLICATIONS INFORMATION (Cont.)

Inserting VIN1 = 5.5V, VO = 3.234V, IO = 400mA,
VIN2 = 3.6V, I

Q1

= 4mA and IQ2 = 2mA yields:

Using this figure, we can calculate the maximum ther­mal impedance allowable to maintain T

J

≤ 125°C at an

ambient temperature of 55°C:

This is readily achievable using pcb copper area to aid
in conducting the heat away from the device (see Fig­ure 1 below).

VIN1 Source Impedance

In order to ensure seamless transitions between sup­plies with VIN1 rising and falling, it is recommended
that the source impedance of VIN1 is less than

0.125Ω. This is because as the output current
switches from VIN1 to VIN2 and visa-versa, the sup­plies can “chatter” if:

In general, this can be avoided by minimizing supply
trace lengths and resistances. In circumstances where
the source impedance is causing supply “chattering”,
increasing the value of the VIN1 input capacitor should
solve the problem by reducing the instantaneous drop
or jump in VIN1 as the supplies are switched.

Layout Considerations

While layout for linear devices is generally not as criti­cal as for a switching application, careful attention to
detail will ensure reliable operation. See Figure 1 below
for a sample layout.

1) Attaching the part (pins 5 to 8) to a larger copper
footprint will enable better heat transfer from the de­vice, especially on PCBs where there are internal
ground and power planes.

2) Place the input and output capacitors close to the
device for optimal transient response.

()

()

W/C75

936.0

55125

P

TT

R

)MAX(D

)MAX(A)MAX(J

)MAX)(AJ(TH

°=

−

=

−

=

−

Fig. 1: Suggested pcb layout based upon Application Circuit on Page 1.

NOTES:

(1) All vias go to ground plane.
(2) Copper area on pins 5 thru 8 is recommended, 0.5” x 0.5” area only is shown. Connect to the ground plane
with a via or vias.

HYSTSOURCEO

VRI

>•

W936.0P

)MAX(D

=

Top Copper Top Silk Screen

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

400mA SmartLDO

TM

with Internal Pass

MOSFET

SC1532

January 3, 2000

9

OUTLINE DRAWING - SO-8

JEDEC

REF: MS-012AA

MINIMUM LAND PATTERN - SO-8

ECN99-789