Page 1
SC1405B
HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
March 14, 2000
1
BLOCK DIAGRAMPIN CONFIGURATION
Top View
(14-Pin TSSOP)
DESCRIPTION
The SC1405B is a Dual-MOSFET Driver with an internal Overlap Protection Circuit to prevent shoot-through
from V
IN
to GND in the main switching and synchronous MOSFET’s. Each driver is capable of driving
a 3000pF load in 15ns rise/fall time and has ULTRAFAST propagation delay from input transition to the
gate of the power FET’s. The Overlap Protection circuit
ensures that the second FET does not turn on until the
top FET source has reached a voltage low enough to
prevent shoot-through. The delay between the bottom
gate going low to the top gate transitioning to high is
externally programmable via a capacitor for optimal
reduction of switching losses at the operating frequency. The bottom FET may be disabled at light loads
by keeping S_MOD low to trigger asynchronous operation, thus saving the bottom FET’s gate drive current
and inductor ripple current. An internal voltage reference allows threshold adjustment for an Output OverVoltage protection circuitry, independent of the PWM
feedback loop. Under-Voltage-Lock-Out circuit is included to guarantee that both driver outputs are low
when the 5V logic level is less than or equal to 4.4V
(typ) at supply ramp up (4.35V at supply ramp down). A
CMOS output provides status indication of the 5V supply. A low enable input places the IC in stand-by mode
thereby reducing supply current to less than 10µA.
SC1405B is offered in a high pitch (.025” lead spacing)
TSSOP package.
FEATURES
•
Fast rise and fall times (15ns with 3000pf load)
•
14ns max. Propagation delay (BG going low)
•
Adaptive/programmable shoot-through protection
•
Wide input voltage range (4.5-25V)
•
Programmable delay between MOSFET’s
•
Power saving asynchronous mode control
•
Output overvoltage protection/overtemp shutdown
•
Under-Voltage lock-out and power ready signal
•
Less than 10µA stand-by current (EN=low)
•
Power ready output signal
•
Improved drive version of SC1405TS
•
High frequency (to 1.2MHz) operation allows use
of small inductors and low cost caps in place of
electrolytics
APPLICATIONS
•
High Density/Fast transient power supplies
•
Motor Drives/Class-D amps
•
Portable computers
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DEVICE
(1)
PACKAGE TEMP. RANGE (TJ)
SC1405B TSSOP-14 0 - 125°C
ORDERING INFORMATION
Note:
(1) Add suffix ‘TR’ for tape and reel.
Page 2
SC1405B
HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
March 14, 2000
2
NOTE:
(1) Specification refers to application circuit in Figure 1.
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Conditions Maximum Units
V
CC
Supply Voltage V
MAX5V
7V
BST to PGND VMAX
BST-PGND
30 V
BST to DRN VMAX
BST-DRN
7V
DRN to PGND VMAX
DRN-PGN
25 V
OVP_S to PGND VMAX
OVP_S-PGND
10 V
Input pin CO -0.3 to 7.3 V
Continuous Power Dissipation Pd Tamb = 25°C, T
J
= 125°C
Tcase = 25°C, T
J
= 125°C
0.66
2.56
W
Thermal Resistance Junction to Case
θ
JC
40 °C/W
Thermal Resistance Junction to Ambient
θ
JA
150 °C/W
Operating Temperature Range
T
J
0 to +125 °C
Storage Temperature Range
T
STG
-65 to +150 °C
Lead Temperature (Soldering) 10 sec
T
LEAD
300 °C
ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS)
Unless specified: -0 <
θ
J
< 125°C; VCC = 5V; 4V < V
BST
< 26V
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
Supply Voltage V
CC
V
CC
4.15 5 6.0 V
Quiescent Current Iq_stby EN = 0V 10 µA
Quiescent Current, operating Iq_op V
CC
= 5V,CO=0V 1 ma
PRDY
High Level Output Voltage V
OH
V
CC
= 4.6V, lload = 10mA 4.5 4.55 V
Low Level Output Voltage V
OL
V
CC
< UVLO threshold, lload =
10µA
0.1 0.2 V
DSPS_DR
High Level Output Voltage V
OH
VCC = 4.6V, Cload = 100pF 4.15 V
Low Level Output Voltage V
OL
VCC = 4.6V, Cload = 100pF 0.05 V
UNDER-VOLTAGE LOCKOUT
Start Threshold V
START
4.2 4.4 4.6 V
Hysteresis Vhys
UVLO
0.05 V
Logic Active Threshold V
ACT
EN is low 1.5 V
Page 3
SC1405B
HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
March 14, 2000
3
ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS) Cont.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OVERVOLTAGE PROTECTION
Trip Threshold V
TRIP
1.145 1.2 1.255 V
Hysteresis Vhys
OVP
0.8 V
S_MOD
High Level Input Voltage V
IH
2.0 V
Low Level Input Voltage V
IL
0.8 V
ENABLE
High Level Input Voltage V
IH
2.0 V
Low Level Input Voltage V
IL
0.8 V
CO
High Level Input Voltage V
IH
2.0 V
Low Level Input Voltage V
IL
0.8 V
THERMAL SHUTDOWN
Over Temperature Trip Point T
OTP
165 °C
Hysteresis T
HYST
10 °C
HIGH-SIDE DRIVER
Peak Output Current I
PKH
2A
Output Resistance Rsrc
TG
Rsink
TG
duty cycle < 2%, tpw < 100µs,
T
J
= 125°C, V
BST
- V
DRN
= 4.5V,
V
TG
= 4.0V (src)+V
DRN
or VTG = 0.5V (sink)+V
DRN
1
.7
Ω
Ω
LOW-SIDE DRIVER
Peak Output Current I
PKL
2A
Output Resistance Rsrc
BG
Rsink
BG
duty cycle < 2%, tpw < 100µs,
T
J
= 125°C
V
V_5
= 4.6V, VBG = 4V (src),
or V
LOWDR
= 0.5V (sink)
1.2
1.0
Ω
Ω
Page 4
SC1405B
HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
March 14, 2000
4
ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS) Cont.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AC OPERATING SPECIFICATIONS
HIGH-SIDE DRIVER
rise time tr
TG
, CI = 3nF, V
BST
- V
DRN
= 4.6V, 14
23
ns
fall time tf
TG
CI = 3nF, V
BST
- V
DRN
= 4.6V, 12
19
ns
propagation delay time,
TG going high
tpdh
TG
CI = 3nF, V
BST
- V
DRN
= 4.6V,
C-delay=0
20
32
ns
propagation delay time,
TG going low
tpdl
TG
CI = 3nF, V
BST
- V
DRN
= 4.6V, 15
24
ns
LOW-SIDE DRIVER
rise time tr
BG
CI = 3nF, V
V_5
= 4.6V, 15
24
ns
fall time tr
BG
CI = 3nF, V
V_5
= 4.6V, 13
21
ns
propagation delay time
BG going high
tpdh
BGHI
CI = 3nF, V
V_5
= 4.6V,
DRN <
1V
12
19
ns
progagation delay time
BG going low
tpdl
BG
CI = 3nF, V
V_5
= 4.6V, 7
12
ns
UNDER-VOLTAGE LOCKOUT
V_5 ramping up tpdh
UVLO
EN is High 10 us
V_5 ramping down tpdl
UVLO
EN is High 10 us
PRDY
EN is transitioning from low to
high
tpdhPRDY V_5 >
UVLO threshold, Delay
measured from EN >
2.0V to
PRDY >
3.5V
10 µs
EN is transitioning from high to
low
tpdh
UVLO
V_5 > UVLO threshold. Delay
measured from EN <
0.8V tp
PRDY <
10% of V_5
500 µs
DSPS_DR
rise/fall time tr
DSPS_DR,
tf
DSPS_DR
CI = 100pf, V_5 = 4.6V, 20 ns
propagation delay,
DSPS_DR going high
tpdh
DSPS_DR
S_MOD goes high and
BG goes high or S_MOD goes low
10 ns
propagation delay
DSPS_DR goes low
tpdl
DSPS_DR
S_MOD goes high and BG goes
low
10 ns
OVERVOLTAGE PROTECTION
propagation delay
OVP_S going high
tpdh
OVP_S
V_5 = 4.6V, TJ = 125°C, OVP_S >
1.2V to BG > 90% of V_5
1µs
Page 5
SC1405B
HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
March 14, 2000
5
PIN CONFIGURATION
NOTE:
(1) All logic level inputs and outputs are open collector TTL compatible.
PIN DESCRIPTION
Pin # Pin Name Pin Function
1 OVP_S Overvoltage protection sense. External scaling resistors required to set
protection threshold.
2 EN When high, this pin enables the internal circuitry of the device. When
low, TG, BG and PRDY are forced low and the supply current (5V) is
less than 10µA.
3 GND Logic GND.
4 CO TTL-level input signal to the MOSFET drivers.
5 S_MOD When low, this signal forces BG to be low. When high, BG is not a
function of this signal.
6 DELAY_C Sets the additional propagation delay for BG going low to TG going high.
Total propagation delay= 20ns + 1ns/pF.
7 PRDY This pin indicates the status of 5V. When 5V is less than 4.4V(typ) this
output is driven low. When 5V is greater than or equals to 4.4V(typ) this
output is driven to 5V level. This output has a 10mA drive capability and
10µA sink capability.
8V
CC
+5V supply. A .22-1µF ceramic capacitor should be connected from 5V
to PGND very close to this pin.
9 BG Output drive for the synchronous MOSFET.
10 PGND Power ground. Connect to the synchronous FET power ground.
11 DSPS_DR Dynamic Set Point Switch Drive. TTL level output signal. When S_MOD
is high, this pin follows the BG driver pin voltage.
12 DRN This pin connects to the junction of the switching and synchronous
MOSFET’s. This pin can be subjected to a -2V minimum relative to
PGND without affecting operation.
13 TG Output gate drive for the switching (high-side) MOSFET.
14 BST Bootstrap pin. A capacitor is connected between BST and DRN pins to
develop the floating bootstrap voltage for the high-side MOSFET. The
capacitor value is typically between 0.1µF and 1µF (ceramic).
Page 6
SC1405B
HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
March 14, 2000
6
Typical Distributed Power Supply
APPLICATION CIRCUIT
Figure 1.
DSPS_DR
P_READY
PWM IN
+5V
INPUT POWER
+
10uF,6.3V
++ +
+ ++
2.2
2.2
.22uF
47pF
.1uF
MTB75N03
MTB75N03
D1
1N5819
SC1405
13
4
3
2
1
14
6
5 10
7
9
11
12
8
TG
CO
GND
EN
OVP_S
BST
DELAY_C
S_MOD PGND
PRDY
BG
DSPS_DR
DRN
Vcc
(20KHz-1MHz)
<<
<<
>>
75A,30V
75A,30V
<<< Output Feedback to PWM
Controller
Over-Voltage Sense
TIMING DIAGRAM
Figure 2.
Page 7
SC1405B
HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
March 14, 2000
7
VOUT
VID1
VIN
EN
VID2
vcc5v
EN
+5V
+5V
VIN
VID4
VIN
VID0
+12V
ovp_sens
VID3
VOUT
VOUT
N/C
SC1405B/SC1142 2-phase Synchronous Evaluation Board
B
11
Tuesday, June 08, 1999
Title
Size Document Number Rev
Date: Sheet
of
.1u
C11
22u,10V
C32
R40
0
1u,10V
C28
R43
10
U8
SC1405B
13
432
1146
5 10
7
91112
8
TG
CO
GND
EN
OVP_S
BST
DELAY_C
S_MOD PGND
PRDY
BG
DSPS_DR
DRN
Vcc
100UF
C9
22u,10V
C13
SS12
D2
1K
R16
C55
.1
Q2
FDB7030
1.5k
R6
22u,10V
C22
300k
R11
10
R1
S1
Vout/Clk switch
1234567
8
16151413121110
9
1u,16V
C6
22u,10V
C21
.1
C27
1500uf
C30
51
R15
Q3
IR7811
22u,10V
C24
.1
C35
1u,16V
C5
R41
0
1u,10V
C15
.01
C26
20k
R10
PentiumII
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98
A99
A100
A101
A102
A103
A104
A105
A106
A107
A108
A109
A110
A111
A112
A113
A114
A115
A116
A117
A118
A119
A120
121
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
B95
B96
B97
B98
B99
B100
B101
B102
B103
B104
B105
B106
B107
B108
B109
B110
B111
B112
B113
B114
B115
B116
B117
B118
B119
B120
121
VCC_VTT
GND
VCC_VTT
IERR#
A20M#
GND
FERR#
IGNNE#
TDI
GND
TDO
PWRGOOD
TESTHI
GND
THERMTRIP#
Reserved
$PIN16
GND
$PIN18
$PIN19
$PIN20
GND
$PIN22
$PIN23
$PIN24
GND
$PIN26
$PIN27
$PIN28
GND
$PIN30
$PIN31
$PIN32
GND
$PIN34
$PIN35
$PIN36
GND
$PIN38
$PIN39
$PIN40
GND
$PIN42
$PIN43
$PIN44
GND
$PIN46
$PIN47
$PIN48
GND
$PIN50
$PIN51
$PIN52
GND
$PIN54
$PIN55
$PIN56
GND
$PIN58
$PIN59
$PIN60
GND
$PIN62
$PIN63
$PIN64
GND
$PIN66
$PIN67
$PIN68
GND
$PIN70
$PIN71
$PIN72
GND
$PIN74
$PIN75
$PIN76
GND
$PIN78
$PIN79
$PIN80
GND
$PIN82
$PIN83
$PIN84
GND
$PIN86
$PIN87
$PIN88
GND
$PIN90
$PIN91
$PIN92
GND
$PIN94
$PIN95
$PIN96
GND
$PIN98
$PIN99
$PIN100
GND
$PIN102
$PIN103
$PIN104
GND
$PIN106
$PIN107
$PIN108
GND
$PIN110
$PIN111
$PIN112
GND
$PIN114
$PIN115
$PIN116
GND
VID[2]
VID[1]
VID[4]
$PIN121
$PIN122
$PIN123
$PIN124
VCC_VTT
$PIN126
$PIN127
$PIN128
VCC_VTT
$PIN130
$PIN131
$PIN132
VCC_CORE
$PIN134
$PIN135
$PIN136
VCC_CORE
$PIN138
$PIN139
$PIN140
$PIN141
$PIN142
$PIN143
$PIN144
VCC_CORE
$PIN146
$PIN147
$PIN148
VCC_CORE
$PIN150
$PIN151
$PIN152
VCC_CORE
$PIN154
$PIN155
$PIN156
VCC_CORE
$PIN158
$PIN159
$PIN160
$PIN161
$PIN162
$PIN163
$PIN164
VCC_CORE
$PIN166
$PIN167
$PIN168
VCC_CORE
$PIN170
$PIN171
$PIN172
VCC_CORE
$PIN174
$PIN175
$PIN176
VCC_CORE
$PIN178
$PIN179
$PIN180
$PIN181
$PIN182
$PIN183
$PIN184
VCC_CORE
$PIN186
$PIN187
$PIN188
VCC_CORE
$PIN190
$PIN191
$PIN192
VCC_CORE
$PIN194
$PIN195
$PIN196
VCC_CORE
$PIN198
$PIN199
$PIN200
$PIN201
$PIN202
$PIN203
$PIN204
VCC_CORE
$PIN206
$PIN207
$PIN208
VCC_CORE
$PIN210
$PIN211
$PIN212
VCC_CORE
$PIN214
$PIN215
$PIN216
VCC_CORE
$PIN218
$PIN219
$PIN220
$PIN221
$PIN222
$PIN223
$PIN224
VCC_CORE
$PIN226
$PIN227
$PIN228
VCC5
$PIN230
$PIN231
$PIN232
VCC_L2
$PIN234
$PIN235
$PIN236
VCC_L2
$PIN238
VID[3]
VID[0]
VCC_L2
D11
5819
U7
SC1405B
13
432
1146
5 10
7
91112
8
TG
CO
GND
EN
OVP_S
BST
DELAY_C
S_MOD PGND
PRDY
BG
DSPS_DR
DRN
Vcc
1u,16V
C7
C57
.1
22u,10V
C18
10
R44
22u,10V
C19
.022
C23
10PFC33
Q1
IR7811
J1
INPUT
12345
6
1500uf
C17
22u,10V
C31
51
R14
22u,10V
C14
22u,10V
C16
51
R13
51
R12
6k
R8
1000uf,16V
C8
.6uh
L2
SS12
D1
C56
.1
10
R9
.6uh
L1
C58
.1
C25
.022
1000uf
C10
10uf
C12
D10
5819
Q4
FDB7030
22u,10V
C29
TBD
R17
R39
0
100
R7
R38
10k
1u,10V
C4
10PFC34
SC1142CSWU1
10
7
231
11
5
4
9 12
8 13
14
15
16
17
18
6
19
20
OC-
Vid3
NC
Rref
Vcc5v
Comp
Vid1
Vid0
OC+ FB
Vid4 Bgout
FBG
Enable
GND
Drv0
Vcc12v
Vid2
Drv1
Outv
22u,10V
C20
R42
0
SC1142EVB-B
**
Long PCB Trace
*
*
*
Component not required when in synchronous mode
SMOD=high
Figure 3 - APPLICATION EVALUATION
BOARD SCHEMATIC
SC1405B/SC1142 Evaluation Board.
2-Phase synchronous, Freq.=1MHz
Iout=30A max. (without external heatsink)
SLOT1 connector included for operation with and
simulating transient condition for the Pentium,
Pentium II™ processors.
Figure 3
Page 8
SC1405B
HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
March 14, 2000
8
BILL OF MATERIAL
Item Qty Reference Value Manufacturer
1 3 C4,C15,C28 1u,10V, Cer. AVX, Murata
2 3 C5,C6,C7 1u,16V, Cer. AVX, Murata
3 1 C8 1000uF, 16V Nichicon, any
4 1 C9 100uF Nichicon, any
5 1 C10 1000uf Nichicon, any
7 1 C12 10uF Nichicon, any
8 12 C13,C14,C16,C18,C19,C20,C21,C22,C24,C29,C31,C32 22u, 10V Murata
(GRM235Y5V226Z010)
9 2 C17,C30 1500uf Nichicon, Sanyo
10 2 C23,C25 .022 Avx, any
11 1 C26 .01 Avx, any
12 7 C11,C27,C35,C55,C56,C57,C58 .1 Avx, any
13 2 C33,C34 10PF Avx, any
14 2 D1,D2 SS12 General Instruments, any
15 2 D10,D11 5819 General Instruments, any
16 1 J1 Input
17 2 L1,L2 .6uh Falco, P/N: TO2508
(305) 662-9076
18 2 Q1,Q3 IR7811 Int. Rectifier
(310) 252-7099
19 2 Q2,Q4 FDB7030 Fairchild Semi.
(408) 822-2000
20 4 R1,R9,R43,R44 10 any
21 1 R6 1.5k any
22 1 R7 100 any
23 1 R8 6k any
24 1 R10 20k any
25 1 R11 300k any
26 4 R12,R13,R14,R15 51 any, Required in asynch.
operation
27 1 R16 1K any
28 1 R17 TBD any
29 1 R38 10k any
30 4 R39,R40,R41,R42 0 any
31 1 S1 Vout
Selector switch
Digikey
32 1 U2 Pentium II™ Slot 1 Connector
33 1 U1 SC1142CSW Semtech, (805) 499-2111
34 2 U7,U8 SC1405B
Page 9
SC1405B
HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
March 14, 2000
9
APPLICATION INFORMATION:
SC1405B
is the newest and the higher speed version
of the SC1405TS. It is designed to drive Low Rds_On
power MOSFET’s with ultra-low rise/fall times and
propagation delays. As the switching frequencies of
PWM controllers is increased to reduce power supply
and Class-D amplifier volume and cost, fast rise and
fall times are necessary to minimize switching losses
(TOP MOSFET) and reduce Dead-time (BOTTOM
MOSFET). While Low Rds_On MOSFET’s present a
power saving in I
2
R losses, the MOSFET’s die area is
larger and thus the effective input capacitance of the
MOSFET is increased. Often a 50% decrease in
Rds_On more than doubles the effective input gate
charge, which must be supplied by the driver. The
Rds_On power savings can be offset by the switching
and dead-time losses with a sub-optimum driver.
While discrete solution can achieve reasonable drive
capability, implementing shoot-through, programmable
delay and other housekeeping functions necessary for
safe operation can become cumbersome and costly.
The SC1405 family of parts presents a total solution for
the high-speed, high power density applications. Wide
input supply range of 4.5V-25V allows use in battery
powered applications, new high voltage, distributed
power servers as well as Class-D amplifiers.
THEORY OF OPERATION
The control input (CO) to the SC1405B is typically supplied by a PWM controller that regulates the power
supply output. (See Application Evaluation Schematic,
Figure 3). The timing diagram demonstrates the sequence of events by which the top and bottom drive
signals are applied. The shoot-through protection is
implemented by holding the bottom FET off until the
voltage at the phase node (intersection of top FET
source, the output inductor and the bottom FET drain)
has dropped below 1V. This assures that the top FET
has turned off and that a direct current path does not
exist between the input supply and ground, a condition
which both the top and bottom FET’s are on momentarily. The top FET is also prevented from turning on
until the bottom FET is off. This time is internally set to
20ns (typical) and may be increased by adding a capacitor to the C-Delay pin. The delay is approximately
1ns/pf in addition to the internal 20ns delay. The external capacitor may be needed if multiple High input capacitance MOSFET’s are used in parallel and the fall
time is substantially greater than 20ns.
It must be noted that increasing the dead-time by high
values of C-Delay capacitor will reduce efficiency since
the parallel Shottkey or the bottom FET body diode will
have to conduct during dead-time.
LAYOUT GUIDELINES
As with any high speed , high current circuit, proper
layout is critical in achieving optimum performance of
the SC1405B. The Evaluation board schematic (Refer
to figure 3) shows a dual phase synchronous design
with all surface mountable components.
While components connecting to C-Delay, OVP_S,
EN,S-MOD, DSPS_DR and PRDY are relatively noncritical, tight placement and short,wide traces must be
used in layout of The Drives, DRN, and especially
PGND pin. The top gate driver supply voltage is provided by bootstrapping the +5V supply and adding it
the phase node voltage (DRN). Since the bootstrap
capacitor supplies the charge to the TOP gate, it must
be less than .5” away from the SC1405. Ceramic X7R
capacitors are a good choice for supply bypassing near
the chip. The Vcc pin capacitor must also be less than
.5” away from the SC1405. The ground node of this
capacitor, the SC1405 PGND pin and the Source of
the bottom FET must be very close to each other,
preferably with common PCB copper land and multiple
vias to the ground plane (if used). The parallel Shottkey must be physically next to the Bottom FETS Drain
and source. Any trace or lead inductance in these connections will drive current way from the Shottkey and
allow it to flow through the FET’s Body diode, thus reducing efficiency.
PREVENTING INADVERTENT BOTTOM FET
TURN-ON
At high input voltages, (12V and greater) a fast turn-on
of the top FET creates a positive going spike on the
Bottom FET’s gate through the Miller capacitance,
Crss of the bottom FET. The voltage appearing on the
gate due to this spike is:
Vspike=Vin*crss/(Crass+ciss)
Where Ciss is the input gate capacitance of the bottom
FET. This is assuming that the impedance of the drive
path is too high compared to the instantaneous
impedance of the capacitors. (since dV/dT and thus
the effective frequency is very high). If the BG pin of
the SC1405B is very close to the bottom FET, Vspike
will be reduced depending on trace inductance, rate if
rise of current,etc.
Page 10
SC1405B
HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
March 14, 2000
10
While not shown in Figure 3, a capacitor may be added
from the gate of the Bottom FET to its source, preferably
less than .1” away. This capacitor will be added to Ciss
in the above equation to reduce the effective spike voltage, Vspike.
The selection of the bottom MOSFET must be done with
attention paid to the Crss/Ciss ratio. A low ratio reduces
the Miller feedback and thus reduces Vspike. Also
MOSFETs with higher Turn-on threshold voltages will
conduct at a higher voltage and will not turn on during
the spike. The MOSFET shown in the schematic (figure
3) has a 2 volt threshold and will require approximately 5
volts Vgs to be conducting, thus reducing the possibility
of shoot-through. A zero ohm bottom FET gate resistor
will obviously help keeping the gate voltage low.
Ultimately, slowing down the top FET by adding gate resistance will reduce di/dt which will in turn make the effective impedance of the capacitors higher, thus allowing
the BG driver to hold the bottom gate voltage low.
RINGING ON THE PHASE NODE
The top MOSFET source must be close to the bottom
MOSFET drain to prevent ringing and the possibility of
the phase node going negative. This frequency is determined by:
F
ring
=1/(2 ∏* Sqrt(Lst*Coss))
Where:
L
st
= The effective stray inductance of the top FET
added to trace inductance of the connection between top
FET’s source and the bottom FET’s drain added to the
trace resistance of the bottom FET’s ground connection.
Coss=Drain to source capacitance of bottom FET. If
there is a Shottkey used, the capacitance of the Shottkey is added to the value.
Although this ringing does not pose any power losses
due to a fairly high Q, it could cause the phase node to
go too far negative, thus causing improper operation,
double pulsing or at worst driver damage. This ringing is
also an EMI nuisance due to its high resonant frequency.
Adding a capacitor, typically 1000-2000pf, in parallel with
Coss can often eliminate the EMI issue. If double pulsing is caused due to excessive ringing, placing 4.7-10
ohm resistor between the phase node and the DRN pin
of the SC1405 should eliminate the double pulsing.
Proper layout will guarantee minimum ringing and elimi-
nate the need for external components. Use of SO8 or
other surface mount MOSFETs will reduce lead inductance and their parasitic effects.
ASYNCHRONOUS OPERATION
The SC1405B can be configured to operate in Asynchronous mode by pulling S-MOD to logic LOW, thus
disabling the bottom FET drive. This has the effect of
saving power at light loads since the bottom FET’s
gate capacitance does not have to charged at the
switching frequency. There can be a significant savings since the bottom driver can supply up to 2A pulses
to the FET at the switching frequency. There is an additional efficiency benefit to operating in asynchronous
mode. When operating in synchronous mode, the inductor current can go negative and flow in reverse direction when the bottom FET is on and the DC load is
less than 1/2 inductor ripple current. At that point, the
inductor core and wire losses, depending on the magnitude of the ripple current, can be quite significant.
Operating in asynchronous mode at light loads effectively only charges the inductor by as much as needed
to supply the load current, since the inductor never
completely discharges at light loads. DC regulation
can be an issue depending on the type of controller
used and minimum load required to maintain regulation. If there are no Shottkeys used in parallel with bottom FET, the FET’s body diode will need to conduct in
asynchronous mode. The high voltage drop of this
diode must be considered when determining the criteria for this mode of operation.
DSPS DR
This pin produces an output which is a logical duplicate
of the bottom FET’s gate drive, if S-MOD is held LOW.
OVP_S/OVER TEMP SHUTDOWN
Output over-voltage protection may be implemented on
the SC1405 independent of the PWM controller . A
voltage divider from the output is compared with the
internal bandgap voltage of 1.2V (typical). Upon exceeding this voltage, the overvoltage comparator disables the top FET, while turning on the bottom FET to
allow discharge of the output capacitors excessive voltage through the output inductor. There should be sufficient RC time constant as well as voltage headroom on
the OVP_S pin to assure it does not enter overvoltage
mode inadvertently. The SC1405 will shutdown if its Tj
exceeds 165°C.
Page 11
SC1405B
HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
March 14, 2000
11
Figure 4-Timing
diagram:
Ch1:CO input
Ch2:TG drive
Ch3:BG non-
overlap drive
Ch4:phase
node
Iout=20A (10A/
phase)
Refer to Eval.
Schematic
(fig.3)
Figure 5-Timing
diagram:
Rise/Fall times
Ch1:TG drive
Ch2:BG drive
Cursor:Tpdh
TG
Iout=20A (10A/
phase)
Refer to Eval.
Schematic
(fig.3)
Performance diagrams, Application Evaluation Board. (Fig.3)
Vin = 12V,Vout = 1.6V Top FET=IR7811
FDB7030(BL) Qgd = 23nc
Page 12
SC1405B
HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER
© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320
March 14, 2000
12
OUTLINE DRAWING TSSOP-14
ECN00-924
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