Datasheet SC1406GCTSTR Datasheet (Semtech Corporation)

POWER MANAGEMENT

Description

SC1406G

SC1406G

Power Supply Controller for Portable

Power Supply Controller for Portable

Pentium ® II & III SpeedStep Processors

Pentium ® II & III SpeedStep Processors

Features

The SC1406G PowerStep controller is a High Speed,
High Performance Hysteretic Mode PWM controller.
Teamed with the SC1405 Smart Driver, it powers ad­vanced Pentium® II and Pentium® III processors. The
SC1406G features Intel Mobile Voltage Positioning
(IMVP), which increases battery life by reducing the volt­age at the processor when it is heavily loaded. It also
directly supports Intels SpeedStep processors for even
longer battery life.

A 5-bit DAC, accurate to 0.85%, sets the output voltage
reference, and implements the 0.925V to 2.00V range
of the mobile Pentium® specifications. The hysteretic
converter uses a comparator without an error amplifier,
and therefore provides the fastest possible transient
response, while avoiding the stability issues inherent to
classical PWM controllers.

Two linear regulator controllers, coupled with appropri­ate external transistors, produce tightly regulated 1.5V
and 2.5V to complete the processor power solution.
The SC1406G also features separate soft-start con­trols for the converter and the regulators, a TTL­compatible power good indication, logic enable, and
low battery undervoltage lockout. Programmable
current limiting uses a separate comparator to protect
against overloads and short-circuits.

u High-speed hysteretic controller provides high effi

ciency over a wide operating load range

u Inherently stable
u Complete CPU power solution with two LDO drivers

u Programmable core voltage for Pentium

cessors

u Native Speed Step

®

support

®

II & III pro

Applications

u Laptop and notebook computers
u High performance microprocessor-based systems
u High efficiency distributed power supplies

Conceptual Application Circuit

+V_5

+V_5

PWM

PWM
Controller

Controller

SC1406G

SC1406G

SC1406G

SC1406G

IMVP

IMVP

IMVP

IMVP

CONTROLLER

CONTROLLER

CONTROLLER

CONTROLLER

LDO

LDO
Controller

VID [4:0]

VID [4:0]

VID [ 4 :0]

VID [ 4 :0]

Controller

LDO

LDO
Controller

Controller

SC1405

SC1405

SC1405

SC1405

Smart

Smart

Smart

Smart

MOSFET

MOSFET

MOSFET

MOSFET

Driver

Driver

Driver

Driver

3.3V

3.3V

3.3V

3.3V

+V_IN

+V_IN

Lo

Lo

+VCC_CPU_CORE

+VCC_CPU_CORE

+VCC_CPU_CORE

+VCC_CPU_CORE

0.925V-2.0V

0.925V-2.0V

Co

Co

Up to 14A

Up to 14A

1.5V

1.5V

2.5A

2.5A

+VCC_CPU_IO

+VCC_CPU_IO

+VCC_CPU_IO

+VCC_CPU_IO

2.5V

2.5V
150mA

150mA

+VCC_CPU_CLK

+VCC_CPU_CLK

+VCC_CPU_CLK

+VCC_CPU_CLK

Revision 8/3/2000

1

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SC1406G

POWER MANAGEMENT

Absolute Maximum Rating

RETEMARAPLOBMYSMUMIXAMSTINU

egatloVylppuSCCV 7ot3.0-V

tupnIyrettaBwoLNIBL7ot3.0-V

elbanENE7ot3.0-V

snipO/IrehtollA 3.0+CCVot3.0-DNGV

erutarepmeTnoitcnuJgnitarepOT

erutarepmeTegarotST

Electrical Characteristics

RETEMARAPLOBMYSSNOITIDNOCNIMPYTXAMSTINU

)CCV(ylppuS

egnaRegatloVylppuStupnI 0.33.30.6V

tnerruCtnecseiuQI

tnerruCgnitarepOI

tuOkcoLegatloVrednU

dlohserhT

tuOkcoLegatloVrednU

siseretsyH

tupnIelbanE

hgiHtupnIV<0.3

woLtupnI 8.0V

J

)sdnoces01gniredloS(erutarepmeTdaeLT

L

GTS

521+ot0C°

003C°

051ot56-C°

Unless specified: -0 < TA < 100°C; VCC = 3.3V (See test circuit)

QCC

CC

V<V0.3,wolsiNE

hgihsiNE451Am

CC

V6.3<01Aµ

CC

OLVUnisiNIBLehtdnahgihsiNE053

7.259.2V

02Vm

V5<V*7.0

CC

V

)NIBL(rotinoMyrettaBwoL

dlohserhTOLVUV

CDHT

tnerruCsaiBtupnIV>

P

DGRW

dlohserhTegatloV-revOV

dlohserhTegatloV-rednUV

EROCH

EROCL

hgiH,egatloVtuptuOI

woL,egatloVtuptuOI

I

DGRWP

V

V>

NIBL

V

NIBL

V

CAD

DGRWP

DGRWP

CDHT

CDHT

V<

CDHT

V576.1otV9.0=V*80.1

OLVU

2ã 2000 Semtech Corp.

571.1522.1572.1V

3.0±Aµ

6.00.15.01

eht,egnahcedocDIVynafoemitycnetalsµ05ehtgnirudtahtetoN(:rotareneGdooGrewoPEROCV

.)semiteromroenoetatsegnahcyamlangistuptuo

hgihsiNE)ecruos(Aµ01=V*59.0

CAD

V*88.0

CAD

CC

V*21.1

V*29.0

V

CAD

V

CAD

V

hgihsiNE,)knis(Aµ01=4.0V

nisiyrettabeht,)knis(Aµ01=

8.0V

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POWER MANAGEMENT

Electrical Characteristics Continued

RETEMARAPLOBMYSSNOITIDNOCNIMPYTXAMSTINU

SC1406G

Unless specified: -0 < TA < 100°C; VCC = 3.3V (See test circuit)

tnerruCtratStfoSretrevnoCeroC

tnerruCtratS-tfoSretrevnoCeroCI

EROCSS

tnerruc)ecruoS(egrahC6.01 54.1Aµ

tnerruc)kniS(egrahcsiD03.01 Am

noitanimreTtratS-tfoSEROCSSV 09.100.201.2V

dlohserhTegrahcsiDEROCSSV 051004Vm

CADDIV

dlohserhThgiHtupnIDIV V6.3<CCV<V0.3cV*7.0V

dlohserhTwoLtupnIDIV 8.0

)4-0(DIV,tnerruCpU-lluPtupnIDIV 11111...00000=)4-0(DIV604Aµ

ycaruccAegatloVtuptuOI

*emiTgniltteSC

CAD

CAD

Fp0001=

11111...00000=)4-0(DIV,0=58.0-58.0+%

53sµ

morfEROCVegnahcottessiDIV

)OC,SYH,FERPMC,PMC(rotarapmoCEROC

tnerruCsaiBtupnIV

egatloVtesffOtupnIV

V=

PMC

FERPMC

V3.1=2±Aµ

FERPMC

V3.1=5.1±3±Vm

tnerruCgnitteSsiseretsyHI

FERPMC

R

R

R

hgiHegatloVtuptuO nik001=ecnadepmIdaoL

woLegatloVtuptuO nik001=ecnadepmIdaoL

**emiTyaleDnoitagaporP

ehtmorf,snipecivedtaderusaeM

.noitisnartOCfo%05ottnioppirt

**semiTllaF/esiRtuptuO

%07dna%03neewtebderusaeM

T

R

noitisnartOCfostniop

V

FERPMC

T

A

T

A

C

V

R

nepo=2±

SYH

k071= W 7±01±31±

SYH

k71= W 58±001±511±

SYH

5.2V

V0.3=CCV,Fp01htiwlellarap

V6.3=CCV,Fp01htiwlellarap

Vm04±=PMCVD,V3.1=

)evirdrevoVm02±(

C°52=

egnarlluf=

Fp01=

OC

V0.3=

CC

K001=

OC

4.0V

02
03

701sn

Aµ

sn

ã 2000 Semtech Corp.

3

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POWER MANAGEMENT

Electrical Characteristics Continued

RETEMARAPLOBMYSSNOITIDNOCNIMPYTXAMSTINU

SC1406G

Unless specified: -0 < TA < 100°C; VCC = 3.3V (See test circuit)

)TESLC,FERLC,LC(rotarapmoCtimiLtnerruC

tnerruCsaiBtupnI V

tnerruCgnitteStimiLtnerruCI|

|R

FERLC

TESLC

R

TESLC

R

TESLC

R

TESLC

V3.1=5Aµ

LC

nepo=V

k071= W V

k5.24= W V

k02= W V

-

FERLC

=

V

LC

Vm01

V

-

FERLC

V

=

LC

Vm01-

-

FERLC

V

=

LC

Vm01

V

-

FERLC

=

V

LC

Vm01-

-

FERLC

V

=

LC

Vm01

V

-

FERLC

V

=

LC

Vm01-

-

FERLC

=

V

LC

Vm01

V

-

FERLC

V

=

LC

Vm01-

5.91035.04

310272

5.0010215.931

760839

222552882

841071291

5.7

Aµ

0.5

Aµ

Aµ

Aµ

R

k71= W V

TESLC

-

FERLC

V

=

LC

Vm01

5.2620035.733

Aµ

-

V

FERLC

V

=

LC

Vm01-

egatloVtesffOtupnIV

**emiTyaleDnoitagaporP

morf,snipecivedehttaderusaeM

OCfo%05ottnioppirteht

noitisnart

V-

LC

FERLC

V

V

FERLC

T

A

V3.1=4±6±Vm

FERLC

,V3.1= D Vm05±=PMCV

)evirdrevoVm02±(

C°52=

571002522

001

sn

051

4ã 2000 Semtech Corp.

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POWER MANAGEMENT

Electrical Characteristics Continued

RETEMARAPLOBMYSSNOITIDNOCNIMPYTXAMSTINU

SC1406G

Unless specified: -0 < TA < 100°C; VCC = 3.3V (See test circuit)

rellortnoCrotalugeRraeniLV5.1

tnerruCsaiBtupnIV

V,egatloVtuptuO

C

5.1_O

51BF

xamRSEWm02,Fµ65=

xamRSEWm54,Fµ051ro

%02=ecnarelotecnaticapaC

tnerruCtuptuOevirDesaBT

I

C

I

O

A

V5.1=1Am

51BF

Am005=

BhtiwTJBpnplanretxE

@05>

NIM

74.105.145.1V

Am005otAm0=

C°52=01021Am

rellortnoCrotalugeRraeniLV5.2

tnerruCsaiBtupnIV

V,egatloVtuptuO

C

5.1_O

51BF

xamRSEWm02,Fµ65=

xamRSEWm54,Fµ051ro

%02=ecnarelotecnaticapaC

tnerruCtuptuOevirDesaBT

I

C

I

O

A

V5.2=1Am

51BF

Am001=

BhtiwTJBpnplanretxE

@05>

NIM

54.205.255.2V

Am001otAm0=

C°52=5.202Am

)SSRL(tratStfoSrotalugeRraeniL

tnerruCtratStfoSgeRraeniLI

SSRL

V=tnerruCegrahC

V0=6.0-1-54.1-Aµ

SSRL

V,tnerruCegrahcsiD

SSRL

,V05.1=

OLVUnisiyrettabehtrowolsiNE

3.01 Am

dlohserhTelbanE 051004Am

dlohserhTnoitanimreTtratS-tfoS 35.107.178.1V

egatloVtupnI 39.05.106.1V

egatloVtuptuOR

**yaleDnoitagagorPR

* Guaranteed by design.
**Guaranteed by characterization.

.)desuylerarsinoitcestiucricsihT:etoN()PYBCV,TUOCV,NICV(pmalCegatloV

W051=

TUOCV

I

NICV

TUOCV

C

PYBCV

V5.2=

Votdeit

S

Aµ01-=

V

V

V5.2=SVotdeitW051=

nepOsisV8.0sVV

NIC

NICV

V571.0=573.0

01Sn

morfspetsNICV,Fp0051=

.kcabdnaV05.1otV571.0

otpetsNICVfo%05morfderusaeM

tneisnartTUOCVfo%05

ã 2000 Semtech Corp.

5

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POWER MANAGEMENT

SC1406G

Pin Configuration

Block Diagram

Top View

TSSOP - 28

Ordering Information

ECIVEDEGAKCAPT(.PMET

RTSTCG6041CS82-POSSTC°521ot0

Note:
Only available in tape and reel packaging. A reel contains 2500
devices.

)

J

6ã 2000 Semtech Corp.

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POWER MANAGEMENT

Pin Descriptions

niPemaNniPnoitcnuFniP

1SYH.gnittessiseretsyhrotarapmoceroC

2TESLC.gnittestimiltnerruC

3TUOCV.desutonfinepoevaeL.tuptuopmalcegatloV

4NICV.desutonfiDNGoteiT.tupnipmalcegatloV

5PYBCV .desutonfinepoevaeL.DNGotnipsihtmorfpacFp0051aseriuqeR.nipssapybpmalcegatloV

64DIV.tibtnacifingistsom)noitacifitnediegatlov(DIV

73DIVtupniDIV

82DIVtupniDIV

91DIVtupniDIV

010DIV.tibtnacifingistsaelDIV

1152ESAB.evirdrotalugerraeniLV5.2

SC1406G

2152BF.kcabdeeftuptuorotalugerraeniLV5.2

3151ESAB.evirdrotalugerraeniLV5.1

4151BF.kcabdeeftuptuorotalugerraeniLV5.1

51NE ebnacnipsiht,revird5041CSehthtiwdemaeT.hgiHsilangiscigolsihtnehwdelbanesiG6041CS.elbanE

61DGRWP htobdna,gnittesCADDIVehtfo%01±nihtiwsyatsdnasehcaorppatuptuoretrevnocniamehtnehW.dooGrewoP

71NIBL .redividrotsiserlanretxenahguorhtretrevnocehtotegatlovmuminimehttesotdesusinipsihT.tupniyrettabwoL

81RLSS ybdegrahcsi)pyt,Fp0021(roticapactrats-tfoslanretxeehtpu-rewoplamronagniruD.tratstfossrotalugerraeniL

91EROCSS si)pyt,Fp0081(roticapactrats-tfoslanretxeehtpu-rewoplamronagniruD.tratstfostuptuoEROCrellortnocniaM

02EROC.kcabdeeftuptuoretrevnocEROCniaM

.5041CSehtfonipYDRWPehtotdetcennoc

.denifednusilangissiht,tuokcolegatlov-rednugniruD.CCVotpudellupsilangissiht,etanimretsdoireptrats-tfos

.semiteromroenoelggotyamDGRWP,noitisnartpetSdeepSagniruD

.NEfosutatsehtfosseldragerOLVUnidlehsiG6041CSehtV522.1nahtsselsinipsihtottupniehtnehW

pu-pmarsihT.V5.2dnaV5.1,stuptuorotalugerraenilehtfoemitpu-pmarehttesotecruostnerrucAµ1lanretnina
CCVehtrowolsiNEnehwhctiwslanretninahguorhtdegrahcsidsiroticapacehT.xamsm6,sm2yllacipytsiemit
dlohserhtawolebspordegatlovnipehtlitnunigebtonlliwelcyctrats-tfoswenA.egatlovrednuerasnipNIBLro

hcaekcarttnerructrats-tfoserocehtdnatnerructrats-tfosrotalugerraenilehT(.)xamVm002(lacipytVm051fo

).%01±nihtiwotrehto

.V5.2dnaV5.1,stuptuorotalugerraenilehtfoemitpu-pmarehttesotecruostnerrucAµ1lanretninaybdegrahc

siNEnehwhctiwslanretninahguorhtdegrahcsidsiroticapacehT.xamsm6,sm3yllacipytsiemitpu-pmarsihT

spordegatlovnipehtlitnunigebtonlliwelcyctrats-tfoswenA.egatlovrednuerasnipNIBLroCCVehtrowol

trats-tfoserocehtdnatnerructrats-tfosrotalugerraenilehT(.)xamVm002(lacipytVm051fodlohserhtawoleb

).%01±nihtiwotrehtohcaekcarttnerruc

12CAD.tuptuogolanaotlatigidrellortnocniaM

22DNGdnuorG

32OC ehtsahcus,CIrevirdTEFSOMehtfotupniehtevirdotdesutuptuorellortnocrotalugerniaM.tuptuorotarapmoC

42CCV .egatlovylppusV0.5roV3.3gnitpeccafoelbapacsitupnisihT.tupniegatlovylppuS

52PMC.tupnirotarapmoceroC

62FERPMC.tupniecnereferrotarapmoceroC

72LC.tupnitimiltnerruC

82FERLC.tupniecnerefertimiltnerruC

ã 2000 Semtech Corp.

.5041CS

7

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POWER MANAGEMENT

SC1406G

VID vs. V

4DIV3DIV2DIV1DIV0DIVV

00000 00.2

00001 59.1

00010 09.1

Voltage

DAC

)stlov(

CAD

PIN Descriptions

00011 58.1

00100 08.1

00101 57.1

00110 07.1

00111 56.1

01000 06.1

01001 55.1

01010 05.1

01011 54.1

01100 04.1

01101 53.1

01110 03.1

01111 *UPCON

10000 572.1

10001 052.1

10010 522.1

10011 002.1

10100 571.1

10101 051.1

10110 521.1

10111 001.1

11000 570.1

11001 050.1

11010 520.1

11011 000.1

11100 579.0

11101 059.0

11110 529.0

11111 *UPCON

* output is disabled

8ã 2000 Semtech Corp.

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POWER MANAGEMENT

Functional Description

SUPPLY

The chip is optimized to operate from a 3.3V + 5% rail but is
also designed to work up to 6V maximum supply voltage.

UNDER VOLTAGE LOCK-OUT CIRCUIT

The under voltage lockout (UVLO) circuit consists of two com­parators, the low battery and low VCC (low supply voltage)
comparators. The output of the comparator, gated with the
Enable signal, turns on or off the internal bias, enables or
disables the CO output, and initiates or resets the soft start
timers.

POWER GOOD GENERATOR

If the chip is enabled but not in UVLO condition, and the core
voltage gets within +10% of the VID programmed value, then a
high level Power Good signal is generated on the PWRGD pin to
trigger the CPU power up sequence. If the chip is either disabled
or enabled in UVLO condition, then PWRGD stays low. This
condition is satisfied by the presence of an internal 200kW pull­down resistor connected from PWRGD to ground.

During soft start, PWRGD stays low independently from the
status of Vcore voltage.
PWRGD is high when all of the following conditions are true:

1 EN is high
2 Soft-start has completed
3 LBIN and VCC are above their under-voltage trip levels.

SC1406G

Current Limit Comparator

The current limit comparator monitors the core converter output
current and turns the high side switch off when the current
exceeds the upper current limit threshold, VHCL and re-enable
only if the load current drops below the lower current limit
threshold, VLCL. The current is sensed by monitoring the
voltage drop across the current sense resistor, R
series with the core converter main inductor (the same resistor
used for IMVP input signal generation). The thresholds have the
following relationships:

R

CLOH

CLSET

CLOH

CLSET

V

REF

V

REF

V

REF

V ••=3

HCL

V ••= 2

LCL

V •=

HYSCL

R

R

R
R

R

CLOH

CLSET

Core Converter Soft Start Timer

This circuit controls the ramp-up time of the core voltage in
order to reduce the initial inrush current on the core input
voltage (battery) rail. The soft-start circuit consists of an internal
current source, external soft-start timing capacitor, internal
discharge switch across the capacitor, and a comparator
monitoring the capacitor voltage.

, connected in

CS

BAND GAP REFERENCE

A better than +1% precision band-gap reference acts as the
internal reference voltage standard of the chip, which all critical
biasing voltages and currents are derived from. All references to
VREF in the equations to follow will assume V

= 1.7V.

REF

CORE CONVERTER CONTROLLER

Precision VID DAC Reference

The 5-bit digital to analog converter (DAC) serves as the pro­grammable reference source of the core comparator. Program­ming is accomplished by CMOS logic level VID code applied to
the DAC inputs. The VID code vs. the DAC output is shown in the
Output Voltage Table. The accuracy of the VID DAC is main­tained on the same level as the band gap reference. There is a
10µA pull-up current on each DAC input when EN is high.

Core Comparator

This is an ultra-fast hysteretic comparator with a typical propaga­tion delay of approximately 20ns at a 20mV overdrive.

This chip can be used in a standard hysteretic mode controller
configuration and in an IMVP hysteretic controller scheme.

Detailed instructions for the IMVP solution are found in the
PowerStep solution design procedure section of this
datasheet.

ã 2000 Semtech Corp.

LINEAR REGULATOR CONTROLLERS

1.5V Linear Regulator

This block is a low drop-out (LDO) linear-regulator controller,
which drives an external PNP bipolar transistor as a pass
element. The linear regulator is capable of delivering 500mA
steady-state DC current and can support transient currents of
greater than 1A, depending on pass element and output
capacitor selection.

2.5V Linear Regulator

This block is a low drop-out (LDO) linear regulator controller,
which drives an external PNP bipolar transistor as a pass
element. The LDO linear regulator is capable of delivering
100mA steady-state DC current and can support transient
currents greater than 200mA, depending on pass element and
output capacitor selection.

Linear Regulator Soft-Start

The soft-start circuit of the linear regulators is similar to that of
the core converter, and is used to control the ramp-up time of
the linear regulator output voltages. For maximum flexibility in
controlling the start-up sequence, the soft-start function of the
linear regulators is separated from that of the core converter.

9

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POWER MANAGEMENT

VOLTAGE CLAMP

This level translator converts an input voltage swing on the IO
rail, into a voltage swing on the CL or VCC rail depending on
where the open-drain output of the translator is tied to through
an external pull-up resistor. The level translator tracks the input
in phase, and switches in 5ns (typical) following an input
threshold intercept.

Evaluation Board Gerber Plots

Evaluation Board Bill of Materials

Applications Information

Power on/off Sequence

SC1406G

PowerStep Solution Design Procedure

Introduction:

The SC1406G (PowerStep for SpeedStep) and SC1405 Smart Driver power chip set provides a flexible, high performance
power solution to the requirements of Intel® mobile SpeedStep processors.

The SC1406G is a control IC that integrates a synchronous step-down controller for V
controllers for V
Smart Driver IC with programmable dead time and industry-leading speed.

The synchronous step-down converter is a hysteretic type, where the output voltage is compared against a VID programmable
reference (V
with the voltage at the reference, QH is off, QL is on and the output filter (L and C) discharge into load R. When the output voltage
hits the lower hysteresis point, the switches reverse state, and the RLC network charges up to the upper hysteresis value.

, and V

I/O

) with a resistor programmable offset, V

DAC

. In addition, the SC1406G also has a low-battery detector and a clamp circuit. The SC1405 is a

CLK

. The basic operation of the converter is very simple: Referring to Figure 1,

HYS

10ã 2000 Semtech Corp.

and two low-dropout regulator (LDO)

CORE

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POWER MANAGEMENT

Typical Application Schematic

C1

4.7uF/50V

C2

4.7uF/50V

C3

4.7uF/50V

D1

MBR0530

12

C4

1uF/0805

GND

CS-

+3.3V

+5Vcc

+V_IN

CS+

SC1406G

C24

NO-POP

C23

NO-POP

LRF3W_003_5%

1.5uH

BSTOVPS

14

BST

C21

150uF/4V

C19

150uF/4V

Q5

5
6
7
8

Q4

5
6
7
8

0.22uF/0805

C17

TG

12

13

TG

DRN

C22

150uF/4V

C20

150uF/4V

D

D

C18

1nF/0805

R17

11

DSPSDR

D2

4

IRF7811A

4

BG1

R11

27/1206

BGDELAYC

BG

PGND

8910

MBRS340

0

VCC

1 2

1
2
3

1
2
3

IRF7811A

C16

1uF/0805

BG2

+VccCPU_CORE

R15

6.65k

34

R23

CS

12

R13

R14

C14

1

270pF

10.0k

L_R

L1

PHASE

C28

D

IRF7811A

TG1

4

1uF/50V/1206

1
2
3

Q3

5
6
7
8

SC1405C

U2

OVPSENGNDCOSMOD

1234567

DELAYC

PRDY

C15

47pF

10uF/1206

C29

R12 0

R19

0/0805

R18

OH

CORE

R5

1.00k

R6 1.00k

R22

107k

OFFSET

BAL

CLOH

C6100pF

C7

R4 1.00k

100pF

C5

CL

27

CL

100pF

CMPREF

CMP

26

CMPREF

25

CMP

R3 1.00k

Vcc_1406

CLREF

28

CLREF

C8

0.22uF/0805

24

VCC

C31

1pF

R21

1.40k

CO

22

23

CO

GND

DAC

DAC

21

DAC

C9

20

CORE

1nF

C10 1.8nF

SSCORE

19

SSCORE

C11

SSLR

18

SSLR

R9

1.2nF

LBIN

17

LBIN

43k

R8

C12

20k

1nF

16

PWRGD

C13

1nF

SC1406G

U1

HYS

CLSET

VCOUT

VCIN

VCBYP

VID4

VID3

VID2

VID1

VID0

BASE25

FB25

BASE15

10

1

2

3

4

5

6

7

8

9

VID2

VID1

VID0

101112

BASE25

1

Q1

MMB T4403

2

150u/4V

C25

HYS

R1 127k

HYS

CLSET

CLSET

R2 86.6k

VID4

VID3

FB15 EN

13

14 15

BASE15

1

Q2

3

C26

MJD45H11

4 3

1uF

C27

150uF/4V

2_5V

1_5V

EN

V_GATE

ã 2000 Semtech Corp.

11

www.semtech.com

POWER MANAGEMENT

Figure 1 - Hysteretic Converter Basics

SC1406G

The major advantages of this approach are simplicity, inherent
stability (there are no reactive elements in the control circuit to
provide the phase shift required for classical stability problems),
and the fastest possible transient response. Any transient
which takes the voltage out of the hysteretic range forces the
converter immediately into the proper response. There are no
error voltages to slew, and no maximum or minimum duty cycle
limits to slow the transient response as in most other control
schemes. A significant benefit of the controller/driver architec­ture is that low-level analog control functions do not have to
coexist in an environment of thousands of volts and amps per
microsecond, reducing noise problems.

The SC1406G also supports the Intel Mobile Voltage Positioning
(IMVP) functions. In short, IMVP allows notebook designers to
reduce the output voltage with increasing load current. This has
two potential benefits:

· IMVP minimizes power by reducing the voltage under
heavy loads; processor power is proportional to V2, so
a 5% reduction in voltage results in a nearly 10%
reduction in power drawn by the processor.

· IMVP can reduce the number of capacitors required to
respond to transients by producing a larger allowable
transient; briefly, the no-load voltage is positioned
above nominal, so when a transient occurs, the load
has farther to drop before hitting the regulation limit.
The loaded voltage is allowed to remain below the
nominal so that when the load returns to zero, the
voltage can rise farther without reaching the transient
specification. Since the allowable transient voltages
are larger, less capacitance and higher ESR can
provide the required performance.

The SC1406G provides the precise voltage positioning required
by IMVP because it employs a current-sense resistor, multiplied
by a gain set by external resistors to very accurately set the
voltage as a function of load current.

R23 (RCS)

-

+

CMP

(pin 25 )

CMPREF

(pin 26 )

DAC

+ -

+

R6

(ROH)

-

+

R22

OFFSET)

(R

-

DAC

(pin 21 )

OUT

I

+

(RCORE)

-

­R21

(RDAC)

+

R5

V

OUT

Figure 2IMVP Example Illustration

The SC1406G implements IMVP, previously named DSPS
(dynamic set-point switching) in the following manner: Please
see Figure 2 above, and assume, for simplicity:

·R

OFFSET

is open

· The current into the CMP and CMPREF pins is zero.

Then, please note:

· The SC1406G regulates to the + side of the current
sense resistor, because that is where the CMP pin is
tied, and,

· No current flows through ROH, since the input current of
the comparator is ~0; V(ROH) = 0.

· The difference in voltage between CMP and CMPREF
is ~0V in order for the controller to be in regulation

In these conditions:

· At zero load, V

OUT

= V

and the voltage across the

DAC

current sense resistor is also zero;

· As the load increases, a voltage is developed across

12ã 2000 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

RCS; V(RCS) = I

· In order to keep the voltage between CMP and
CMPREF = 0V, V(RCS) appears across R

·V(RCS) + V(R
current flows through R

· I(R

CORE

) = I

· An equal, but opposite current must flow in R
voltage at CMPREF is reduced by I(R
V

= V

CMPREF

· Substituting the equations from above: V
I

* RCS * R

OUT

· Since V

·V

OUT

= V

OUT

DAC

OUT

) = 0, so V(R

CORE

* RCS / R

OUT

- I(R

DAC

/ R

DAC

= V

CMPREF

- I

* RCS (1 + R

OUT

* RCS.

) = -V(RCS); therefore, a

CORE

CORE

) * R

CORE

CORE

CORE

from V

DAC

to CMPREF.

OUT

CORE

 V(RCS), with a little algebra:

/ R

CORE

)

DAC

CORE

) l R

.

DAC

CMPREF

, so the

DAC

, so

= V

DAC

SC1406G

in having a larger transient response band to work with, thereby
providing a solution with the fewest output capacitors. On the
other hand, this also means that at low currents, the processor
will burn more power than without the offset, since CV2F still
applies, so battery life will be reduced.

The numbers in the sample calculations are taken from the Intel
Mobile Pentium III Processor in
BGA2 and Micro-PGA2 Packages Datasheet, Revision 1.0,
Document Number: 245302-002. Please consult the data for



your specific processor.

Hysteretic Converter Design Equations:

So, with the SC1406G, you get an accurate, linear droop greater
than the drop across the current sense resistor, without the
efficiency penalty of a large RCS, with a gain that is set by 1%
resistors! Adding R

shifts the position at zero current, as

OFFSET

described later.

For further information on IMVP, consult the Intel yellow-cover
document Intel® Mobile Voltage Positioning Voltage Regulation
Controller Application Note, Reference Number OR-2101.

The SC1405, a smart MOSFET driver, provides industry-leading
performance, driving a 3000pF load in under 15nS, typically.
Not only does the SC1405 offer built-in shoot-through protec­tion, but also has externally programmable dead time. In
addition, it provides other protection and performance features,
such as under-voltage lock-out (UVLO), programmable adaptive
over-voltage protection (OVP), and the SMOD pin, which may be
used to force the low-side gate drive LO during very light load
conditions to prevent negative circulating current in the inductor.
It comes in the small TSSOP-14 package.

DESIGN PROCEDURE:

Requirements:

The first step in designing any converter is in defining the
requirements, which can come from many sources. For the
SC1406G, you need to determine the minimum and maximum
input voltages, which are determined by the battery and AC
adapter characteristics, unless you plan to use an existing
regulated voltage, such as +5V. The processor determines other
requirements; they are:

· Maximum output voltage

· Minimum output voltage

· Maximum output current

· Minimum output current

· Maximum transient current

· Transient voltage requirements

One decision you need to make is whether a positive offset
voltage at zero current is desirable. Providing this offset results

ã 2000 Semtech Corp.

The Typical Application Schematic on Page 12 is a schematic of
the sample converter. Note that several of the resistors have
annotations along with reference designators and values.
These resistors set the basic functions and IMVP.

Referring to Figure 1, the basic equations for a hysteretic
converter are:

1)

V

HYS

−

V

()

INVOUT

d

⋅:=

ESR RCS+

⋅

()

F

L⋅

S

where,

2)

T

d

:= d

ON

T

+

()

ONTOFF

:=

V

V

OUT

IN

IIn equation 2), d is commonly referred to as the duty cycle.
The output voltage of the SC1406G is set digitally by the VID
(0:4) inputs, producing a voltage at the DAC output (pin 21)
accurate to better than 0.85%. The DAC voltage requirements
are given in the referenced Intel document and the SC1406G
datasheet. A similarly accurate fixed voltage internal bandgap
reference, Vref, has a nominal value of 1.70V, and is used for
setting voltage hysteresis and current limiting levels. In addition,
these references are used to provide active voltage positioning
 adjusting the output voltage as a function of load current
scaled by external resistors.

The output voltage of an IMVP converter has three
components:

· The programmed DAC voltage, V

· The load dependent droop V

· An optional positive offset, V

DAC

IMVP

OFFSET

In equation form,

3)

V

OUT

V

− V

DACVIMVP

+:=

OFFSET

The full equations for the IMVP converter are:

13

4)

V

⋅ R

()

V

DACROFFSETROH

:=

OUT

+

⋅ I

R

COREROFFSET

CORE

OUTRCS

⋅ R

⋅ R

⋅ R

DACROH

OFFSET

⋅+

CORERDAC

www.semtech.com

+

⋅−

()

POWER MANAGEMENT









R

V

RIPPLE2VHYS

5)

⋅

⋅

R

COREROFFSETROH

⋅ R

COREROFFSET

For customers familiar with the Intel IMVP application notes, the
above schematic has the IMVP resistors denoted using bold
lettering. To these resistors, Semtech has added one additional
resistor, R

, which is used to balance the impedance at the

BAL

current limit comparator for improved noise performance. A
cross-reference between the IMVP nomenclature and the
reference designator in the schematic above is provided in the
table below.

+

⋅

()

⋅+

DACROH

⋅:=

ESR

R

ESR

⋅

R

()

COREROFFSETROH

⋅ R

COREROFFSET

+

⋅+

DACROH

RCS⋅+

SC1406G

VNLR

⋅

8)

R

OFF

:=

R

+

OH

V

NL

V

DAC

To disable the no-load positive offset, leave R22 unpopulated.
Negative offsets are also possible  contact Semtech Applica­tions Engineering for details.

The current sense resistor, RCS (R23), R
R

(R5) set the IMVP gain. V

CORE

subtracted from the zero current output voltage.

V

DAC

DAC

1−

resistor (R21), and

DAC

is a function of current, and is

IMVP

erutalcnemoNletnIecnerefeRcitamehcS

rotangiseD

R

YSH

R

TESLC

R

EROC

R

HO

R

HOLC

R

CAD

R

TESFFO

R

SC

Without IMVP, the ROH (R6) and R

1R

2R

5R

6R

3R

12R

22R

32R

(R1) resistors set the

HYS

hysteresis voltage via the following equation:

R

6)

V

HYS

2V

⋅

REF

OH

⋅:=

R

HYS

The factor of 2 is due to the fact that half of the total hysteresis
occurs above the DC set point, half below, per Figure 1. Be­cause output ripple is fed back to CMPREF via the R5/R21
divider, the uncorrected output ripple is increased. We correct
for this later when selecting R1.
The no load offset in a non-IMVP converter is set by R6 and R22.
The zero load voltage is:

7)

V

NL

V

DAC

⋅:=



1

+

R

OH

R

OFFSET

As in the case of the hysteresis resistor, IMVP requires an
adjustment of the offset resistor value because at zero current,
the current drawn by the offset resistor divider is mirrored into
the R5/R21 divider, and increases the offset just as it increases
the ripple. R22 is calculated by solving equation 4) for I

OUT

= 0A.

9)

V

IMVPIOUTRCS



⋅ 1

⋅:=

+

DAC

R

CORE

R

Note that the SC1406G regulates to the + side of R23; as a
result, the minimum load dependent drop is Iout x R23. In
addition, the ripple voltage across R23 provides a minimum
input to the hysteretic comparator, so the SC1406G works well
with very low ESR capacitors.

The constant-current type of over current protection is provided
via R23, R
from I

CLMAX

10)

I

CLMIN

I

11)

CLMAX

(R3), and R

CLOH

to I

CLMIN

2V

3V

(R2). Current limiting will cycle

CLSET

until the load becomes less than I

R

⋅

⋅

REF

REF

CLOH

⋅:=

R

CLSETRCS

R

CLOH

⋅:=

R

CLSETRCS

⋅

⋅

CLMAX

:

Design Example  SC1406G:
We can use the above equations to design a mobile voltage

regulator circuit to meet the requirements of the Intel® 650/
500MHz SpeedStep processor using values from the proces­sor datasheet. This example is for reference only; your require­ments, parts availability, and newer processors may require
different component values. Contact Intel for the latest
processor requirements. Note that in the calculations, results
have been rounded to the nearest commonly available compo­nent value.

14ã 2000 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

Requirements:

The critical processor requirements are:

SC1406G

1. V

2. V

3. V

4. V

5. V

6. V

7. V

8. V

9. I

10. I

11. I

12. I

CC650MAXDC

CC650MINDC

CC650MAXTRANS

CC650MINTRANS

CC500MAXDC

CC500MINDC

CC500MAXTRANS

CC500MINTRANS

CC650MAX

CC650SG

CC500MAX

CC500SG

= 1.65V
= 1.485V

= 1.715V
= 1.485V

= 1.45V

= 1.25V

= 1.45V
= 1.25V

= 13.6A

= 2.2A

= 9.5A

= 1.7A

13. dICC/dt = 1400A/mS (at the processor. Local decoupling
reduces the requirement at the regulator.)

The system requirements are to minimize the number of
capacitors, and:

1. V

2. V

ADAPTERMAX

BATTMIN

= 21V

= 10V

Basic Calculations:

The 0.85% DAC output voltage accuracy accounts for an
uncertainty of 14mV at the 1.60V setting. In addition, 20mV of
resistive drop is expected in the power distribution from the
current sense resistor to the processor. A footnote in the
processor specification reads that the long-term voltage should
never exceed 1.65V. As a result, the nominal value of the no­load voltage [V (0)] should be set accordingly.

A.

V

NL

V

CC650MAXDCVTOL

−:= V

NL

1.636V=

The full-load voltage (V (fl)) is set similarly, including tolerance
and DC drop.

B.

V

FL

V

CC650MINDCVTOL

+ V

+:= V

DIST

FL

1.519V=

Figure 3 - Hysteretic Converter Response to a Positive
Transient

In a hysteretic converter with adaptive voltage positioning, like
the SC1406, two conditions determine if you meet the positive
transient requirements:

D.

V

IMVPICC650MAXICC650SG

V

E.

IMVP

()

deltaV C

≥

−

()

OUT

ESR⋅≥

The first condition is easy to see  if the ESR is too high, the
transient response will fail.

In the second condition, because the hysteretic converter
responds in < 100ns, the capacitor does not droop very far
before the inductor current starts ramping up. (This is not true
of control schemes where time constants in the error amplifier
cause delays.) Once the inductor current starts to rise, the
increasing DV of the capacitor is offset by reduced DV from the
ESR, so DV is constant. If the DV due to the charge taken from
the capacitor before the inductor current reaches the load
current (see the shaded area above) is less than V

, then the

IMVP

transient response will pass.

The regulator is to be designed with 40mV of output ripple, so
the effective IMVP voltage drop (V

V

C.

V

IMVPVNLVFL

−

−:= V

IMVP

RIPPLE

2

) is:

IMVP

0.098V=

Output Inductor and Capacitor Selection:

Output capacitance and ESR values are a function of transient
requirements and output inductor value. The following figure
illustrates the response of a hysteretic converter to a positive
transient:

ã 2000 Semtech Corp.

The maximum ESR requirement is:

V

ESR

F.

ESR

MAX

MAX

:=

I

()

CC650MAXICC650SG

8.579 10

IMVP

−

3−

×Ω=

For the second condition, we need to know the inductor value,
which is a function of the highest desired switching frequency.
The maximum frequency occurs at the highest input voltage. As
a reasonable compromise between efficiency and component
size, a maximum switching frequency of 300kHz is desired.

15

www.semtech.com

POWER MANAGEMENT





















Rearranging equation 1), we select the minimum inductor value.

G.

L

MINdMIN

V

()

⋅:=

−

INMAXVDAC

F

⋅

SVRIPPLE

ESR

⋅

()

+

MAXRCS

SC1406G

through 28) are two differential pairs connected to the current
sense resistor. In order to cancel out common-mode noise,
resistor pairs R3-R4 and R5-R6 should be equal. For the time
being, assume R3=R4=R5=R6=1kW. These values may be
adjusted later if required.

L

MIN

1.426 106−× H=

This value of inductance is required up to maximum load.
Inductors with a swinging choke characteristic, where the zero
current value of inductance is much less than the full load
current inductance can be used, as long as the above restriction
is met. A value of 1.5uH is used to allow tolerances. Then, the
worst-case (low input voltage) response time (the time for the
current to reach the new transient value) is:

H.

dT

:=

dT 1.936 10

L

⋅

()

MINICC650MAXICC650SG

V

INMINVDAC

× s=

−

−

6−

Add ~100ns for the SC1405/06 response. Since the shaded
area is triangular, the total charge taken out of the capacitor =
(DI ? Dt) / 2. Q = C ? DV = (DI ? Dt) / 2, therefore;

I

()

C

I.

MINP

CC650MAXICC650SG

:=

−

2V

()

dT 100 109−⋅ sec⋅+

⋅

⋅

IMVP

C 1.186 104−× F=

This condition applies only to the positive transient. For
negative load steps, the capacitance also has to be large
enough to absorb the energy in the inductance. Since:

C

J.

MINNLMIN

C

MINN

I

⋅:=

V

4.045 10

× F=

2

I

CC650MAX

CC650MAXTRANS

4−

−

CC650SG

2

2

2

V

−

FL

Using Panasonic SP-Caps, the EEFUE0E221R is 220uF at 2.5V
with 15mW ESR. Two are sufficient to meet ESR requirements,
but three are required to meet the capacitance requirement,
when tolerances are considered. The Sanyo POSCAP 4TPC150
is a 150uF capacitor with a maximum ESR specification of
45mW; six are required to meet the ESR requirement. The
resulting 900mF exceeds the capacitance requirement.

The current limit is a function of peak current and should be set
at about 125% of the peak to allow for some overshoot of
inductor current during transients. For L=1.5uH, and
F=300kHz:

I

K.

PEAKICC650MAX

I

PEAK

15.327A=

V

()

+:=

−

INMAXVDAC

⋅ FS⋅

2L

MIN

⋅

d

MIN

So, set the current limit at approximately 18.5A. Using equation

10):

L.

I

CLMAXIPEAK

M.

R

CLSET

R

CLSET

:=

Using equation 6) we calculate R

N.

R

R

DAC

DAC

()

:=

1.397 10

1.25⋅:= I

CLMAX

3V

⋅ R

⋅

REF

CLOH

R

⋅

CSICLMAX

8.873 10

V

IMVPICC650MAXRCS

×Ω=

4

×Ω=

DAC:

I

CC650MAXRCS

3

⋅

19.159A=

⋅−

R

⋅

CORE

The offset resistor, R22, is calculated from equation 8):

VNLR

⋅

5

V

DAC

DAC

1−

R

+

OH

R

OFF

R

OFF

:=



1.068 10

V

V

×Ω=

NL

DAC

O.

Equation 5) is used to calculate R1 by calculating a new value of
V

which accounts for the IMVP and offset dividers, and then

HYS

plugging the resulting value into equation 3).

+

R

()

OFFROH

⋅+

R

⋅ R

COREROFF

⋅ R

⋅

()

CORE

OFFROH

⋅−

DACROH

+

V

HYSVRIPPLERCOREROFF

P.



ESR R

⋅

CSRCORE

⋅ ROHR

⋅

()



⋅−

⋅:=

DAC

2 ESR⋅ R




Other Component Selection:

As a compromise between current sensing accuracy, efficiency,
and availability, a current sense resistor of 3mW is used. The
power dissipation is I2xR, or 555mW, so choose a 1W or larger
resistor for design margin.

V

Q.

R

HYS

R

HYS

HYS

0.027V=

V

2

⋅:=

1.281 105×Ω=

⋅

REFROH

V

HYS

The connections to CMP, CMPREF, CL, and CLREF (pins 25

16ã 2000 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1406G

The 55nS maximum delay from CO to the turn-off of the high­side driver will result in somewhat larger than calculated ripple,
especially at high line, high ESR, and low inductor values. For
the example, the increase in output ripple is about 6mV. R1 can
be adjusted for this, if desired.

Once the design is complete, rerun the calculations for 1.35V to
be sure the low voltage requirements are being met.

Several small capacitors are required for signal filtering. Use
SMT ceramic capacitors with an X7R or better temperature
coefficient. C0G is preferred.

C6 and C7, which filter the output voltage feedback, are sized
to provide filtering beyond the fifth harmonic of the fundamen­tal. The R5/R6 and C5/C6 components are balanced differen­tial pairs that effectively filter both common-mode and differen­tial noise sources that are troublesome in any high-performance
switching converter:

C6

R.

C6

MAX

MAX

:=

2 Π⋅ R

1.061 10

1

⋅ FS⋅ 5⋅

CORE

10−

× F=

Occasionally, due to layout-dependent noise on the CMP pin, the
value of C6 and C7 must be increased. If multiple high fre­quency pulses are seen on the CO pin (pin 23), then additional
capacitance is required. An additional capacitor is tied from the
CO pin to the CMPREF pin to provide AC hysteresis during
switching, and also helps to eliminate multiple pulses. Use a
1pF NPO capacitor for this purpose.

ments sized for the required currents: 2.5A peak @ 1.5V, and
150mA peak @ 2.5V.

PNP regulators are somewhat harder to stabilize than NPN
regulators. They require low source impedance,
with input decoupling <0.5 inches from the emitter of the pass
element; one capacitor suffices if the pass elements are close
enough together. The size of capacitor required varies according
to the impedance back to the 3.3V source. If the bulk
decoupling is within two inches, and the 3.3V is distributed
using a trace of at least 1 inch in width, then a 22mF capacitor
is sufficient. Otherwise, use at least 100mF. PNP regulators
generally require some ESR in the output capacitors for stability
purposes, but excess ESR can also create problems. The
allowable range of output capacitor and ESR values, based on
simulation and testing is shown in Figure 4 for the 1.5V output
and Figure 5 for the 2.5V output.

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W

L
F

( 

D
S

( 

D
&

( 
( 

(

      

6WDEOH5HJLRQ

(652KPV

Figure 4 - Recommended output C and ESR values (1.5V
output)

C5 is sized similarly, using R3 and R4. Since the current-limit
comparator does not affect the normal operation of the
converter, the frequency requirement is only to the second
harmonic, so as not to attenuate the fundamental.

C5

S.

C5

MAX

MAX

:=

2 Π⋅ R

⋅ FS⋅ 2⋅

()

1.326 10

× F=

1

+

CORERBAL

10−

The DAC output requires a similar 1nF, X7R or C0G capacitor
(C9) for high frequency noise filtering.

Powering the SC1406:

Vcc to the SC1406 can be either 5V, or 3.3V +/- 10%. 3.3V is
recommended for lower power consumption, and because the
UVLO function of the SC1406G provides protection for LDO
outputs. Filter Vcc with an RC network; R18 should be 10W,
C8, 0.1uF or greater.

Linear Regulator Design:

The SC1406G includes two linear regulator controllers, preset to

1.5V (V

ã 2000 Semtech Corp.

) and 2.5V (V

I/O

), and sized to drive PNP pass ele-

CLK

9 2XWSXW&DSDFLWRU6HOHFWL RQ

(
(



(

)




H

(

F
Q
D

W

L

(

F
D
S

(

D
&

(
(

         

6WDEOH5HJLRQ

(652KP V

Figure 5 - Recommended output C and ESR values (2.5V
output)

Pass Elements:

The last thing to consider is the pass elements themselves. The
drivers are sized to provide peak output current with a minimum
beta of 50. The MMBT4403 is one choice for the 2.5V pass
element, and the MJD45H11 for the 1.5V output, although
there are many acceptable choices. Do not use a Darlington
transistor; the high gain and extra poles create stability prob­lems, and defeat the beta current limiting scheme.

17

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POWER MANAGEMENT





Soft-Start Design:

The three outputs have two soft-start controls, with the two
linear regulators sharing one of them. The soft-start timing is
controlled with a capacitor charged by a nominal 1mA current
source. The soft-start period is the time to charge the soft-start
capacitors to Vref (though the voltage eventually terminates
near Vcc). The soft-start capacitor value is calculated for a 2ms
nominal time by:

I

⋅

T.

C

The soft-start period for V
the higher power and larger amount of output capacitance to
charge. Choosing 3ms results in C10=1800pF.

Low Battery Design:

CSStSS

:= C

SS

V

REF

1.176 109−× F=

SS

should be somewhat longer due to

CORE

SC1406G

VCIN (pin 4) must be referenced to the V
can be tied to either V

CLK

or V

, depending on the connection of

CC

the pull-up resistor. The clamp circuit has a dedicated refer­ence, VCBYP (pin 5) that requires a 1.5nF capacitor for proper
operation. The clamp circuit is not normally used in Pentium III
mobile computers. To disable this function, tie VCIN to analog
ground, with VCOUT and VCBYP open.

Other Features and Functions:

ENABLE is a 5V-safe CMOS input with an upper threshold
voltage at 70% of Vcc and a lower threshold of 0.8V. It can be
used in two different ways. One is to tie ENABLE to the PWRDY
pin of the SC1405; this will bring both the SC1405 and SC1406
up properly even if ENABLE can be active before the system 5V
supply is stable. Alternately, the ENABLE lines of both devices
can be tied together.

rail; VCOUT (pin 3)

IO

The SC1406G provides a low-battery indication with a hysteresis
current feature. That is, when the voltage at the LBIN pin is
above the reference, the input bias current is very low. Once the
threshold (a 1.225V bandgap) is reached and LBIN trips, a

0.6mA to 10mA current source must be overcome by the
battery and divider before the converter is allowed to come on
again. For the sample converter, assume V

= 9.5V. Ignoring

TRIP

bias currents, and assuming R8=20kW.

U.

V

LBTRIPVLBREF

R8 R9+

⋅:=

R8

In the example schematic, R9 = 43kW to accommodate
operation down to 4.5VDC. The rounded value gives a V

TRIPLO

of

9.62V. In order for LBIN to reset, the current source must be
overpowered, so:

V.

V

TRIPHIMAXVLBREF

V

TRIPHIMAX

W.

V

TRIPHIMIN

V

TRIPHIMIN

10.986V=

V

10.438V=

LBREF



R9 10 µA⋅

⋅+:=



R9 6 µA⋅

⋅+:=

+

+

V

LBREF

R8

V

LBREF

R8

The hysteresis current, in this case provides a voltage hysteresis
of 0.82V to 1.38V.

C10 provides noise filtering at the LBIN input. The 1nF value is
intended to provide attenuation at the lowest frequency load of
the battery. To disable this feature, tie LBIN (pin 17) to Vcc of
the SC1406 through a resistor (10kW is a good nominal value).

Clamp Design:

The clamp circuit is an open-collector uni-directional level shifter
capable of driving a 16mA load with a 5ns typical delay time.

CO is the clock output from the SC1406 to the SC1405.
POWERGOOD is LO (inactive) whenever any of the following
conditions is present:

1 Vcore is more than 10% higher or lower than its set-

point,

2 Either soft-start pin is lower than its threshold
3 Vcc is below the UVLO threshold
4 LBIN is active

POWERGOOD is HI (active) when none of the above is true, as
during normal operating conditions.

SC1405 Design Example:

The main function of SC1405 is to rapidly drive the power
MOSFETs on and off on using a break before make algorithm
to prevent cross conduction in the FETs.

FET selection:

The duty cycle (d) of the converter is a function of the input
voltage. In most applications, where the converter runs directly
from the battery, AC adapter, or even a regulated +5V source, d
is always going to be much less than 50%. The low-side (or
synchronous) FET, therefore, is conducting most of the time;
further, because the diode clamps the voltage across the low­side FET, it switches with virtually zero voltage across it. The
high-side (or control) FET conducts for a relatively small amount
of time, but has to switch the entire voltage. Therefore, the
control FET can have a relatively high R

, but needs to have

DS (ON)

low capacitive losses, and the synchronous FET needs to have a
low R

, and can have higher capacitance. To accomplish

DS (ON)

this, one can use a single FET type, with two or more in parallel
in the low-side, or one can use FET sets with individually
optimized devices.

18ã 2000 Semtech Corp.

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POWER MANAGEMENT

SC1406G

The current in the control FET is approximately:

I

X.

Q3RMSICC650MAXdMAX

I

Q3RMS

5.44A=

⋅:=

This current also should be used to size input capacitors; the
three input capacitors need a ripple current rating of 1.8A each,
to meet this requirement. The synchronous FET should be sized
for the full output current. Since the drive is derived from 5V,
both FETs should be sized using R

and current ratings for

DS(ON)

Vgs=4.5V.

Gate resistors are always recommended, and are required for
the control FET and for multiple synchronous FETs (one resistor
per gate). The value is dependent on FET selection and layout.
Generally, start with 2.2W to 4.7W for R11 -13 to evaluate the
circuit for EMI performance and Miller (gate to drain) capaci­tance effects. Increasing the high-side FET gate resistor value
will lessen both problems, but at the expense of higher switch­ing losses.

Miller capacitance in the low-side FET can cause it to turn ON as
the high-side FET turns on. It acts as a charge-pump capacitor to
couple the current from the fast dV/dt on the drain into the gate.
The voltage that appears on the low-side FET gate is:

C

DS

Y.

V

GZDRIVE

⋅

dV

⋅:=

dT

C

GS

If the voltage is sufficient to conduct significant current, then
efficiency is poor, and in extreme cases, the devices can be
damaged. For a given FET, Cgs is fixed, so one possible solution
is to slow down dV/dt; another is to reduce Zdrive. Reducing
Zdrive is primarily a function of layout and FET selection, since
the internal Rg of the FET can be on the order of 10W. The
SC1405 driver is typically 1W; so, given the short (10-20ns) dt,
Zdrive can be dominated by trace inductance. For long gate
drive traces, this inductance can resonate with the gate capaci­tance; in this case, a few ohms of gate resistance can damp the
circuit and actually reduce the peak gate voltage. Howeve r, the
best practice is to locate the SC1405 as near as possible to the
low-side FET and run wide traces to the gate.

Other potential solutions are to choose FETs with a low Cds/Cgs
ratio, low Rg, or add a capacitor from the low-side gate drive to
ground to externally lower the Cds/Cgs ratio.

Charge Pump Design:

The high-side drive circuit is tied to the source of the FET at DRN
(pin 12) and rides along the switching (phase) node rather than
being hard referenced to ground. The drive circuit makes use of
this switching action to pump charge from the 5V source up to
the BST pin (pin 14) to drive the control FET. When Q4 and Q5
are ON, C17 is charged through D1 to nearly 5V; when Q4 and
Q5 turn off, this voltage is available to turn Q3 on. C17 rides
along with the source, maintaining the drive level.

The charge pump capacitor needs to be low impedance, with a
value at least 100 times the gate capacitance it has to charge.
Ceramic capacitors are recommended. Schottky diodes are
recommended for D1. Wide traces are also required for the
charge pump traces.

In very low power situations, the low side drive may be disabled
via use of the SMOD pin (pin 5). This pin effectively prevents
reverse current from flowing in the inductor, so the inductor
current becomes discontinuous and the operating frequency is
reduced. The reduced losses related to circulating current and
faster switching need to be compared with the additional loss in
using the diode rather than the synchronous rectifier to deter­mine whether it improves low load efficiency in the system
application. In addition, the system must supply the SMOD
signal at the appropriate time.

Phase Node Design:

The phase node is one of the most critical nodes in the con­verter design, and must be treated with care. When neither Q3
nor Q4 is on, the inductor current flows through D2. D2 should
be a Schottky diode with a forward voltage at the peak inductor
current less than the forward voltage of the parasitic diode of
the FET, to keep it from conducting, and improving efficiency.
Holding the gate of Q4 low until the phase node reaches 1V for
a high to low transition provides shoot-through protection. For a
low to high transition, the high-side driver is held off by an
internal 20ns delay. This period may be extended using C15,
connected to pin 6, to provide an additional delay of approxi­mately 1ns/pF. Size C15 to provide dead time for the worst­case drive conditions given the choice of control FET and gate
drive resistor.

The phase node voltage at DRN (pin 12) must not go below -2V;
very short (<25nS) pulses to -5V can be tolerated. Excessive
negative transients may result in double pulsing of the gate
drive, and in severe cases, device damage.

The phase node, since it switches at very high rates of speed, is
generally the largest source of common-mode noise in the
converter circuit. For this reason, it should be kept to a
minimum size consistent with its connectivity and current
carrying requirements. Occasionally, a snubber network (R17/
C18) is required to dampen parasitic ringing on the phase node
caused by parasitic inductance and capacitance excited by the
switching. One approach to snubber design is to record the
frequency and amplitude of ringing before the snubber, then add
pure capacitance until the frequency is reduced, then adding
resistance until the required damping is achieved.

ã 2000 Semtech Corp.

19

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POWER MANAGEMENT

Additional Functions:

The SC1405 also provides two voltage protection functions:

1 A drive voltage under voltage lockout (UVLO) with

output on PRDY, pin 7

2 An output over voltage protection (OVP) using input

OVPS, pin 1

UVLO shuts off the drivers when Vcc is less than 4.4Vdc; in this
condition, PRDY is driven low, and may be used to disable the
SC1406G as well. OVP is implemented using a resistive divider
to a 1.20V +/- 55mV reference. In order to keep the voltage
within the 2.1V processor specification:

Z.

V

REFMAXVOVPMAX

With R14=10kW, R15=6.65kW. Solving this equation for the
minimum trip voltage yields V
~250mV from the zero load voltage, a noise filter capacitor
(C14) is required, and should be chosen that the R14||C15
time constant is longer than the minimum switching period. The
OVP input has very fast response, so C14 needs to be located
directly at the pin, and the length of the OVP trace should be
minimized.. Ground pin 1 to disable OVP.

A logic output signal DPSPDR (pin11) mirrors BG when SMOD is
HI; it is HI when SMOD is LO.

Additional notes:

Since the SC1405 puts out large, sharp pulses, decoupling and
grounding are very important. The Vcc decoupling capacitor,
C16 should be at least 1uF ceramic, and located right at the
chip with the + terminal connected directly to Vcc (pin 8) and
the  terminal connected directly to PGND (pin 10). Note that
the SC1405 connects to both the power and analog grounds.
Grounding is described in the following section.

LAYOUT GUIDELINES:

As with any high-speed switching converter, the area of high
current loops needs to be minimized. The two major loops are
(referring to Figure 2):

R14

⋅:=

R14 R15+

=1.906V. Since this is only

OVPMIN

SC1406G

In addition:

1. Separate the noisy and quiet areas of the circuit.
A significant benefit of the controller/driver
architecture is that the control circuit does not
have to coexist in an environment of thousands of
volts and amps per microsecond.

2. Place the SC1405 so as to reduce the trace
length to the synchronous rectifier(s).

3. Place the current-sense resistor as close as
possible to the output capacitors; inductance
from the voltage sense point to ground results in
extra output ripple.

4. Connections and routing of the differential pairs
are critical. The first three items are essential; the
others are suggested for additional guidance.

a. Run the traces as close together as

possible.

b. Use minimum width traces to reduce

capacitive coupling.

c. Run a single pair as far as possible; split

them at the resistors as close as
possible to the SC1406; put the filter
capacitors as close as possible to the
device.

d. In noisy environments, use a guard ring

(ground trace around the differential
pair). Tie the ring to ground every 2-4
cm.

e. Run the traces in a quiet layer; use the

minimum number of vias.

5. Minimize the area of the switching node and any
other high-speed nodes.

6. Layout the protection circuitry (OVP, LBIN) keeping
noise in mind:

a. Minimize the length and area of traces

to the pins.

b. Put the noise filter capacitor next to the

pin.

1. From the input capacitors, through Q3, L1, and
C19  C24, returning through PGND;

2. From Q4/Q5 through L1 and C19  C24, returning
through PGND.

Secondary loops are in the gate drive circuitry:

1. From C17 through the SC1405, R13 and Q3,
returning through the phase node.

2. From C16 through the SC1405, R11/R12 and
Q4/Q5, returning through PGND.

20ã 2000 Semtech Corp.

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POWER MANAGEMENT

Sample Layout

The following shows the layout of the SpeedStep VRM.
Additional data, including electronic format schematic and
layout files, as well as experienced layout assistance is avail­able from your local Semtech field applications engineer.

SC1406G

Figure 9 - PowerStep VRM - Inner Layer

Figure 6 - PowerStep VRM  Top Layer

Figure 7 - PowerStep VRM - Bottom Layer

Figure 10 - PowerStep VRM - Top Silkscreen

Figure 11 - PowerStep VRM - Bottom Silkscreen

Figure 8 - PowerStep VRM - Ground Layer

ã 2000 Semtech Corp.

21

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SC1406G

POWER MANAGEMENT

Bill of Materials

Critical Component Recommendations:

A list of components used successfully in this and/or similar circuits appears below. Listing does not necessarily indicate
available supply.

Table 2 - Critical Components Supplies

tnenopmoCsrerutcafunaMrebmuNtraProseireS

rotcudnItuptuOcinosanaP

sroticapaCtuptuOtenreK

oynaS

STEFSOMrewoPreifitceRlanoitanretnI

rotsiseResneStnerruCCRI

Table 3 - Critical Supplier Contacts

YNAPMOCTCATNOC

reifitceRlanoitanretnI/ofni-tcudorp/moc.fri.www//:ptth:beW

CRI/moc.ttcri.www//:ptth:beW

tenreK/moc.tenrek.www//:ptth:beW

cinosanaP/gce/cip/moc.cinosanap.www//:ptth:beW

oynaS/moc.oedivoynas.www//:ptth:beW

adimuS

cinosanaP

sinociliS/yahsiV

cinosanaP

elaD/yahsiV

0008-627)013(:enohP

6734-274)888(:enohP

0036-369)468(:enohP

2257-843)102(:enohP

5386-166)916(:enohP

1S-CCP,6N-CCPseireS

)H(431PEDCseireS

025TseireS,paCOK

BCseireS,paCPS

xPTseireS,PACSOP

A1187FRI,A9087FRI

4884iS,4784iS

0102FRL,W3FRLseireS

TSW1-MJREseireS

RSW,LSWseireS

adimuS/moc.adimus.www//:ptth:beW

6660-659)748(:enohP

KDT lmth.stnenopmoc/stnenopmoc/moc.kdt.tnenopmoc.www//:ptth:beW

3734-093)748(:enohP

elaD/yahsiVelad/sdnarb/moc.yahsiv.www//:ptth:beW

1313-465)204(:enohP

xinociliS/yahsiV /xinocilis/sdnarb/moc.yahsiv.www//:ptth:beW

5655-455)008(:enohP

CONCLUSION:

The SC1405/06G PowerStep chip set provides a complete, optimized solution for the power requirements of Intels SpeedStep
processors. Evaluation kits and application notes are available. For further information, please see the Semtech website
(www.semtech.com), or contact your local Semtech field applications engineer.

22ã 2000 Semtech Corp.

www.semtech.com

POWER MANAGEMENT

SC1406G

Figure 12 - SpeedStep Transition, 1.60V to 1.35V

Figure 14 - 0A to 12A Transient Load Response Figure 15 - 12A to 0A Transient Load Response

Figure 13 - SpeedStep Transition, 1.35V to 1.60V

ã 2000 Semtech Corp.

23

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POWER MANAGEMENT

SC1406G

Output Ripple Voltage @ VIN = 6.0V

Figure 16 - V

= 1.6V, I

OUT

= 2.0A Figure 17 - V

OUT

Output Ripple Voltage @ VIN = 18V

OUT

= 1.6V, I

= 12.0A

OUT

Figure 18 - V

= 1.6V, I

OUT

= 2.0A Figure 19 - V

OUT

24ã 2000 Semtech Corp.

= 1.6V, I

OUT

= 12.0A

OUT

www.semtech.com

POWER MANAGEMENT

Load Regulation & Efficiency

89.50%

Efficiency vs. Vout

SC1406G

Line Regulation & Efficiency

Vout = 1 .60V Vout = 1.35V

1.600

89.00%

88.50%

88.00%

87.50%

87.00%

86.50%

1.100 1.300 1.500 1.700 1.900

Vout, V

1.550

1.500

1.450

1.400

1.350

1.300

5.000 7.000 9. 000 1 1. 000 1 3.000 15.000 1 7.000 1 9.000 21 .000 23.000

Vin, V

Figure 20 - VIN = 12V, VO = 1.6V Figure 21 - VOUT = 1.6V, IOUT = 8.0A

Efficiency vs Output Voltage Efficiency vs Input Voltage

89.50%

Efficiency vs. Vout

89.00%

90.00%

89.00%

Vout=1. 35V Vout=1 .6V

88.50%

88.00%

87.50%

87.00%

86.50%

1.100 1.300 1.500 1.700 1.900

Vout, V

88.00%

87.00%

86.00%

85.00%

84.00%

4.000 6.000 8.000 10.00 0 1 2.000 1 4.000 1 6.000 1 8.000 20.000 22.000

Vin, V

Figure 22 - VIN = 12V, IOUT = 8.0A Figure 23 - VOUT = 1.3V, IOUT = 8.0A

ã 2000 Semtech Corp.

25

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POWER MANAGEMENT

Supply Current vs VIN, Temperature @ UVLO mode

400

SC1406G

Supply Current vs VIN. Temperature @ Operating mode

8

350

300

250

Current, uA

200

150

3456

Voltage, V

100’C
20’C
0’C

7

6

5

4

Current, mA

3

2

1

3456

Figure 24 Figure 25

DAC Output vs Temperature

1.8

1.6

1.4

1.2

DAC, V

1.0

0.8

Vout @ 1. 67 5V
Vout @ 1. 35 0V
Vout @ 0. 90 0V

Power Good Threshold vs Temperature

120

110

100

Volts

90

Operating @100’C
Operating @ 20’C
Operating @ 0’C

Voltage, V

VhCore
VLCore

0.6
0 20406080100

Temperature, ’C

80

Figure 26 Figure 27

Hysteresis Setting Current vs Temperature

120

100

80

60

Current, uA

40

20

0

020406080100

Temp erature, ’C

Figure 28

17k(+10mV)
17k(-10mV)
170k(+10mV)
170k(-10mV)

Current Limit Threshold vs Temperature

300

250

200

150

Current, uA

100

50

0

Figure 29

0 20 40 60 80 100

Tem perature ’C

42.5k +10mV

42.5k -10mV
20k +10mV
20k -10mV

020406080100

Temperaure, ’C

26ã 2000 Semtech Corp.

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POWER MANAGEMENT

Core Soft-Start Current vs Temperature LDOs Soft-Start Current vs Temperature

SC1406G

2.5

2

1.5

Current

1

0.5

0

0 20406080100

Temperature, ’C

Figure 30

DisCharge, mA
Charge, uA

2.5

2

1.5

Current

1

0.5

0

0 20406080100

Temperature, ’C

Figure 31

Low Battery Monitor Threshold vs Temperature LDOs Drive Currents vs Temperature

2.0

1.5

1.0

Voltage, V

0.5

0.0
0 20406080100

Temperature, ’C

Figure 32

80

70
60
50

40

Current, mA

30
20
10

0

0 20406080100

Temperature ’C

Figure 33

DisCharge, mA
Charge, uA

1.5V

2.5V

101.0%

100.5%

100.0%

Regulation, %

99.5%

99.0%

0.0 0.5 1.0 1.5 2.0

Figure 34

ã 2000 Semtech Corp.

Current, A

CLK LDO Load Regulation-Normalized for 100mAI/O LDO Load Regulation-Normalized for 1A

Regulation, %

Figure 35

27

103%
102%
101%

100%

99%
98%

97%
96%
95%

0 50 100 150 200

Current, mA

www.semtech.com

POWER MANAGEMENT

Outline Drawing - TSSOP-28

SC1406G

Contact Information

ECN 00-1128

Semtech Corporation

Power Management Products Division

652 Mitchell Rd., Newbury Park, CA 91320

Phone: [phone] FAX [phone]

28ã 2000 Semtech Corp.

www.semtech.com