Datasheet SC1405TS.TR Datasheet (Semtech Corporation)

HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER

SC1405

August 31, 2000

TEL:[phone] FAX:[phone] WEB:http://www.semtech.com

DESCRIPTION

The SC1405 is a Dual-MOSFET Driver with an internal
Overlap Protection Circuit to prevent shoot-through
from V
chronous MOSFET’s. Each driver is capable of driving
a 3000pF load in 20ns rise/fall time and has ULTRA­FAST propagation delay from input transition to the
gate of the power FET’s. The Overlap Protection circuit
ensures that the second FET does not turn on until the
top FET source has reached a voltage low enough to
prevent shoot-through. The delay between the bottom
gate going low to the top gate transitioning to high is
externally programmable via a capacitor for optimal
reduction of switching losses at the operating fre­quency. The bottom FET may be disabled at light loads
by keeping S_MOD low to trigger asynchronous opera­tion, thus saving the bottom FET’s gate drive current
and inductor ripple current. An internal voltage refer­ence allows threshold adjustment for an Output Over­Voltage protection circuitry, independent of the PWM
feedback loop. Under-Voltage-Lock-Out circuit is in­cluded to guarantee that both driver outputs are low
when the 5V logic level is less than or equal to 4.4V
(typ) at supply ramp up (4.35V at supply ramp down). A
CMOS output provides status indication of the 5V sup­ply. A low enable input places the IC in stand-by mode
thereby reducing supply current to less than 10µA.
SC1405 is offered in a high pitch (.025” lead spacing)
TSSOP package.

to GND in the main switching and syn-

IN

FEATURES

•= Fast rise and fall times (20ns typical with 3000pf

load)

•= 20ns max. Propagation delay (BG going low)

•= Adaptive/programmable shoot-through protection

•= Wide input voltage range (4.5-25V)

•= Programmable delay between MOSFET’s

•= Power saving asynchronous mode control

•= Output overvoltage protection/overtemp shutdown

•= Under-Voltage lock-out and power ready signal

•= Less than 10µA stand-by current (EN=low)

•= Power ready output signal

APPLICATIONS

•= High Density/Fast transient power supplies

•= Motor Drives/Class-D amps

•= High frequency (to 1.2 MHz) operation allows use

of small inductors and low cost caps in place of

electrolytics

•= Portable computers

ORDERING INFORMATION

DEVICE

SC1405TS.TR TSSOP-14 0 - 125°C

Note:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.

(1)

PACKAGE TEMP. RANGE (TJ)

Top View

(14-Pin TSSOP)

BLOCK DIAGRAMPIN CONFIGURATION

1

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

HIGH SPEED SYNCHRONOUS POWER

SC1405

MOSFET SMART DRIVER

August 31, 2000

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Conditions Maximum Units

Supply Voltage V

V

CC

BST to PGND VMAX
BST to DRN VMAX
DRN to PGND VMAX
OVP_S to PGND VMAX

MAX5V

BST-PGND

BST-DRN

DRN-PGN

OVP_S-PGND

Input pin CO -0.3 to 7.3 V
Continuous Power Dissipation Pd Tamb = 25°C, T

Tcase = 25°C, T

Thermal Resistance Junction to Case
Thermal Resistance Junction to Ambient
Operating Temperature Range
Storage Temperature Range

Lead Temperature (Soldering) 10 sec

T

θ

T

JC

θ

JA

T

STG

LEAD

J

= 125°C

J

= 125°C

J

7V

30 V

7V
25 V
10 V

0.66

W

2.56
40 °C/W

150 °C/W

0 to +125 °C

-65 to +150 °C
300 °C

NOTE:

(1) Specification refers to application circuit in Figure 1.

ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS)

Unless specified: -0 < θJ < 125°C; VCC = 5V; 4V < V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY

Supply Voltage V

CC

Quiescent Current Iq_stby EN = 0V 10 µA
Quiescent Current, operating Iq_op V

PRDY

High Level Output Voltage V
Low Level Output Voltage V

OH

OL

V

V

CC

DSPS_DR

High Level Output Voltage V
Low Level Output Voltage V

OH

OL

VCC = 4.6V, Cload = 100pF 4.15 V
VCC = 4.6V, Cload = 100pF 0.05 V

UNDER-VOLTAGE LOCKOUT

< 26V

BST

V

CC

= 5V,CO=0V 1 ma

CC

= 4.6V, lload = 10mA 4.5 4.55 V

CC

< UVLO threshold, lload =

4.15 5 6.0 V

0.1 0.2 V

10µA

Start Threshold V

START

Hysteresis Vhys
Logic Active Threshold V

ACT

UVLO

EN is low 1.5 V

4.2 4.4 4.6 V

0.05 V

2

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

HIGH SPEED SYNCHRONOUS POWER

SC1405

MOSFET SMART DRIVER

August 31, 2000

ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS) Cont.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
OVERVOLTAGE PROTECTION

Trip Th reshold V

TRIP

Hysteresis Vhys

S_MOD

High Level Input Voltage V
Low Level Input Voltage V

ENABLE

High Level Input Voltage V
Low Level Input Voltage V

CO

High Level Input Voltage V
Low Level Input Voltage V

THERMAL SHUTDOWN

Over Temperature Trip Point T
Hysteresis T

OTP

HYST

HIGH-SIDE DRIVER

Peak Output Current I

PKH

Output Resistance Rsrc

Rsink

IH

IL

IH

IL

IH

IL

OVP

TG

TG

duty cycle < 2%, tpw < 100µs,

= 125°C, V

T

J

= 4.0V (src)+V

V

TG

or VTG = 0.5V (sink)+V

BST

- V

DRN

= 4.5V,

DRN

DRN

1.145 1.2 1.255 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

2.0 V

0.8 V

165 °C

10 °C

1.5 A

1.4

1.4

Ω

Ω

LOW-SIDE DRIVER

Peak Output Current I

PKL

Output Resistance Rsrc

Rsink

BG

BG

duty cycle < 2%, tpw < 100µs,

= 125°C

T

J

= 4.6V, VBG = 4V (src),

V

V_5

or V

LOWDR

= 0.5V (sink)

2A
2

2

Ω
Ω

3

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

HIGH SPEED SYNCHRONOUS POWER

SC1405

MOSFET SMART DRIVER

August 31, 2000

ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS) Cont.

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

AC OPERATING SPECIFICATIONS

HIGH-SIDE DRIVER

rise time tr

fall time tf

propagation delay time,

tpdh

TG going high
propagation delay time,

tpdl

TG going low

LOW-SIDE DRIVER

rise time tr

fall time tr

propagation delay time

tpdh

BG going high
progagation delay time

tpdl

BG going low

UNDER-VOLTAGE LOCKOUT

V_5 ramping up tpdh
V_5 ramping down tpdl

PRDY

, CI = 3nF, V

TG

TG

TG

TG

BG

BG

BGHI

BG

UVLO

UVLO

CI = 3nF, V

CI = 3nF, V

CI = 3nF, V

CI = 3nF, V

CI = 3nF, V

CI = 3nF, V

CI = 3nF, V

BST

BST

BST

- V

- V

- V

= 4.6V, 16

DRN

= 4.6V, 17

DRN

= 4.6V,

DRN

35

25

27

56

ns

ns

ns

C-delay=0

- V

BST

DRN <

= 4.6V, 25

DRN

= 4.6V, 20

V_5

= 4.6V, 18

V_5

= 4.6V,

V_5

1V

= 4.6V, 12

V_5

45

40

32

29

72

20

ns

ns

ns

ns

ns

EN is High 10 us
EN is High 10 us

EN is transitioning from low to
high

EN is transitioning from high to
low

tpdhPRDY V_5 >

measured from EN >

tpdh

UVLO

V_5 > UVLO threshold. Delay

measured from EN <

UVLO threshold, Delay

2.0V to

PRDY >

3.5V

0.8V tp

PRDY <

10% of V_5

10 µs

500 µs

DSPS_DR

rise/fall time tr

propagation delay,
DSPS_DR going high

propagation delay
DSPS_DR goes low

DSPS_DR,

tf

DSPS_DR

tpdh

tpdl

DSPS_DR

DSPS_DR

CI = 100pf, V_5 = 4.6V, 20 ns

S_MOD goes high and

BG goes high or S_MOD goes low

S_MOD goes high and BG goes

low

10 ns

10 ns

OVERVOLTAGE PROTECTION

propagation delay
OVP_S going high

tpdh

OVP_S

V_5 = 4.6V, TJ = 125°C, OVP_S >

1.2V to BG > 90% of V_5

1µs

Note:
(1) This device is ESD sensitive. Use of standard ESD handling precautions is required.

4

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

HIGH SPEED SYNCHRONOUS POWER

SC1405

MOSFET SMART DRIVER

August 31, 2000

PIN DESCRIPTION

Pin # Pin Name Pin Function

1 OVP_S Overvoltage protection sense. External scaling resistors required to set

protection threshold.

2 EN When high, this pin enables the internal circuitry of the device. When

low, TG, BG and PRDY are forced low and the supply current (5V) is

less than 10µA.
3 GND Logic GND.
4 CO TTL-level input signal to the MOSFET drivers.
5 S_MOD When low, this signal forces BG to be low. When high, BG is not a

function of this signal.
6 DELAY_C Sets the additional propagation delay for BG going low to TG going high.

Total propagation delay= 20ns + 1ns/pF.
7 PRDY This pin indicates the status of 5V. When 5V is less than 4.4V(typ) this

output is driven low. When 5V is greater than or equals to 4.4V(typ) this

output is driven to 5V level. This output has a 10mA drive capability and

10µA sink capability.
8V

9 BG Output drive for the synchronous MOSFET.

10 PGND Power ground. Connect to the synchronous FET power ground.
11 DSPS_DR Dynamic Set Point Switch Drive. TTL level output signal. When S_MOD

12 DRN This pin connects to the junction of the switching and synchronous

13 TG Output gate drive for the switching (high-side) MOSFET.
14 BST Bootstrap pin. A capacitor is connected between BST and DRN pins to

NOTE:

(1) All logic level inputs and outputs are open collector TTL compatible.

CC

+5V supply. A .22-1µF ceramic capacitor should be connected from 5V

to PGND very close to this pin.

is high, this pin follows the BG driver pin voltage.

MOSFET’s. This pin can be subjected to a -2V minimum relative to

PGND without affecting operation.

develop the floating bootstrap voltage for the high-side MOSFET. The

capacitor value is typically between 0.1µF and 1µF (ceramic).

PIN CONFIGURATION

5

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

August 31, 2000

HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER

SC1405

APPLICATION CIRCUIT

INPUT POWER

+5V

10uF,6.3V

P_READY

<<

PWM IN

>>

(20KHz-1MHz)

DSPS_DR

<<

<<< Output Feedback to PWM
Controller

+

.1uF

47pF

Typical Distributed Power Supply

+ ++

D1

1N5819

8

Vcc

3

GND

7

PRDY

2

EN

4

CO

6

DELAY_C

1

OVP_S

5 10

S_MOD PGND

BST

TG

DRN

BG

DSPS_DR

SC1405

14
13
12
9
11

.22uF

2.2

2.2

Over-Voltage Sense

MTB75N03
75A,30V

MTB75N03
75A,30V

++ +

TIMING DIAGRAM

Figure 1.

Figure 2.

6

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER

August 31, 2000

APPLICATION EVALUATION BOARD SCHEMATIC

SC1405/SC1144 Evaluation Board.
4-Phase synchronous, Freq.=1MHz

SC1405

22u,10V

C20

22u,10V

C21

22u,10V

BST

Vcc

C24

22u,10V

C25

22u,10V

C30

22u,10V

C29

22u,10V

C33

22u,10V

C34

22u,10V

C38

1000uf,6.3

VOUT

870nh

L3

D6

30BQ015

Q4

FDB7030

0

0

R12

10u,16V

.1u

C22

.1u

4.7

R29

13

91112

TG

BG

DRN

CO

GND

EN

OVP_S

DELAY_C

PRDY

432

1146

7

DSPS_DR

C28

C27

S_MOD PGND

5 10

Q5

FDP6035

R140R16

SC1405

870nh

L5

D7

30BQ015

Q6

FDP6035

0

.1u

BST

U4

Vcc

8

10u,16V

C36

.1u

C35

C31

4.7

R30

13

91112

TG

BG

DRN

CO

GND

EN

OVP_S

DELAY_C

PRDY

432

1146

7

C39

870nh

L7

D8

Q7

Q8

FDP6035

0

R23

R17

.1u C40

BST

DSPS_DR

U5

SC1405

Vcc

S_MOD PGND

8

5 10

1000uf,6.3

C51

30BQ015

FDB7030

0

4.7

R31

13

91112

TG

BG

DRN

DSPS_DR

SC1405

CO

GND

EN

OVP_S

DELAY_C

PRDY

7

S_MOD PGND

432

1146

5 10

*

TBD

R26

R26 AND R27 SET THE OVERVOLTAGE TRIP

POINT. C48 SETS THE TIME CONSTANT.

R27=0,R26=OPEN to disable OVP_S.

.01

C48

TBD

R27

*

22u,10V

C17

22u,10V

C15

22u,10V

C10

22u,10V

C6

22u,10V

C1

870nh

L1

D5

30BQ015

Q2

Q1

FDP6035

R2

.1u

C49

.1u C50
D4

SS12

D3

SS12

D2

SS12

D1

SS12

.1uC5
.1uC4
.1uC3
.1uC2

U1

8

BST

Vcc

FDB7030

0

0

R3

C9

.1u

4.7

R28

13

91112

TG

DRN

CO

GND

EN

PRDY

432

7

Q3

FDP6035

R10

10u,16V

C19

.1u

C18

BG

DSPS_DR

U3

SC1405

OVP_S

DELAY_C

S_MOD PGND

1146

8

5 10

NC

11Thursday, June 10, 1999

PLATFORM SYNCHRONOUS 40A CONVERTER

B

Title

Size Document Number Rev

Date: Sheet of

EN

47pf

47pf

.1uC14.1uC23.1uC32.1uC41

C16

47pf

C26

47pf

C37

C44

10

R21

.1u

C47

C43

.022

300k

R24

C42

R25

2.2

.001

C46

.01

C45

ENSYN

BY JUMPERING JMP1, ALL SC1405'S ARE ENABLED AND

DISABLED TOGETHER WITH SC1144. THREE OF THE SC1405'S

CAN BE DIRECTLY CONTROLLED BY SEPARATING THE TWO ENABLES.

Long PCB Trace

10K

+5V power

+12V

0

R32

2.2k

3k

R15

22

R9

22

22

23

24

Drv3

Outv

Divsel

5v

10uf,6.3v

C13

C12

C11

6

231

R7

10K

R6

10K

R5

10K

R4

10K

8

S1

9

INPUT

SMOD

R33

10

R1

C8

.1uC7

330UF,16V

1u,16V

1u,16V

12345

J1

22

R8

Drv1

Clksel

R1122R13

19

20

21

12V

Drv0

Rref

Extclk

4

EN

1234567

16151413121110

EN

16

17

18

GND

Drv2

Vid0

Vout/Clk switch

Enable

Vid1

Vid2

756

9

8

JMP1

VOUT

FBG

Vid3

OC+ FB

Vid4 Bgout

11 14

10 15

R20

.01u

13

Comp

SC1144-SOIC

U2

OC-

12

15K

R22

0

R19

3.92K

R18

Figure 3

7

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

HIGH SPEED SYNCHRONOUS POWER

SC1405

MOSFET SMART DRIVER

August 31, 2000

BILL OF MATERIAL
Item Qty Reference Value Manufacturer

1 14 C1,C6,C10,C15,C17,C20,C21,C24,C25,C29,C30,C33,C34,C38 22u, 10V Murata

(GRM235Y5V226Z010)

2 19 C2,C3,C4,C5,C7,C9,C14,C18,C22,C23,C27,C31,C32,C35,C40,

C41,C47,C49,C50
3 1 C8 10uF, 6.3V any
4 2 C11,C12 1uF, 16V any
5 1 C13 330uf, 16V Sanyo
6 4 C16,C26,C37,C44 44pF any
7 3 C19,C28,C36 10uF, 16V any
8 2 C39,C51 1000uF, 6.3V any
9 3 C42,C45,C46 .01uf any

10 1 C43 .022 Avx, any
11 1 C46 .001 Avx, any
12 4 D1,D2,D3,D4 SS12 General Instruments
13 4 D5,D6,D7,D8 30BQ015 Int. Rectifier

14 2 JMP1,JMP2 Jumper
15 1 J1 Input
16 4 L1,L3,L5,L7 .87uh Falco, P/N: TO2509

17 5 Q1,Q3,Q5,Q6,Q7 FDP6035 Fairchild Semi.

.1uF any

[phone]

[phone]

[phone]

IR7811 Int. Rectifier

18 3 Q2,Q4,Q8 FDB7030 Fairchild Semi.
19 2 R1,R21 10 any
20 10 R2,R3,R10,R12,R14,R16,R17,R19,R23,R32 0 any
21 5 R4,R5,R6,R7,R33 10k any
22 4 R8,R9,R11,R13 22 any
23 1 R15 3k any
24 1 R18 3.92k any
25 1 R20 2.2k any
26 1 R22 15K any
27 1 R24 300K any
28 1 R25 2.2 any
29 2 R26,R27 TBD any
30 4 R28,R29,R30,R31 4.7 any
31 1 S1 Vout/Clk switch Digikey
32 4 U1,U3,U4,U5 SC1405 Semtech, [phone]
33 1 U2 SC1144CSW Semtech, [phone]

8

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

August 31, 2000

HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER

SC1405

APPLICATION INFORMATION
SC1405 is a high speed, smart dual MOSFET driver.

It is designed to drive Low Rds_On power MOSFET’s
with ultra-low rise/fall times and propagation delays.
As the switching frequencies of PWM controllers is in­creased to reduce power supply and Class-D amplifier
volume and cost, fast rise and fall times are necessary
to minimize switching losses (TOP MOSFET) and re­duce Dead-time (BOTTOM MOSFET). While Low
Rds_On MOSFET’s present a power saving in I
losses, the MOSFET’s die area is larger and thus the
effective input capacitance of the MOSFET is in­creased. Often a 50% decrease in Rds_On more than
doubles the effective input gate charge, which must be
supplied by the driver. The Rds_On power savings
can be offset by the switching and dead-time losses
with a sub-optimum driver. While discrete solution can
achieve reasonable drive capability, implementing
shoot-through, programmable delay and other house­keeping functions necessary for safe operation can be­come cumbersome and costly. The SC1405 family of
parts presents a total solution for the high-speed, high
power density applications. Wide input supply range of

4.5V-25V allows use in battery powered applications,
new high voltage, distributed power servers as well as
Class-D amplifiers.

THEORY OF OPERATION

The control input (CO) to the SC1405 is typically sup­plied by a PWM controller that regulates the power
supply output. (See Application Evaluation Schematic,
Figure 3). The timing diagram demonstrates the se­quence of events by which the top and bottom drive
signals are applied. The shoot-through protection is
implemented by holding the bottom FET off until the
voltage at the phase node (intersection of top FET
source, the output inductor and the bottom FET drain)
has dropped below 1V. This assures that the top FET
has turned off and that a direct current path does not
exist between the input supply and ground, a condition
which both the top and bottom FET’s are on momen­tarily. The top FET is also prevented from turning on
until the bottom FET is off. This time is internally set to
20ns (typical) and may be increased by adding a ca­pacitor to the C-Delay pin. The delay is approximately
1ns/pf in addition to the internal 20ns delay. The exter­nal capacitor may be needed if multiple High input ca­pacitance MOSFET’s are used in parallel and the fall
time is substantially greater than 20ns.

2

R

the parallel Schottky or the bottom FET body diode will
have to conduct during dead-time.

LAYOUT GUIDELINES

As with any high speed , high current circuit, proper
layout is critical in achieving optimum performance of
the SC1405. The Evaluation board schematic (Refer
to figure 3) shows a four-phase synchronous design
with all surface mountable components.
While components connecting to C-Delay, OVP_S,
EN,S-MOD, DSPS_DR and PRDY are relatively non­critical, tight placement and short,wide traces must be
used in layout of The Drives, DRN, and especially
PGND pin. The top gate driver supply voltage is pro­vided by bootstrapping the +5V supply and adding it
the phase node voltage (DRN). Since the bootstrap
capacitor supplies the charge to the TOP gate, it must
be less than .5” away from the SC1405. Ceramic X7R
capacitors are a good choice for supply bypassing near
the chip. The Vcc pin capacitor must also be less than
.5” away from the SC1405. The ground node of this
capacitor, the SC1405 PGND pin and the Source of
the bottom FET must be very close to each other,
preferably with common PCB copper land with multiple
vias to the ground plane (if used). The parallel Schot­tky must be physically next to the Bottom FETS Drain
and source. Any trace or lead inductance in these con­nections will drive current way from the Schottky and
allow it to flow through the FET’s Body diode, thus re­ducing efficiency.

PREVENTING INADVERTENT BOTTOM FET
TURN-ON

At high input voltages, (12V and greater) a fast turn-on
of the top FET creates a positive going spike on the
Bottom FET’s gate through the Miller capacitance,
Crss of the bottom FET. The voltage appearing on the
gate due to this spike is:

Vspike=Vin*crss/(Crass+ciss)
Where Ciss is the input gate capacitance of the bottom

FET. This is assuming that the impedance of the drive
path is too high compared to the instantaneous
impedance of the capacitors. (since dV/dT and thus
the effective frequency is very high). If the BG pin of
the SC1405 is very close to the bottom FET, Vspike
will be reduced depending on trace inductance, rate if
rise of current,etc.

It must be noted that increasing the dead-time by high
values of C-Delay capacitor will reduce efficiency since

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

While not shown in Figure 3, a capacitor may be added
from the gate of the Bottom FET to its source, prefer-

9

August 31, 2000

HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER

SC1405

ably less than .1” away. This capacitor will be added to
Ciss in the above equation to reduce the effective spike
voltage, Vspike.
The selection of the bottom MOSFET must be done with
attention paid to the Crss/Ciss ratio. A low ratio reduces
the Miller feedback and thus reduces Vspike. Also
MOSFETs with higher Turn-on threshold voltages will
conduct at a higher voltage and will not turn on during
the spike. The MOSFET shown in the schematic (figure

3) has a 2 volt threshold and will require approximately 5
volts Vgs to be conducting, thus reducing the possibility
of shoot-through. A zero ohm bottom FET gate resistor
will obviously help keeping the gate voltage low.
Ultimately, slowing down the top FET by adding gate re­sistance will reduce di/dt which will in turn make the ef­fective impedance of the capacitors higher, thus allowing
the BG driver to hold the bottom gate voltage low. It
does this at the expense of increased switching times (
and switching losses) for the top FET.

RINGING ON THE PHASE NODE

The top MOSFET source must be close to the bottom
MOSFET drain to prevent ringing and the possibility of
the phase node going negative. This frequency is de­termined by:

=1/(2¶* Sqrt(Lst*Coss))

F

ring

ASYNCHRONOUS OPERATION

The SC1405 can be configured to operate in Asyn­chronous mode by pulling S-MOD to logic LOW, thus
disabling the bottom FET drive. This has the effect of
saving power at light loads since the bottom FET’s
gate capacitance does not have to charged at the
switching frequency. There can be a significant sav­ings since the bottom driver can supply up to 2A pulses
to the FET at the switching frequency. There is an ad­ditional efficiency benefit to operating in asynchronous
mode. When operating in synchronous mode, the in­ductor current can go negative and flow in reverse di­rection when the bottom FET is on and the DC load is
less than 1/2 inductor ripple current. At that point, the
inductor core and wire losses, depending on the mag­nitude of the ripple current, can be quite significant.
Operating in asynchronous mode at light loads effec­tively only charges the inductor by as much as needed
to supply the load current, since the inductor never
completely discharges at light loads. DC regulation
can be an issue depending on the type of controller
used and minimum load required to maintain regula­tion. If there are no Schottkys used in parallel with bot­tom FET, the FET’s body diode will need to conduct in
asynchronous mode. The high voltage drop of this
diode must be considered when determining the crite­ria for this mode of operation.

Where:

= The effective stray inductance of the top FET

L

st

added to trace inductance of the connection between top
FET’s source and the bottom FET’s drain added to the
trace resistance of the bottom FET’s ground connection.
Coss=Drain to source capacitance of bottom FET. If
there is a Schottky used, the capacitance of the Schottky
is added to the value.

Although this ringing does not pose any power losses
due to a fairly high Q, it could cause the phase node to
go too far negative, thus causing improper operation,
double pulsing or at worst driver damage. This ringing is
also an EMI nuisance due to its high resonant frequency.
Adding a capacitor, typically 1000-2000pf, in parallel with
Coss can often eliminate the EMI issue. If double puls­ing is caused due to excessive ringing, placing 4.7-10
ohm resistor between the phase node and the DRN pin
of the SC1405 should eliminate the double pulsing.
Proper layout will guarantee minimum ringing and elimi­nate the need for external components. Use of SO-8 or
other surface mount MOSFETs will reduce lead induc­tance as well as radiated EMI.

DSPS DR

This pin produces an output which is a logical duplicate
of the bottom FET’s gate drive, if S-MOD is held LOW.

OVP_S/OVER TEMP SHUTDOWN

Output over-voltage protection may be implemented on
the SC1405 independent of the PWM controller . A
voltage divider from the output is compared with the
internal bandgap voltage of 1.2V (typical). Upon ex­ceeding this voltage, the overvoltage comparator dis­ables the top FET, while turning on the bottom FET to
allow discharge of the output capacitors excessive volt­age through the output inductor. There should be suffi­cient RC time constant as well as voltage headroom on
the OVP_S pin to assure it does not enter overvoltage
mode inadvertently. The SC1405 will shutdown if its Tj
exceeds 165 °C.

10

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER

August 31, 2000
Performance diagrams, Application Evaluation Board. (Fig.3)

SC1405

Figure 4-Timing diagram:
Ch1:CO input
Ch2:TG drive
Ch3:BG non-overlap drive
Ch4:phase node

Iout=20A (10A/phase)
Refer to Eval. Schematic
(fig.3)

Vin=10V, Vout=2V TOP FET IR7811, Bottom
FET IR7030(L) Qg(tot)=35nc

Figure 5-Timing diagram:
Rise/Fall times

Ch1:TG drive
Ch2:BG drive
Cursor:Tpdh
Iout=20A (10A/phase)

Refer to Eval. Schematic
(fig.3)

TG

11

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

August 31, 2000

OUTLINE DRAWING TSSOP-14

HIGH SPEED SYNCHRONOUS POWER
MOSFET SMART DRIVER

SC1405

ECN00-1259

12

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320