Page 1
HIGH SPEED SYNCHRONOUS POWER
MOSFET DRIVER
SC1205
PRELIMINA RY - Dec ember 7, 1999
TEL:805-498-2111 FAX:805-498-3804 WEB:ht tp://www.semtech.com
DESCRIPTION
The SC1205 is a cost effect iv e Dual MOSFE T Driver
designed for switc hing High and Low side Power
MOSFETs. Each driver i s capable of driving a
3000pF load in 20ns rise/fall time and has a 20ns max
propagation delay from input t r ansition to the gate of
the power FET’s. An internal O verlap Protection Circuit prevents shoot-t hr ough from V in
main switc hing and synchronous MOSFET’s. The
Ov er lap Protection circuit ensures the Bottom FET
does not turn on unti l the Top FE T source has reached
a voltage low enough to prevent cross-conduction.
The high curr ent drive capability (2A peak) allows fast
switching, t hus reducing switching l osses at high
(1MHz) PWM frequencies. T he high voltage CMOS
process allows operation from 5-25 V olts at top MO S FET drain, thus making SC1205 suitabl e for batt er y
powered applications. Connecting E nable pin (EN) to
logic low shuts down both drives and reduces operating current to less than 10uA.
An Under-Voltage-Lock-Out c ircuit is included t o guar antee that both driver outputs are low when the 5V
logic level is less than or equal to 4.4V (typ) at supply
ramp up (4. 35V at supply ramp down). A n Internal
temperature sensor shuts down all drives in the event
of overtemperature. SC1205 is fabri c ated utilizing
CMOS technology for low quiescent current . The
SC1205 is offered in a standar d S O-8 package.
to GND in the
FEATURES
•
Fast rise and fall t imes (15ns typi c al with 3000pf
load)
•
2Amp peak drive c ur rent
•
14ns max Pr opagation delay ( B G going low)
•
Adaptive Non-overlapping Gate Dri ves provide
shoot-through protec tion
•
Floating top drive switches up to 25V
•
Under-Volt age lock-out
•
Ov er temperature protection
•
Less than 10uA supply current when EN is l ow
•
Low cost
APPLICATIONS
•
High Density sunchronous power supplies
•
Motor Dri ves/Class-D amps/Half br idge drivers
•
High fr equenc y (to 1.2 MHz) oper ation allows use
of small inductors and low cost caps in place of
electrolytics
•
Portable c omputers
•
Battery powered appl ications
ORDERING INFORMATION
DEVICE
SC1205CS SO-8 0 - 125°C
Note:
(1) Add suffix ‘TR’ for t ape and r eel.
(1)
PACKAGE TEMP. RANGE (TJ)
BLOCK DIAGRAMPIN CONFIGURATION
Top View
(SO-8)
1
© 1999 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 2
HIGH SPEED SYNCHRONOUS POWER
SC1205
MOSFET DRIVER
PRELIMINA RY - Dec ember 7, 1999
ABSOLU TE MAXIMUM RATINGS
Parameter Symbol Conditions Maximum Units
V
Supply Vol tage V
CC
BST to PGND VMAX
BST to DRN VMAX
DRN to PGND VMAX
OVP_S to PGND VMAX
MAX5V
BST-PGND
BST-DRN
DRN-PGN
OVP_S-PGND
Input pin CO -0.3 to 7.3 V
Continuous Power Dissipation Pd Tamb = 25° C, T
Tcase = 25°C, T
Thermal Resistance Junction to Case
Thermal Resistance Junction to
Ambient
Operating Temperat ur e Range
Storage Temperature Range
Lead Temperature (Soldering) 10 sec
θϑΧ
θ
T
T
STG
T
LEAD
JA
J
= 125°C
J
= 125°C
J
NOTE:
(1) Specificat ion refers to application cir c uit in F igure 1.
7V
30 V
7V
25 V
10 V
0.66
W
2.56
40 °C/W
150 °C/W
0 to +125 °C
-65 to +150 °C
300 °C
ELECTRICAL CHARACTERISTICS (DC OPERATING SPECIFICATIONS)
Unless specified: -0 <
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
POWER SUPPLY
Supply Vol tage V
Quiescent Curr ent, operati ng Iq_op VCC = 5V, CO = 0V 1 ma
Quiescent Current Iq_stby EN = 0V 10 µA
UNDER-VOLTAGE LOCKO UT
Start T hr eshol d V
Hysteresis Vhys
Logic Activ e Threshold V
< 125°C; VCC = 5V; 4V < V
θ
J
CC
START
UVLO
ACT
BST
< 26V
V
CC
4.15 5 6.0 V
4.2 4.4 4.6 V
0.05 V
1.5 V
2
© 1999 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 3
HIGH SPEED SYNCHRONOUS POWER
SC1205
MOSFET DRIVER
PRELIMINA RY - Dec ember 7, 1999
ELECTRICAL CHARACTERISTICS (DC O PERATING SPECIFICATIONS) Cont.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CO
High Level Input V oltage V
Low Level I nput Voltage V
THERMAL SHUTDOWN
Ov er Temperature Trip Point T
Hysteresis T
OTP
HYST
HIGH-SIDE DRIVER
Peak Output Cur rent I
PKH
Output Resistanc e Rsrc
Rsink
LOW-SIDE DRIVER
IH
IL
2.0 V
0.8 V
165 °C
10 °C
2A
TG
TG
duty cycle < 2%, tpw < 100µs,
= 125°C, V
T
J
= 4.0V (src)+V
V
TG
or VTG = 0.5V (sink ) +V
BST
- V
DRN
= 4.5V,
DRN
DRN
.7
1
Ω
Ω
Peak Output Cur rent I
PKL
Output Resistanc e Rsrc
Rsink
BG
BG
duty cycle < 2%, tpw < 100µs,
= 125°C
T
J
= 4.6V, VBG = 4V (src),
V
V_5
or V
LOWDR
= 0.5V (sink )
2A
1.2
1.0
Ω
Ω
3
© 1999 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 4
HIGH SPEED SYNCHRONOUS POWER
SC1205
MOSFET DRIVER
PRELIMINA RY - Dec ember 7, 1999
AC OPERATING SPECIFICATIONS
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
HIGH-SIDE DRIVER
rise time tr
fall time tf
propagation del ay tim e,
tpdh
TG going high
propagation del ay tim e,
tpdl
TG going low
LOW-SIDE DRIVER
rise time tr
fall time tr
propagation del ay tim e
tpdh
BG going hi gh
, CI = 3nF, V
TG
TG
TG
TG
BG
BG
BGHI
CI = 3nF, V
CI = 3nF, V
CI = 3nF, V
CI = 3nF, V
CI = 3nF, V
CI = 3nF, V
= 125°C
T
J
BST
= 125°C
T
J
BST
= 125°C
T
J
BST
= 125°C
T
J
BST
= 125°C
T
J
= 125°C
T
J
= 125°C
T
J
- V
DRN
- V
DRN
- V
DRN
- V
DRN
= 4.6V,
V_5
= 4.6V,
V_5
= 4.6V,
V_5
, DRN <
= 4.6V,
= 4.6V,
= 4.6V,
= 4.6V,
1V
14
12
20
15
15
13
12
23
19
32
24
24
21
19
ns
ns
ns
ns
ns
ns
ns
progagation del ay tim e
BG going l ow
tpdl
BG
CI = 3nF, V
= 125°C
T
J
V_5
= 4.6V,
7
12
ns
UNDER-VOLTAGE LOCKO UT
V_5 rampi ng up tpdh
V_5 ramping down tpdl
UVLO
UVLO
EN is High 10 us
EN is High 10 us
4
© 1999 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 5
HIGH SPEED SYNCHRONOUS POWER
SC1205
MOSFET DRIVER
PRELIMINA RY - Dec ember 7, 1999
PIN DESCRIPTION
Pin # Pin Name Pin Function
1 DRN This pin connects to t he junction of the switching and synchronous
MOSFET’s. This pin can be subj ec ted to a -2V m inim um relat iv e to
PGND without affec ting operation.
2 TG Output gate drive for t he swit c hing (high-side) M OSFET.
3 BST Bootstrap pin. A capacitor is connected between BST and DRN pins to
develop the floating boot str ap vol tage for t he high-side MOSFET. The
capacitor val ue is typically between 0.1µF and 1µF (ceramic).
4 CO TTL-l evel input signal to the MOSF ET drivers.
5 EN When high, thi s pi n enables the internal circ uitry of the device. When
low, TG, B G and PRDY are forced low and the supply curr ent (5V) is
less than 10µA.
6 VS +5V supply. A .22-1µF ceram ic capacitor should be connected from 5V
to PGND very close to this pin.
7 BG O utput drive for the synchronous MOSF ET.
8 PGND Ground.
NOTE:
(1) All logic level inputs and output s are open c ollector TTL compatible.
TIMING DIAGRAM
5
© 1999 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 6
HIGH SPEED SYNCHRONOUS POWER
MOSFET DRIVER
PRELIMINA RY - Dec ember 7, 1999
Figure 1 - Timing characteristics while driv ing a 3nf load at Tam b = 125°C
after CO low to high tr ansition.
SC1205
Ch1. CO input
going high (star t
of cycle)
Ch2. BG dri ve
Ch3. TG drive
Cload = 3 nf
C_delay = 0
Figure 2-Timing characteristics while driv ing a 3nf load at Tam b = 125°C
after DRN vol tage transition to a low voltage (DRN < 1V )
Ch1. DRN (phase
node) voltage going low
Ch2. BG going
high
Cload = 3 nf
C_delay = 0
6
© 1999 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 7
PRELIMINA RY - Dec ember 7, 1999
HIGH SPEED SYNCHRONOUS POWER
MOSFET DRIVER
SC1205
Figure 3-SC1205 Evaluation
Board
22u,10V
C14
22u,10V
1500uf
C17
C56
.1
Q1
IR7811Q2FDB7030
4.7
R390
2
1657
TG
BST
U12
C55
18619
Drv1
Vcc12v
NC
Rref
231
10k 10
10uf
EN
8
S1
9
C13
.6uh
L1
SS12
D1
R45
0
R40
BG
DRNVS
EN
4
R43
10
16
17
GND
Drv0
Vid1
Vid0
5
4
1234567
16151413121110
+5V
VIN
C4
C31
C16
C15
VIN+12V
Long PCB Trace
1000uf
C10
J1
12345
1u,10V
22u,10V
22u,10V
1u,10V
10
R1
C9
1000uf,16V
1u,16V
1u,16V
1u,16V
1500uf
C30
3
D10
5819
.1
R44
20
Outv
Vcc5v
vcc5v
R38
C12
.1
C11
100UF
C8
C7
C6
C5
INPUT
6
GND
CO
22u,10V
C18
VIN
8
SC1205
D11
EN
15
Enable
Vid2
Vout/Clk switch
14
FBG
Vid3
7
22u,10V
C19
C58
.1
Q3
3
U11
5819
C57
.1
8 13
Vid4 Bgout
R410
2
TG
BST
22u,10V
C20
22u,10V
C21
.6uh
L2
SS12
D2
IR7811Q4FDB7030
4.7
R45
0
R42
1657
BG
DRNVS
CO
EN
4
VOUT
11
Comp
SC1142CSW
OC-
OC+ FB
9 12
10
22u,10V
GND
22u,10V
C22
8
SC1205
10
35k
R10
100
3.9k
R6
C24
R9
R8
.022
U1
35k
R10
R7 6k
22u,10V
C29
22u,10V
C32
51
R15
VOUT
51
R14
51
R13
****
51
R12
EN
1u,10V
C28
C25
.022
300k
R11
C23
.1
C27
.01
C26
22u,10V
C36
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98
A99
A100
A101
A102
A103
A104
A105
A106
A107
A108
A109
A110
A111
A112
A113
A114
A115
A116
A117
A118
A119
A120
N/C
11Tuesday, June 29, 1999
PentiumII
VCC_VTT
GND
VCC_VTT
IERR#
A20M#
GND
FERR#
IGNNE#
TDI
GND
TDO
PWRGOOD
TESTHI
GND
THERMTRIP#
Reserved
$PIN16
GND
$PIN18
$PIN19
$PIN20
GND
$PIN22
$PIN23
$PIN24
GND
$PIN26
$PIN27
$PIN28
GND
$PIN30
$PIN31
$PIN32
GND
$PIN34
$PIN35
$PIN36
GND
$PIN38
$PIN39
$PIN40
GND
$PIN42
$PIN43
$PIN44
GND
$PIN46
$PIN47
$PIN48
GND
$PIN50
$PIN51
$PIN52
GND
$PIN54
$PIN55
$PIN56
GND
$PIN58
$PIN59
$PIN60
GND
$PIN62
$PIN63
$PIN64
GND
$PIN66
$PIN67
$PIN68
GND
$PIN70
$PIN71
$PIN72
GND
$PIN74
$PIN75
$PIN76
GND
$PIN78
$PIN79
$PIN80
GND
$PIN82
$PIN83
$PIN84
GND
$PIN86
$PIN87
$PIN88
GND
$PIN90
$PIN91
$PIN92
GND
$PIN94
$PIN95
$PIN96
GND
$PIN98
$PIN99
$PIN100
GND
$PIN102
$PIN103
$PIN104
GND
$PIN106
$PIN107
$PIN108
GND
$PIN110
$PIN111
$PIN112
GND
$PIN114
$PIN115
$PIN116
GND
VID[2]
VID[1]
VID[4]
121
$PIN121
B1
$PIN122
B2
$PIN123
B3
$PIN124
B4
VCC_VTT
B5
$PIN126
B6
$PIN127
B7
$PIN128
B8
VCC_VTT
B9
$PIN130
B10
$PIN131
B11
$PIN132
B12
VCC_CORE
B13
$PIN134
B14
$PIN135
B15
$PIN136
B16
VCC_CORE
B17
$PIN138
B18
$PIN139
B19
$PIN140
B20
$PIN141
B21
$PIN142
B22
$PIN143
B23
$PIN144
B24
VCC_CORE
B25
$PIN146
B26
$PIN147
B27
$PIN148
B28
VCC_CORE
B29
$PIN150
B30
$PIN151
B31
$PIN152
B32
VCC_CORE
B33
$PIN154
B34
$PIN155
B35
$PIN156
B36
VCC_CORE
B37
$PIN158
B38
$PIN159
B39
$PIN160
B40
$PIN161
B41
$PIN162
B42
$PIN163
B43
$PIN164
B44
VCC_CORE
B45
$PIN166
B46
$PIN167
B47
$PIN168
B48
VCC_CORE
B49
$PIN170
B50
$PIN171
B51
$PIN172
B52
VCC_CORE
B53
$PIN174
B54
$PIN175
B55
$PIN176
B56
VCC_CORE
B57
$PIN178
B58
$PIN179
B59
$PIN180
B60
$PIN181
B61
$PIN182
B62
$PIN183
B63
$PIN184
B64
VCC_CORE
B65
$PIN186
B66
$PIN187
B67
$PIN188
B68
VCC_CORE
B69
$PIN190
B70
$PIN191
B71
$PIN192
B72
VCC_CORE
B73
$PIN194
B74
$PIN195
B75
$PIN196
B76
VCC_CORE
B77
$PIN198
B78
$PIN199
B79
$PIN200
B80
$PIN201
B81
$PIN202
B82
$PIN203
B83
$PIN204
B84
VCC_CORE
B85
$PIN206
B86
$PIN207
B87
$PIN208
B88
VCC_CORE
B89
$PIN210
B90
$PIN211
B91
$PIN212
B92
VCC_CORE
B93
$PIN214
B94
$PIN215
B95
$PIN216
B96
VCC_CORE
B97
$PIN218
B98
$PIN219
B99
$PIN220
B100
$PIN221
B101
$PIN222
B102
$PIN223
B103
$PIN224
B104
VCC_CORE
B105
$PIN226
B106
$PIN227
B107
$PIN228
B108
VCC5
B109
$PIN230
B110
$PIN231
B111
$PIN232
B112
VCC_L2
B113
$PIN234
B114
$PIN235
B115
$PIN236
B116
VCC_L2
B117
$PIN238
B118
VID[3]
B119
VID[0]
B120
VCC_L2
121
SC1142EVB-A
SC1142-1205 Evaluation Board
B
Title
Size Document Number Rev
Date: Sheet of
*
OPTIONAL
+5V
7
© 1999 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 8
HIGH SPEED SYNCHRONOUS POWER
SC1205
MOSFET DRIVER
PRELIMINA RY - Dec ember 7, 1999
BILL OF MATERIAL
Item Qty Reference Value Manufacturer
1 3 C4,C15,C28 1u,10V, Cer. AVX, Murata
2 3 C5,C6, C7 1u,16V, Cer. AVX, Murata
3 1 C8 1000uF, 16V Nichicon, any
4 1 C9 100uF Nichicon, any
5 1 C10 1000uf Nichic on, any
7 1 C12 10uF Nichicon, any
8 13 C13,C14,C16,C18,C19,C20,C21,C22,C24,C29,C31,C32,
C36
9 2 C17,C30 1500uf Nichicon, Sanyo
10 2 C23,C25 .022 Avx, any
11 1 C26 .01 Avx, any
12 6 C11,C27,C55,C56,C57,C58 .1 Avx, any
13
14 2 D1,D2 SS12 General Instruments, any
15 2 D10,D11 5819 General Instruments, any
16 1 J1 Input
17 2 L1,L2 .6uh Falco, P/N: TO2508 or
18 2 Q1,Q 3 IR7811 Int. Rectifier
19 2 Q2,Q4 FDB7030 Fairchild Semi .
20 4 R1,R9,R43,R44 10 any
21 1 R6 3.9k any
22 1 R7 100 any
23 1 R8 6k any
24 1 R10 35k any
25 1 R11 300k any
26 4 R12,R13,R14,R15 51 any, Required in asynch.
27 1 R38 10K any
28 4 R39,R40,R41,R42 0 any
29 1 R45 4.7 any
30 1 S1 Vout/Clk switch Digikey
31 1 U2 Pentium II™ Slot 1 Connector
22u, 10V Murata
(GRM235Y5V226Z010)
SDIP0804-608M
(305) 662-9076
(310) 252-7099
(408) 822-2000
operation
32 1 U1 SC1142CSW Semtech, (805) 499-2111
33 2 U11,U12 SC1205S Semtech, (805) 499-2111
8
© 1999 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 9
PRELIMINA RY - Dec ember 7, 1999
HIGH SPEED SYNCHRONOUS POWER
MOSFET DRIVER
SC1205
APPLICATION INFORMATION:
SC1205
It is designed t o dr ive Low Rds_On power MOSFET’s
with ultr a- low rise/fall times and propagati on delays.
As the switching frequencies of PWM control lers is
increased to reduce power supply and Class-D ampli fier vol ume and cost, fast rise and f all times are necessary to minimize switching losses ( TOP MOS FET)
and reduce Dead-ti me (BOT TOM MOSFET). Whi le
Low Rds_On MOSFET’s present a power sav ing in I
losses, the MOSFE T’s die area is larger and thus the
effective input capacitanc e of the MO S FET is increased. Often a 50% decrease in Rds_On more than
doubles the effective input gate charge, which must be
supplied by the dr iver. The Rds_On power savings
can be offset by the switching and dead-time losses
with a sub-optimum driver . While discr ete solution
can achieve reasonable drive capab ility, implementing
shoot-through, progr ammable delay and other housekeeping f unc tions necessary for safe operation c an
become cumbersome and costl y . The SC120X family
of parts presents a total solution for t he high-speed,
high power density appl ications. Wide input supply
range of 4.5V -25V allows use in batter y powered applicat ions, new high voltage, distributed power servers
as well as Class-D amplifi er s.
THEORY OF OPERATION
The control input (CO ) to the SC1205 is typicall y supplied by a PWM c ontroller that regulates the power
supply output. ( S ee A pplication Evaluation
Schematic, Figure 3). The timing diagram demonstrates the sequence of events by which the top and
bottom drive signals are applied. The shoot-t hr ough
protection is im plemented by holding the bottom FET
off until the voltage at the phase node (intersection of
top FET source, the output inductor and the bot tom
FET drain) has dropped below 1V. Thi s assures that
the top FET has turned off and that a di rect current
path does not exist between the input supply and
ground, a condition which both t he top and bottom
FET’s are on m omentari ly. The t op FET is also prevent ed from turning on until the bottom FET is off.
This ti me is int er nally set to 20ns.
is a high speed, smart dual MOSFET driver.
2
R
to figure 3) shows a two-phase synchronous design
with all surface mountable com ponents.
While components connecting to EN are relatively
non-crit ical, tight placement and short,wide traces
must be used in l ay out of The Dr ives, DRN, and especially PGND pin. The top gate driv er suppl y vol tage is
provided by bootstrapping the +5V supply and adding
it the phase node voltage ( DRN) . Since the bootstrap
capacitor suppl ies the charge to the top gate, it must
be less than .5” away fr om the SC1205. Cer amic X7R
capacitor s are a good choice for suppl y by passing
near the chip. The Vcc pi n c apac itor m ust also be less
than .5” away f r om the SC1205. The ground node of
this capaci tor, the SC1205 PGND pin and the Sourc e
of the bot tom FET must be very cl ose t o eac h other,
preferably with common PCB copper land with multiple vias to the ground plane (if used). The paral lel
Shottkey must be physical ly next to the Bottom FETS
Drain and source. Any trace or lead inductance in
these connections will drive current way from the
Shottkey and allow it t o flow through t he FET’s Body
diode, thus reducing effici enc y.
PREVENTING INADVERTENT BOT TOM FET
TURN-ON
At high i nput voltages, (12V and great er) a fast t ur n- on
of the t op FET creat es a posit iv e going spike on the
Bottom FET’s gate through the Miller capacitance,
crss of the bottom FET. The voltage appear ing on the
gate due to thi s spik e is:
Vspike=Vin*crss/(Crass+ciss)
Wher e Ciss is the input gat e c apac itance of the bot-
tom FE T. This is assuming that the impedance of the
drive path is too high compared t o the instantaneous
impedance of the capacitors. (sinc e dV /dT and thus
the effecti ve frequency is very hi gh) . If the BG pin of
the SC1205 is very cl ose to the bottom FET, Vspik e
will be reduced depending on trace inductance, rate of
rise of current,etc.
LAYOUT GUIDELINES
As with any high speed , hi gh c ur r ent circuit, proper
layout i s cr itical in achi eving optimum perf or mance of
the SC1205. The E valuation board schematic (Refer
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© 1999 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 10
PRELIMINA RY - Dec ember 7, 1999
HIGH SPEED SYNCHRONOUS POWER
MOSFET DRIVER
SC1205
While not shown in Figure 3, a capacitor may be
added from the gate of the Bottom FET to its source,
preferably less than .1” away. T his capacitor will be
added to Ciss in the above equati on to reduce the effectiv e spi k e vol tage, Vspike.
The selection of the bot tom MOSFET must be done
with attention paid to t he Cr ss/Ciss ratio. A l ow ratio
reduces the Miller feedback and thus reduces Vspike.
Also MOSF E Ts with higher Turn- on threshold voltages
will conduct at a higher v oltage and will not turn on
during the spik e. The MOSF E T shown in the
schemati c ( figure 3) has a 2 volt threshold and will require approximat ely 4.5 volts Vgs to be conducting,
thus reducing the possibility of shoot-through. A zer o
ohm bottom FET gate resistor will obviously help
keeping the gate vol tage low.
Ultimately , slowing down the top FET by adding gate
resistance will reduce di/dt which will in turn make the
effective impedance of the capacitor s hi gher , thus allowing the BG dr iver to hold the bottom gate vol tage
low. It does this at the expense of increased switching
tim es ( and switc hing losses) for the top FET.
RINGING ON THE PHASE NODE
The top MOS FET source must be c lose to the bottom
MOSFET drain to prevent r inging and the possibility of
the phase node going negati ve. T his frequency is
determined by:
can often elim inate the EMI issue. If double pulsing i s
caused due to excessive ringing, placing 4.7-10 ohm
resistor between the phase node and the DRN pin of
the SC1205 should eliminate the double pul sing.
Proper layout will guarantee minimum r inging and
eliminate the need for ex ternal components. Use of
SO-8 or other surface mount MOSFETs while increasing thermal resistance, will reduce lead inductance as
well as radiated E M I.
OVER T E M P S HUTDOWN
The SC1205 will shutdown by pulling both driver if its
juncti on temperature, Tj, exceeds 165 °C.
=1/(2¶* Sqrt(Lst*Coss))
F
ring
Wher e:
L
= The effect ive st r ay inductance of the top FE T
st
added to trace inductance of the connection between
top FET’s source and the bottom F E T’s drain added to
the trace resi stanc e of the bottom FET’s ground connection.
Coss=Drain to source capacitance of bottom F E T. If
there is a Shottkey used, the capacitance of the Shottkey is added to the value.
Although this ringing does not pose any power losses
due to a fairly hi gh Q, it c ould cause the phase node
to go too f ar negative, thus causing improper oper ation, double pulsing or at worst driv er damage. On t he
SC1205, the drain node, DRN, can go as far as 2V
below ground without affecting operation or sustaining
damage.
The ringing is also an EMI nuisance due to its high
resonant frequenc y . Adding a capacitor, ty picall y
1000-2000pf, in parall el with Coss of the bottom F E T
10
© 1999 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 11
PRELIMINA RY - Dec ember 7, 1999
HIGH SPEED SYNCHRONOUS POWER
MOSFET DRIVER
Figure 4-Timing diagram:
Ch1:CO input
Ch2:TG drive
Ch3:BG non-overlap dr iv e
Ch4:phase node
Iout=20A ( 10A /phase)
Refer to E val . Schemat ic
(fig.3)
SC1205
Figure 5-Timing diagram:
Rise/Fall times
Ch1:TG drive
Ch2:BG dri ve
Cursor:Tpdh
Iout=20A ( 10A /phase)
Refer to E val . Schemat ic
(fig.3)
TG
11
© 1999 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 12
PRELIMINA RY - Dec ember 7, 1999
OUTLINE DRAWING - SO-8
HIGH SPEED SYNCHRONOUS POWER
MOSFET DRIVER
JEDEC
REF: MS-012A A
SC1205
LAND PATTERN - SO- 8
ECN99-742
12
© 1999 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY P A RK CA 91320
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