Page 1
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1999 SEMTECH CO RP .
PRELIMINARY - December 2, 1999
652 MITCHELL ROA D NE WBURY P A RK CA 91320
SC1186
1
DESCRIPTION
The SC1186 combines a synchronous vol tage mode
controller with two low-dropout linear regulators
providing m ost of the circuitr y nec essary to
implement t hr ee DC/DC converters for poweri ng
advanced micropr oc essors such as Pentium
®
II & III.
The SC1186 switching sect ion features an integrated
5 bit D/A c onvert er , latched drive output for
enhanced noise im munity , pulse by pulse current
limiti ng and logic compatibl e shutdown. The SC1186
switching secti on oper ates at a fi xed frequenc y of
140kHz, providi ng an optimum compromise between
size, ef ficiency and cost in the intended appl ication
areas. The integrated D/A converter pr ovi des
programmability of output voltage from 2.0V to 3.5V
in 100mV increments and 1.30V to 2.05V in 50mV
increm ents with no external component s.
The SC1186 li near sections are low dropout regulators with short ci r c uit protection, supplying 1.5V f or
GTL bus and 2.5V for non-GTL I/O. The Reference
voltage is made available for exter nal linear
regulators.
Pentium is a regis tered trademark of Intel Corporation
TEL:805-498-2111 F AX:805-498-3804 WEB:htt p://www.semtech.com
BLOCK DIAGRAM
R
S
Q
+
-
70mV
+
+
-
2.5V FET
CONTROLLER
1.5V FET
CONTROLLER
1.265V
REF
ERROR
AMP
D/A
SHOOT-THRU
CONTROL
VCC CS-
BSTH
DH
PGNDH
ENCS+
BSTL
DL
PGNDL
VOSENSE
LDOEN
LDOS2
VID3
LDOS1
VID2
VID1
VID0
AGND
REF
GATE2
GATE1
LDOV REF
VID4
CURRENT
LIMIT
LEVEL SHIFT AND
HIGH SIDE DRIVE
SYNCHRONOUS
MOSFET DRIVE
OSCILLATOR
PIN CONFIGURATION
AGND
GATE1
LDOS1
LDOS2
VCC
REF
LDOEN
CS-
CS+
PGNDH
DH
PGNDL
1
2
3
LDOV
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VOSENS
E
EN
BSTH
BSTL
DL
VID0
VID1
VID2
VID3
VID4
GATE2
Top View
(24 Pin SOIC)
FEATURES
•
Synchronous design, enabl es no heatsi nk sol ution
•
95% efficienc y ( switc hing section)
•
5 bit DAC for output programmability
•
Designed for I ntel Pentium® ll & III requirements
•
1.5V, 2.5V short circuit protected linear contr ollers
•
1.265V ± 1.5% Reference available
APPLICATIONS
•
Pentium® ll & III microprocessor supplies
•
Flex ible m otherboards
•
1.3V to 3.5V micropr oc essor supplies
•
Programmable triple power supplies
ORDERING INFORMATION
Part Number
(1)
Package
Linear
Voltage
Temp.
Range (T
J
)
SC1186CSW SO-24 1.5V/2.5V 0° to 125°C
Note:
(1) Add suffix ‘TR’ for tape and r eel.
Page 2
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1999 SEMTECH CO RP .
PRELIMINARY - December 2, 1999
652 MITCHELL ROA D NE WBURY P A RK CA 91320
SC1186
2
Parameter Symbol Maximum Units
VCC to GND V
IN
-0.3 to +7 V
PGND to GND ± 1 V
BST to GND -0.3 to +15 V
Operating Temperatur e Range T
A
0 to +70 °C
Junction T emperature Range T
J
0 to +125 °C
Storage Temperature Range T
STG
-65 to +150 °C
Lead Temperat ur e (Soldering) 10 seconds T
L
300 °C
Thermal Impedance J unc tion to Ambient
θ
JA
80 °C/W
Thermal Impedance J unc tion to Case
θ
JC
25 °C/W
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
Unless specified: VCC = 4.75V to 5.25V; GND = P
GND
= 0V; V
OSENSE
= VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching Section
Output Voltage I
O
= 2A in Application Circui t See Output Voltage Tabl e
Supply Vol tage VCC 4.5 7 V
Supply Current VCC = 5.0V 8 15 mA
Load Regulation I
O
= 0.8A to 15A 1 %
Line Regulation ±0.15 %
Current Limit Voltage 60 70 85 mV
Oscillator Frequency 120 140 160 kHz
Oscillator Max Duty Cycle 90 95 %
Peak DH Sink/ S our c e Cur r ent BSTH-DH = 4.5V,DH-PGNDH = 3.3V
DH-PGNDH = 1.5V1100
A
mA
Peak DL Sink/ S our c e Cur rent BSTL-DL = 4.5V, DL-PGNDL = 3. 3V
DL-PGNDL = 1. 5V1100
A
mA
Gain (A
OL
) VOSENSE to V
O
35 dB
VID Source Current
VIDx ≤ 2.4V
110 µA
VID Leakage VIDx = 5V 10 µA
Power Good Threshold Voltage 88 112 %
Dead Tim e 40 100 ns
Linear Sections
Quiescent Current LDOV = 12V 5 mA
Output Voltage LDO1 2.493 2.525 2.556 V
Output Voltage LDO2 1.496 1.515 1.534 V
Reference Voltage
Iref ≤ 100µA
1.246 1.265 1.284 V
Gain (A
OL
) LDOS (1,2) to GATE (1,2) 90 dB
Load Regulation I
O
= 0 to 8A 0.3 %
Line Regulation 0.3 %
Output Impedance V
GATE
= 6.5V 1 1.5
k
Ω
Page 3
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1999 SEMTECH CO RP .
PRELIMINARY - December 2, 1999
652 MITCHELL ROA D NE WBURY P A RK CA 91320
SC1186
3
AGND
GATE1
LDOS1
LDOS2
VCC
REF
LDOEN
CS-
CS+
PGNDH
DH
PGNDL
1
2
3
LDOV
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VOSENSE
EN
BSTH
BSTL
DL
VID0
VID1
VID2
VID3
VID4
GATE2
Top View
(24 Pin SOIC)
Note:
(1) All logic l evel inputs and outputs are open
collector TTL compatible.
PIN DESCRIPTION
Pin Pin Name Pin Function
1 AGND Small Signal A nalog and Digit al Ground
2 GATE1 Gate Drive Output LDO1
3 LDOS1 Sense Input for LDO1
4 LDOS2 Sense Input for LDO2
5 VCC Input Voltage
6 REF Buffered Reference Vol tage output
7 LDOEN LDO Supply Monitor.
8 CS- Current S ense Input (negative)
9 CS+ Current Sense Input (positive)
10 PGNDH P ower Gr ound for High S ide Switch
11 DH High Side Dri ver O utput
12 PGNDL Power Ground for Low Side Switch
13 DL Low Side Dri ver Output
14 BSTL Supply for Low Side Driver
15 BSTH Supply for High Si de Dr iver
16 EN
(1)
Logic low shuts down the converter;
High or open f or nor mal operat ion.
17 VOSENSE Top end of int er nal feedback c hain
18
VID4
(1)
Programming Input ( M S B )
19
VID3
(1)
Programming Input
20
VID2
(1)
Programming Input
21
VID1
(1)
Programming Input
22
VID0
(1)
Programming Input ( LS B )
23 LDOV +12V for LDO secti on
24 GATE2 Gat e Dr iv e Output LDO2
ELECTRICAL CHARACTERISTICS (Cont.)
Unless specified: VCC = 4.75V to 5.25V; GND = P
GND
= 0V; V
OSENSE
= VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
LDOV Undervoltage Lock out 6.5 8.0 10 V
LDOEN Threshold 1.3 1.9 V
LDOEN Sink Cur r ent LDOEN = 3.3V
LDOEN = 0V
0.01
-200
1.0
-300µAµA
Ov er c ur r ent Trip Voltage % of Vo set poi nt 20 40 60 %
Power-up Output Short Circui t Immunity 1 5 60 ms
Output Short Circuit Glitch Immunity 0.5 4 6 ms
Gate Pulldown Impedance GATE(1, 2) - AGND;VCC=B S T=0V 80 300 750
k
Ω
VOSENSE I mpedance 10
k
Ω
Page 4
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1999 SEMTECH CO RP .
PRELIMINARY - December 2, 1999
652 MITCHELL ROA D NE WBURY P A RK CA 91320
SC1186
4
OUTPUT VOL TAGE
Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV;
= 0°C < T
j
< 85°C
Standard
PARAMETER VID
43210
MIN TYP MAX UNITS
Output Voltage 01111 1. 277 1.300 1.323 V
01110 1.326 1.350 1.374
01101 1.375 1.400 1.425
01100 1.424 1.450 1.476
01011 1.478 1.500 1.523
01010 1.527 1.550 1.573
01001 1.576 1.600 1.624
01000 1.625 1.650 1.675
00111 1.675 1.700 1.726
00110 1.724 1.750 1.776
00101 1.782 1.800 1.818
00100 1.832 1.850 1.869
00011 1.881 1.900 1.919
00010 1.931 1.950 1.970
00001 1.980 2.000 2.020
00000 2.030 2.050 2.071
11111 1.970 2.000 2.030
11110 2.069 2.100 2.132
11101 2.167 2.200 2.233
11100 2.266 2.300 2.335
11011 2.364 2.400 2.436
11010 2.463 2.500 2.538
11001 2.561 2.600 2.639
11000 2.660 2.700 2.741
10111 2.758 2.800 2.842
10110 2.842 2.900 2.958
10101 2.940 3.000 3.060
10100 3.038 3.100 3.162
10011 3.136 3.200 3.264
10010 3.234 3.300 3.366
10001 3.332 3.400 3.468
10000 3.430 3.500 3.570
Page 5
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1999 SEMTECH CO RP .
PRELIMINARY - December 2, 1999
652 MITCHELL ROA D NE WBURY P A RK CA 91320
SC1186
5
VCC_CORE
2.5V
1.5V
GND
VID0
VID1
VID2
VID3
VID4
12V
5V
EN
REF
3.3V
C1
0.1uF
L1
4uH
R4
5mOhm
C18
0.1uF
+
C14
1500uF
+
C15
1500uF
+
C16
1500uF
+
C17
1500uF
+
C3
1500uF
+
C2
1500uF
R1
10
C13
0.1uF
Q2
IRL34025
Q1
IRL34025
C5
0.1uF
Q3
IRLML2803
+
C11
330uF
R5
2.32k
U1
SC1186CSW
AGND
1
VCC5REF
6
LDOEN
7
CS-
8
CS+
9
PGNDH
10DH11
BSTH
15
EN
16
VOSENSE
17
VID4
18
VID319VID220VID121VID0
22
DL
13
PGNDL
12
BSTL
14
GATE224GATE1
2
LDOV
23
LDOS1
3
LDOS2
4
Q4
IRFZ14S
+
C9
1000uF
R6
1.00k
C21
+
330uF
APPLICATION CIRCUIT
Page 6
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1999 SEMTECH CO RP .
PRELIMINARY - December 2, 1999
652 MITCHELL ROA D NE WBURY P A RK CA 91320
SC1186
6
MATERIALS LIST
Qty. Reference Part/Description Vendor Notes
4 C1,C5,C13,C18 0.1µF Ceram ic Various
6 C2,C3,C14-C17 1500µF/6.3V SANYO MV-GX or equiv. Low ESR
1 C9 1000µF
2 C11,C21 330µF/6.3V Various
1 L1 4µH 8 Turns 16AWG on MICROM ETALS T50-52D core
2 Q1,Q2 See notes See notes FET selection r equires trade-off between effic iency and
cost. Absolute maximum R
DS(ON)
= 22 mΩ for Q1,Q2
1 Q3 IRLML2803 IR
.25Ω 30V SOT23 (or equiv alent)
1 Q4 IRFZ14S IR Or equival ent
1R4
5m
Ω
IRC OAR-1 Series
1R5
2.32kΩ, 1%, 1/8W
Various
1R6
1kΩ, 1%, 1/8W
Various
1R1
10Ω, 5%, 1/8W
Various
1 U1 SC1186CSW SEMTECH
Page 7
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1999 SEMTECH CO RP .
PRELIMINARY - December 2, 1999
652 MITCHELL ROA D NE WBURY P A RK CA 91320
SC1186
7
Typical Ripple, V o=2.0V, Io=10A
Transient Response Vo=2.4V , Io=300m A to 15A
76%
80%
84%
88%
92%
96%
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0
Io (Amps)
Efficiency (%)
Vo=2.8V
Vo=2.0V
Vo=2.5V
Typical Efficiency (Switching section)
2.5V Linear Shor t circuit output response
Output Voltage
Output Current
5A/div
Page 8
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1999 SEMTECH CO RP .
PRELIMINARY - December 2, 1999
652 MITCHELL ROA D NE WBURY P A RK CA 91320
SC1186
8
LAYOUT GUIDELINES
Careful attention to layout requirement s are necessary
for successful implementation of the SC1186 PWM
controller. High cur r ents switching at 140kHz are pr esent in the application and their effect on ground plane
voltage different ials must be underst ood and minimized.
1). The high power parts of the ci rcuit should be laid
out first. A ground pl ane shoul d be used, the number
and position of ground plane i nterruptions should be
such as to not unnecessarily compromise ground plane
integri ty. Isolat ed or semi-isol ated areas of the ground
plane may be deliberately intr oduc ed to constrain
ground currents to particular areas, for example the
input capacitor and bottom FET gr ound.
2). The loop form ed by the Input Capaci tor(s) (Cin), the
Top FET (Q1) and the Bott om FET ( Q2) must be kept
as small as possible. This loop contains all the high
current, fast transit ion switching. Connec tions should
be as wide and as short as possible to minimiz e loop
inductance. M inim izing this loop area will a) reduce
EMI, b) lower ground inject ion currents, r esul ting in
electrically “ c leaner” grounds for the rest of t he system
and c) mi nimi z e source r inging, resul ting in more reliable gate switching signals.
3). The connect ion between the junct ion of Q 1, Q2 and
the output i nduc tor should be a wide trace or c opper
region. It should be as short as practical. Since this
connection has fast voltage transitions, keeping this
connection short will minimize EMI. The connection
between the output induc tor and the sense resistor
should be a wide trace or copper ar ea, there are no
fast voltage or c ur r ent transitions in this connect ion
and length is not so i mportant, however addi ng unnec essary impedance will reduce efficiency.
Vout
12V IN
3.3V Vo Lin1
Vo Lin2
5V
4uH
5mOhm
+
Cout
+
Cin
10
Q2
0.1uF
Q3
+
Cout Lin1
2.32k
Q4
+
Cout Lin2
1.00k
+
Cin Lin
SC1186
AGND
1
VCC
5
REF
6
LDOEN
7
CS-
8
CS+
9
PGNDH
10
DH
11
BSTH
15
EN
16
VOSENSE
17
VID4
18
VID3
19
VID2
20
VID1
21
VID0
22
DL
13
PGNDL
12
BSTL
14
GATE2
24
GATE1
2
LDOV
23
LDOS1
3
LDOS2
4 Q1
0.1uF
Heavy lines indicate
high current paths.
Layout diagram for the SC1186
Page 9
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1999 SEMTECH CO RP .
PRELIMINARY - December 2, 1999
652 MITCHELL ROA D NE WBURY P A RK CA 91320
SC1186
9
Vout
5V
+
+
4) The Output Capac itor(s) (Cout ) shoul d be located
as close to the load as possible, fast tr ansi ent load
currents are suppli ed by Cout only, and connec tions
between Cout and the load must be short, wide copper areas to mi nimi z e inductance and resistanc e.
5) The SC1186 is best pl ac ed over a qui et ground
plane area, avoid pulse currents in the Cin, Q1, Q 2
loop flowing in this area. PGNDH and PGNDL shoul d
be returned to the gr ound plane close to the pac k age.
The AGND pin shoul d be c onnected to the ground
side of (one of) the output capacitor ( s). If this is not
possible, the AG ND pin may be connec ted to the
ground path between the Output Capacitor( s) and the
Cin, Q1, Q2 loop. Under no circumstanc es should
AGND be returned t o a gr ound inside the Cin, Q1, Q2
loop.
6) Vcc f or the SC1186 should be supplied from the
5V supply through a 10Ω resistor, the V c c pin should
be decoupled direc tly to AGND by a 0.1µF ceramic
capacitor, trace lengths should be as short as possi-
ble.
7) The Current Sense resi stor and the divider across
it should form as small a loop as possible, the traces
running back to CS + and CS- on the SC1186 should
run parallel and close to each ot her . The 0.1µF capacitor should be mounted as close to t he CS + and
CS- pins as possible.
8) Ideall y , the grounds for the two LDO sections
should be returned to the ground side of (one of) the
output capaci tor(s).
Currents in various parts of the power section
Page 10
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1999 SEMTECH CO RP .
PRELIMINARY - December 2, 1999
652 MITCHELL ROA D NE WBURY P A RK CA 91320
SC1186
10
COMPONENT SELECTION
SWITCHING SECTION
OUTPUT CAPACITORS - Selection begi ns with the
most cri tical c omponent. Bec ause of fast t r ansi ent load
current requi rements in modern microprocessor core
supplies, the output capacitor s must supply all transient
load current r equirement s until the cur r ent in the output
inductor ramps up to the new level. Output capacitor
ESR is therefore one of the most important c r iteria. The
maximum ESR can be sim ply calculated fr om:
step current Transient I
excursion voltage transient MaximumV
Where
I
V
R
t
t
t
t
ESR
=
=
≤
Each Capacitor Total
Technology C
(µF)
ESR
(mΩ)
Qty.
Rqd.C(µF)
ESR
(mΩ)
Low ESR Tantalum 330 60 6 2000 10
OS-CON 330 25 3 990 8.3
Low ESR Aluminum 1500 44 5 7500 8.8
()
OIN
t
ESR
VV
I
CR
L
−≤
OSC
IN
L
fL4
V
I
RIPPLE
⋅⋅
=
IN
O
)on(DS
2
OCOND
V
V
cycleduty =
where
RIP
≈δ
δ⋅⋅=
2
INOSW
10VIP
−
⋅⋅=
4
f)tt(VI
P
OSCfrINO
SW
⋅+⋅⋅
=
OSCINRRRR
fVQP
⋅⋅=
For example, t o meet a 100m V transient limit with a
10A load step, the output capacitor ESR must be less
than 10mΩ. To meet this kind of ESR l evel, there are
three available capacitor technologies.
The choice of which to use is simply a cost/per formance issue, wit h Low ESR Alumi num being the
cheapest, but taking up the most space.
INDUCTOR - Having dec ided on a suitable type and
value of output capacitor , the maximum all owable
value of i nduc tor can be calculated. Too large an inductor will produce a slow current ramp rat e and will
cause the output capacitor to supply more of the transient load current for longer - leading to an output volt age sag below the ESR excur si on c alculated above.
The maximum induct or value may be calc ulated f r om:
The calculated maxim um inductor value assumes 100%
duty cycle, so some allowance must be made. Choosing
an inductor value of 50 to 75% of the calculated maximum will guarantee that the induct or c ur r ent will ramp
fast enough to reduc e the voltage dropped across the
ESR at a f aster rate than the capacitor sags, hence ensuring a good recovery f r om transient with no additi onal
excursions.
We must also be concerned wit h ripple curr ent in the
output inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current .
Note that most of the output voltage ri pple is produced
by the induct or ripple curr ent fl owing in the output c apacitor ES R. Ripple cur r ent can be calculated fr om:
Ripple current allowance will define the minimum permit ted inductor val ue.
POWER FETS - The FETs are chosen based on several cri teria with probably the m ost import ant being
power dissipation and power handling capability.
TOP FET - The power dissipation in the top F E T is a
combination of c onduc tion losses, switching losses and
bottom FET body diode r ec overy losses.
a) Conduction losses are simply calculated as:
b) Switching losses can be estimated by assuming a
switching time, i f we assume 100ns then:
or more generally,
c) Body diode rec overy losses are more diffi c ult to esti mate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body
diode will be moved through the top FET as it starts to
turn on. The resulting power dissipation in the top FET
will be:
To a first order approx imation, it is convenient to only
consider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A r equirement , typical FET
losses would be:
Page 11
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1999 SEMTECH CO RP .
PRELIMINARY - December 2, 1999
652 MITCHELL ROA D NE WBURY P A RK CA 91320
SC1186
11
)1(RIP
)on(DS
2
OCOND
δ−⋅⋅=
FET type
R
DS(on)
(mΩ)
P
D
(W) Package
IRL34025 15 1.69 D
2
PAK
IRL2203 10.5 1.19 D
2
PAK
Si4410 20 2.26 SO-8
FET type
R
DS(on)
(mΩ)
P
D
(W) Package
IRL34025 15 1.33 D
2
PAK
IRL2203 10.5 0.93 D
2
PAK
Si4410 20 1.77 SO-8
BOTTOM FET - Bottom FET losses are almost entirely
due to conducti on. The body diode is forced i nto conduction at the beginning and end of the bott om switch
conduction period, so when the FET turns on and off,
there is very little voltage across it, resul ting in l ow
switching losses. Conduction losses for the FE T can be
determined by:
For the ex ample above:
Each of t he pac k age types has a characteristic thermal
impedance, for t he TO-220 package, thermal
impedance is mostly determi ned by the heatsink used.
For the surf ace mount packages on doubl e sided FR4, 2
oz printed circuit boar d materi al, thermal impedances of
40
o
C/W for t he D2PAK and 80oC/W for t he S O-8 are
readily ac hiev able. The corr espondi ng temperatur e r ise
is detail ed below:
Temperat ur e rise (oC)
FET type Top FET Bottom FET
IRL34025 67.6 53.2
IRL2203 47.6 37.2
Si4410 180.8 141.6
It is apparent that single SO-8 Si4410 are not adequate
for this applicat ion, but by using par allel pairs in each position, power dissipation will be approximately halved and
temperat ur e rise reduced by a f ac tor of 4.
INPUT CAPACITORS - since the RMS ripple current
in the input capacitor s may be as high as 50% of the
output current , suitable capac itors must be chosen accordingly . Also, duri ng fast load t r ansi ents, there may
be restrict ions on input di/ dt. These restri c tions require
useable energy storage within the converter ci r cuitry,
either as extra output capacitance or, more usually ,
additional input capac itors. Choosing l ow ESR input
capacitors will help maximize ripple rating for a given
size.
SHORT CIRCUIT PROTECTION - LINEARS
The Short circuit feature on t he linear cont r ollers is
implemented by usi ng the Rds(on) of the FETs. As
output current increases, the regul ation loop maintai ns
the output volt age by turning the F E T on more and
more. Eventually, as the Rds(on) lim it is reached, the
FET will be unably to turn on mor e fully, and output
voltage will start to fall. When the output voltage falls
to approximately 50% of nominal, the LDO controller
is latched off, setting output voltage to 0. Power must
be cycled to reset the latch.
To prevent false latchi ng due to capacitor inrush currents or low supply rai ls, the current lim it latc h is initially disabled. It is enabled at a pr eset time ( nominal ly
2mS) after both t he LDOV and LDOEN rai ls rise
above t heir lockout points.
To be most effective, the linear FET Rds(on) should
not be selected art ificially low, the F E T should be chosen so that, at maximum requi r ed c ur r ent, it is almost
fully turned on
If, for ex ample, a linear supply of 1.5V at 4A is required f r om a 3.3V ± 5% rail, max allowable Rds(on)
would be.
Rds(on)max = (0.95*3.3-1.5)/4 ≈ 400m
Ω
To allow for temper ature effects 200mΩ would be a
suitable room temper ature maximum, allowing a peak
short circuit current of approx imately 15A for a short
tim e before shutdown.
Using 1.5X Room temp R
DS(ON)
to allow for temper ature
rise.
Page 12
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1999 SEMTECH CO RP .
PRELIMINARY - December 2, 1999
652 MITCHELL ROA D NE WBURY P A RK CA 91320
SC1186
12
OUTLINE DRAWING
JEDEC MS-013AD
B17104B
ECN99-600 9-22-99
ECN99-719 12-2-99
Loading...