Page 1
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查询SC1186供应商
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
PRELIMINA RY - Dec ember 2, 1999
TEL:805-498-2111 FAX:805-498-3804 WEB:ht tp://www.semtech.com
DESCRIPTION
The SC1186 com bines a synchronous vol tage mode
controller with two low-dropout linear regulators
providing m ost of the circuitr y necessary to
implement t hr ee DC/DC conv er ters for powering
advanced micropr ocessors such as Pentium
The SC1186 switching sect ion feat ur es an i ntegrated
5 bit D/A c onvert er , latched dr ive output for
enhanced noise immunit y, pulse by pulse curr ent
limiti ng and logic compatible shutdown. The SC1186
switching secti on oper ates at a fi xed fr equenc y of
140kHz, providi ng an optimum compr omise between
size, effic iency and cost i n the intended application
areas. The int egr ated D/A converter provi des
programmability of output voltage from 2.0V to 3.5V
in 100mV increments and 1.30V to 2.05V in 50mV
increments with no ext er nal component s.
The SC1186 linear sections are low dropout r egulators with short ci r c uit protection, supplying 1.5V for
GTL bus and 2.5V for non-GTL I/O. The Reference
voltage is made avai lable for exter nal linear
regulators.
®
II & III.
SC1186
FEATURES
•
Synchronous design, enabl es no heatsi nk sol ution
•
95% efficienc y ( swit c hing section)
•
5 bit DAC for output programmability
•
Designed for I ntel Pentium® ll & III requirements
•
1.5V, 2.5V short circuit protect ed linear cont r ollers
•
1.265V ± 1.5% Reference available
APPLICATIONS
•
Pentium® ll & III microprocessor supplies
•
Flex ible m otherboards
•
1.3V to 3.5V microprocessor supplies
•
Programmable tr iple power supplies
ORDERING INFORMATION
Part Number
(1)
Package
Linear
Voltage
SC1186CSW SO-24 1.5V/2.5V 0° to 125°C
Note:
(1) Add suffix ‘TR’ for t ape and r eel.
Temp.
Range (T
J
)
PIN CONFIGURATION
Top View
AGND
GATE1
LDOS1
LDOS2
VCC
REF
LDOEN
CS-
CS+
PGNDH
DH
PGNDL
1
2
3
4
5
6
7
8
9
10
11
12
(24 Pin SOIC)
24
23
22
21
20
19
18
17
16
15
14
13
GATE2
LDOV
VID0
VID1
VID2
VID3
VID4
VOSENS
EN
BSTH
BSTL
DL
BLOCK DIAGRAM
REF
VID4
VID3
VID2
VID1
VID0
VOSENSE
AGND
LDOEN
LDOS1
GATE1
D/A
2.5V FET
CONTROLLER
VCC CS-
+
-
ERROR
AMP
OSCILLATOR
1.265V
REF
LDOV REF
70mV
-
+
1.5V FET
CONTROLLER
ENCS+
CURRENT
LIMIT
+
-
R
Q
S
LDOS2
GATE2
LEVEL SHIFT AND
HIGH SIDE DRIVE
SHOOT-THRU
CONTROL
SYNCHRONOUS
MOSFET DRIVE
BSTH
DH
PGNDH
BSTL
DL
PGNDL
1
© 1999 SEMTECH CORP.
Pentium is a registered trademark of Intel Corporation
652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 2
PROGRAMMABLE SYNCHRONOUS DC/DC
SC1186
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
PRELIMINA RY - Dec ember 2, 1999
ABSOLU TE MAXIMUM RATINGS
Parameter Symbol Maximum Units
VCC to GND V
IN
-0.3 to +7 V
PGND to GND ± 1 V
BST to GND -0.3 to +15 V
Operating Temperat ur e Range T
Junction Temperatur e Range T
Storage Temperature Range T
Lead Temperature (Soldering) 10 seconds T
Thermal Impedance Junction to A mbient
Thermal Impedance Junction to Case
θ
θ
A
J
STG
L
JA
JC
0 to +70 °C
0 to +125 °C
-65 to +150 °C
300 °C
80 °C/W
25 °C/W
ELECTRICAL CHARACTERISTICS
Unless specified: VCC = 4.75V to 5.25V; GND = P
PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching Section
Output Voltage I
Supply Vol tage VCC 4.5 7 V
Supply Current VCC = 5.0V 8 15 mA
Load Regulation I
Line Regulation ±0.15 %
Current Limit Voltage 60 70 85 mV
Oscillator Frequency 120 140 160 kHz
Oscillator Max Duty Cycle 90 95 %
Peak DH Sink/ S our c e Cur rent BSTH-DH = 4.5V,DH- P GNDH = 3.3V
Peak DL Sink/ S ource Current BSTL-DL = 4.5V, DL-PGNDL = 3. 3V
Gain (A
) VOSENSE to V
OL
VID Source Current
VID Leakage VIDx = 5V 10 µA
Power Good Threshold Voltage 88 112 %
Dead Tim e 40 100 ns
Linear Sect ions
Quiescent Curr ent LDOV = 12V 5 mA
Output Voltage LDO1 2.493 2.525 2.556 V
Output Voltage LDO2 1.496 1.515 1.534 V
Reference Voltage
Gain (A
) LDOS (1,2) to GATE (1,2) 90 dB
OL
Load Regulation I
Line Regulation 0.3 %
Output Impedance V
= 0V; V
GND
VIDx ≤ 2.4V
Iref ≤ 100µA
= VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70°C
OSENSE
= 2A in Application Circuit See Output Voltage Tabl e
O
= 0.8A to 15A 1 %
O
DH-PGNDH = 1. 5V1100
DL-PGNDL = 1. 5V1100
O
35 dB
110 µA
1.246 1.265 1.284 V
= 0 to 8A 0.3 %
O
= 6.5V 1 1.5
GATE
A
mA
A
mA
k
Ω
© 1999 SEMTECH CORP.
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652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 3
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
PRELIMINA RY - Dec ember 2, 1999
ELECTRICAL CHARACTERISTICS (Cont.)
SC1186
Unless specified: VCC = 4.75V to 5.25V; GND = P
GND
= 0V; V
= VO; 0mV < (CS+-CS-) < 60mV; LDOV = 11.4V to 12.6V; TA = 0 to 70°C
OSENSE
PARAMETER CONDITIONS MIN TYP MAX UNITS
LDOV Undervoltage Lock out 6.5 8.0 10 V
LDOEN Threshold 1.3 1.9 V
LDOEN Sink Cur r ent LDOEN = 3.3V
LDOEN = 0V
0.01
-200
1.0
-300
µA
µA
Ov er c urrent Trip Voltage % of Vo set poi nt 20 40 60 %
Power-up Output Shor t Circui t Immunity 1 5 60 ms
Output Short Circuit Glitch Immunity 0.5 4 6 ms
Gate Pulldown Impedance GATE(1,2)-AGND;VCC=BST=0V 80 300 750
VOSENSE Impedance 10
k
Ω
k
Ω
PIN DESCRIPTION
Pin Pin Name Pin Function
1 AGND Small Signal A nalog and Digital Ground
2 GATE1 Gate Drive Output LDO1
3 LDOS1 Sense Input for LDO1
4 LDOS2 Sense Input for LDO2
5 VCC Input Voltage
6 REF Buffered Reference Voltage output
7 LDOEN LDO Supply Monitor.
8 CS- Current Sense Input ( negative)
9 CS+ Current Sense Input (positive)
10 PGNDH P ower Ground for Hi gh S ide Switch
11 DH High Side Driver Output
12 PGNDL Power Ground for Low Side Switch
13 DL Low Side Dri ver O utput
14 BSTL Supply for Low Side Driver
15 BSTH Supply for High Si de Dr iv er
16 EN
(1)
Logic low shuts down the converter;
High or open f or normal operation.
17 VOSENSE Top end of int er nal feedback c hain
VID4
VID3
VID2
VID1
VID0
(1)
(1)
(1)
(1)
(1)
Programming Input (MSB)
Programming Input
Programming Input
Programming Input
Programming Input (LSB)
18
19
20
21
22
23 LDOV +12V for LDO secti on
24 GATE2 Gat e Drive Output LDO 2
AGND
GATE1
LDOS1
LDOS2
VCC
REF
LDOEN
CS-
CS+
PGNDH
DH
PGNDL
Note:
(1) All logic level inputs and output s are open
collector TTL compatible.
Top View
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
(24 Pin SOIC)
GATE2
LDOV
VID0
VID1
VID2
VID3
VID4
VOSENSE
EN
BSTH
BSTL
DL
© 1999 SEMTECH CORP.
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652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 4
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
PRELIMINA RY - Dec ember 2, 1999
OUTPUT VOLTAGE
Unless specified: 4.75V < VCC < 5.25V; GND = PGND = 0V; VOSENSE = VO; 0mV < (CS+-CS-) < 60mV;
= 0°C < T
PARAMETER VID
Output Voltage 01111 1. 277 1.300 1.323 V
< 85°C
j
Standard
MIN TYP MAX UNITS
43210
01110 1.326 1.350 1.374
01101 1.375 1.400 1.425
01100 1.424 1.450 1.476
01011 1.478 1.500 1.523
01010 1.527 1.550 1.573
01001 1.576 1.600 1.624
01000 1.625 1.650 1.675
00111 1.675 1.700 1.726
00110 1.724 1.750 1.776
00101 1.782 1.800 1.818
00100 1.832 1.850 1.869
00011 1.881 1.900 1.919
00010 1.931 1.950 1.970
00001 1.980 2.000 2.020
00000 2.030 2.050 2.071
11111 1.970 2.000 2.030
11110 2.069 2.100 2.132
11101 2.167 2.200 2.233
11100 2.266 2.300 2.335
11011 2.364 2.400 2.436
11010 2.463 2.500 2.538
11001 2.561 2.600 2.639
11000 2.660 2.700 2.741
10111 2.758 2.800 2.842
10110 2.842 2.900 2.958
10101 2.940 3.000 3.060
10100 3.038 3.100 3.162
10011 3.136 3.200 3.264
10010 3.234 3.300 3.366
10001 3.332 3.400 3.468
10000 3.430 3.500 3.570
SC1186
© 1999 SEMTECH CORP.
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652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 5
PRELIMINA RY - Dec ember 2, 1999
APPLICATION CIRCUIT
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1186
GND
C18
IRL34025
15
BSTH
0.1uF
+
+
+
10DH11
PGNDH
C16
C14
13
14
DL
BSTL
+
VCC_CORE
C17
1500uF
C15
Q1
8
CS-
IRL34025
17
VOSENSE
1500uF
R4
5mOhm
4uH
L1
Q2
7
18
VID4
LDOEN
R5
2.32k
R6
1.00k
C13
0.1uF
9
CS+
1500uF
1500uF
23
LDOV
3
LDOS1
2.5V
+
Q3
330uF
C11
IRLML2803
1.5V
C9
1000uF
+
Q4
3.3V
IRFZ14S
C21
+
330uF
VCC5REF
U1
6
R1
10
+
+
12V
5V
C1
0.1uF
22
C3
1500uF
C2
1500uF
AGND
EN
VID319VID220VID121VID0
PGNDL
GATE224GATE1
LDOS2
1
16
12
C5
0.1uF
EN
REF
VID0
VID1
SC1186CSW
2
4
VID2
VID3
VID4
5
© 1999 SEMTECH CORP.
652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 6
PROGRAMMABLE SYNCHRONOUS DC/DC
SC1186
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
PRELIMINA RY - Dec ember 2, 1999
MATERIALS LIST
Qty. Reference Part/Description Vendor Notes
4 C1,C5,C13,C18 0.1µF Ceram ic Various
6 C2,C3,C14-C17 1500µF/6.3V SANYO MV-GX or equiv. Low ESR
1 C9 1000µF
2 C11,C21 330µF/6.3V Various
1 L1 4µH 8 Turns 16AWG on MICROM E TALS T50-52D core
2 Q1,Q2 See notes See notes FET selection r equires trade-off between effi c iency and
cost. Absolute maximum R
1 Q3 IRLML2803 IR
1 Q4 IRFZ14S IR Or equival ent
.25Ω 30V SOT23 (or equivalent)
= 22 mΩ for Q1,Q2
DS(ON)
1R4
1R5
1R6
1R1
1 U1 SC1186CSW SEMTECH
5m
Ω
2.32kΩ, 1%, 1/8W
1kΩ, 1%, 1/8W
10Ω, 5%, 1/8W
IRC OAR-1 Series
Various
Various
Various
© 1999 SEMTECH CORP.
6
652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 7
PRELIMINA RY - Dec ember 2, 1999
96%
92%
88%
84%
Efficiency (%)
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1186
80%
76%
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0
Vo=2.8V
Vo=2.0V
Vo=2.5V
Io (Amps)
Typical Efficiency (Switching section)
Typical Ripple, V o=2.0V, I o=10A
Output Voltage
Output Current
5A/div
Transient Response Vo=2.4V , Io=300mA to 15A
© 1999 SEMTECH CORP.
2.5V Linear Short circ uit output r esponse
7
652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 8
PRELIMINA RY - Dec ember 2, 1999
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1186
LAYOUT GUIDELINES
Careful attention to layout requirement s are nec essary
for successful im plementation of the SC1186 PWM
controller. High cur rents switching at 140kHz ar e pr esent in the appl ication and their ef fect on ground plane
voltage differentials m ust be under stood and mini mized.
1). The hi gh power part s of the cir c uit should be laid
out first. A ground plane should be used, the number
and position of ground plane i nterrupti ons should be
such as to not unnecessarily compromise ground plane
integri ty. Isolated or semi-isolated areas of the ground
plane may be deliberately intr oduced to constrain
ground currents to particular ar eas, for ex ample the
input capacitor and bottom FET ground.
2). The l oop formed by the Input Capacitor(s) (Ci n) , the
Top FET ( Q1) and the Bott om FET ( Q2) must be kept
10
1
AGND
2
GATE1
3
LDOS1
4 Q1
0.1uF
0.1uF
LDOS2
5
VCC
6
REF
7
LDOEN
8
CS-
9
CS+
10
PGNDH
11
DH
12
PGNDL
GATE2
LDOV
VID0
VID1
VID2
VID3
VID4
VOSENSE
EN
BSTH
BSTL
DL
SC1186
as small as possible. This loop contains all the high
current, fast transition switching. Connections should
be as wide and as short as possible to minimiz e loop
inductance. Minimizi ng this loop area will a) reduce
EMI, b) lower ground injection current s, r esul ting in
electrically “cleaner” gr ounds for the rest of the system
and c) minimize source ringing, resulting in mor e r eliable gate switching signals.
3). The connection between the junc tion of Q1, Q2 and
the output i nductor should be a wide trac e or c opper
region. It should be as short as practical. Sinc e this
connection has fast voltage transi tions, keeping this
connection short will minimize EMI. The connection
between the output i nduc tor and the sense resistor
should be a wide trace or copper ar ea, there are no
fast voltage or c urrent transitions in this connection
and length is not so i mportant, however addi ng unnec essary impedance will reduce efficiency.
12V IN
24
23
22
21
20
19
18
17
16
15
14
13
5V
Cin
+
1.00k
Q2
4uH
2.32k
5mOhm
Cout
Vout
+
3.3V Vo Lin1
+
Cin Lin
Layout diagram for the SC1186
© 1999 SEMTECH CORP.
Heavy lines indicate
Q3
Q4
+
Cout Lin1
Vo Lin2
+
Cout Lin2
high current paths.
8
652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 9
PRELIMINA RY - Dec ember 2, 1999
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1186
4) The Output Capacitor( s) (Cout) should be locat ed
as close to the load as possible, fast tr ansi ent load
currents are suppli ed by Cout only, and connec tions
between Cout and the load must be short, wide copper areas to minimize induct anc e and r esi stanc e.
5) The SC1186 is best pl ac ed over a quiet ground
plane area, avoid pulse currents in the Cin, Q1, Q2
loop flowing in this area. PGNDH and PGNDL shoul d
be returned to t he gr ound plane close to the pac k age.
The AGND pin should be connected to t he gr ound
side of (one of) the output capacitor(s). If this is not
possible, the AGND pin may be c onnected to the
ground path between the Out put Capacitor( s) and t he
Cin, Q1, Q2 loop. Under no circumstanc es should
AGND be returned to a ground inside the Cin, Q1, Q 2
loop.
6) Vcc for the SC1186 should be supplied from the
5V
5V supply through a 10Ω resistor, the V c c pin should
be decoupled direc tly to AGND by a 0.1µF ceramic
capacitor , trace lengths should be as short as possi-
ble.
7) The Current S ense resistor and the divider across
it should form as small a loop as possible, the traces
running back to CS + and CS- on the SC1186 should
run parall el and close to each ot her . The 0.1µF capacitor shoul d be mounted as close to t he CS + and
CS- pins as possible.
8) Ideall y, the grounds f or the two LDO sections
should be returned to the ground side of ( one of) the
output capacitor(s).
+
Currents in various part s of the power section
Vout
+
9
© 1999 SEMTECH CORP.
652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 10
PRELIMINA RY - Dec ember 2, 1999
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1186
COMPONENT SELECTION
SWITCHING SECTION
OUTPUT CAPACIT O RS - Selection begins with the
most critical component. Because of fast transient load
current requirements i n modern microprocessor core
supplies, the out put capacitor s must supply all transient
load current r equirement s until the cur r ent in the output
inductor r amps up to the new level. Output capacitor
ESR is therefore one of the most important c r iteria. The
maximum ESR can be sim ply calculated f r om:
V
R
ESR
t
≤
I
t
Where
=
t
=
t
step current Transient I
For example, t o meet a 100m V transient l imit with a
10A load step, t he output capacitor ESR must be less
than 10mΩ. To meet this ki nd of ESR level , there are
three available capacitor technologies.
Each Capacitor Total
Technology C
(µF)
Low ESR Tantalum 330 60 6 2000 10
OS-CON 330 25 3 990 8.3
Low ESR Aluminum 1500 44 5 7500 8.8
ESR
(mΩ)
The choice of which to use is simply a cost/ per formance issue, wit h Low ESR Alumi num being the
cheapest, but tak ing up the most space.
INDUCTOR - Having dec ided on a suitable type and
value of output capacitor , the maxim um all owable
value of i nduc tor can be calculated. Too large an inductor will produce a slow current ramp rat e and will
cause the output capacitor to supply more of the transient load cur r ent for longer - leadi ng to an output voltage sag below the ESR excur si on c alculated above.
The maximum induct or val ue may be calc ulated f r om:
CR
ESR
L
()
I
t
VV
−≤
OIN
The calculated maxim um induct or val ue assumes 100%
duty cycle, so some allowance must be made. Choosing
an inductor value of 50 to 75% of the calc ulated maximum will guarantee that the induct or c ur r ent will ramp
excursion voltage transient MaximumV
Qty.
Rqd.C(µF)
ESR
(mΩ)
fast enough to r educ e the voltage dropped across the
ESR at a f ast er r ate than the capacitor sags, hence ensuring a good recovery from tr ansi ent with no additional
excursions.
We must also be concerned with ripple c ur r ent in the
output inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current.
Note that most of the output voltage ripple is produced
by the inductor rippl e c ur r ent fl owing in the output c apacitor E S R. Ripple cur r ent can be calculated fr om:
V
I
L
RIPPLE
IN
=
fL4
⋅⋅
OSC
Ripple current allowance will define the minimum permit ted inductor val ue.
POWER FETS - The FETs are chosen based on several criteria wit h pr obably the m ost import ant being
power dissipation and power handling capability.
TOP FE T - The power dissipati on in the top FE T is a
combination of c onduc tion losses, switching losses and
bottom FET body diode recover y losses.
a) Conduction losses are simply calculated as:
2
RIP
OCOND
δ⋅⋅=
)on(DS
where
V
O
cycleduty =
≈δ
V
IN
b) Switchi ng losses can be estimated by assuming a
switching time, if we assume 100ns then:
2
−
10VIP
⋅⋅=
INOSW
or more generally,
f)tt(VI
⋅+⋅⋅
P
=
SW
4
c) Body diode r ec overy losses are more diffi c ult to esti mate, but to a first approximation, it is reasonable to assume that t he stor ed c har ge on the bottom FET body
diode will be moved through the top FET as it starts to
turn on. The r esul ting power dissipati on in the top FE T
will be:
fVQP
⋅⋅=
OSCINRRRR
To a first order approximation, it is convenient to only
consider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, ty pical FE T
losses would be:
OSCfrINO
© 1999 SEMTECH CORP.
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652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 11
PRELIMINA RY - Dec ember 2, 1999
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
SC1186
Using 1.5X Room temp R
to allow for temperature
DS(ON)
rise.
FET type
R
DS(on)
(mΩ)
IRL34025 15 1.69 D
IRL2203 10.5 1.19 D
(W) Package
P
D
2
PAK
2
PAK
Si4410 20 2.26 SO-8
BOTTOM FET - Bottom FET losses are almost entirely
due to conduction. The body diode is forced into conduction at the beginning and end of the bott om switch
conduction per iod, so when the FET tur ns on and off,
there is very little vol tage across it, resul ting in low
switching losses. Conduction losses for the FE T can be
determined by:
2
OCOND
)1(RIP
δ−⋅⋅=
)on(DS
For the example above:
FET type
R
DS(on)
(mΩ)
IRL34025 15 1.33 D
IRL2203 10.5 0.93 D
(W) Package
P
D
2
PAK
2
PAK
Si4410 20 1.77 SO-8
Each of t he pac kage types has a characteri stic thermal
impedance, for t he TO-220 package, thermal
impedance is mostly determi ned by the heatsink used.
For the surface mount pac k ages on doubl e si ded FR4, 2
oz printed c ircuit boar d materi al, thermal impedances of
o
C/W for t he D2PAK and 80oC/W for t he S O-8 are
40
readily achievable. The c or responding temper ature rise
is detailed below:
INPUT CAPACITORS - since the RMS ripple current
in the input capacitor s may be as high as 50% of t he
output current, suitabl e c apac itors must be chosen accordingly. Also, during fast load transients, t her e may
be restrict ions on input di/dt. These restrictions requi r e
useable energy storage within the converter circuitr y ,
either as ex tra output capacitance or, more usually ,
additional input capac itors. Choosing low ESR input
capacitor s will help maximize ripple rating for a given
size.
SHORT CIRCUIT PROTECTION - LINEARS
The Short circuit feature on t he linear cont r ollers is
implemented by usi ng the Rds(on) of t he FETs. As
output current increases, the regulation l oop maintains
the output volt age by turning the F E T on more and
more. Eventually, as the Rds(on) lim it is reached, the
FET will be unably to turn on mor e fully, and output
voltage will start to fall. When the output voltage falls
to approximately 50% of nominal, the LDO contr oller
is latched off, setting output voltage to 0. P ower must
be cycled to reset the latch.
To prevent false latchi ng due to capacitor inrush currents or low supply rai ls, the current lim it lat c h is initially disabled. It is enabled at a preset time (nominally
2mS) after both t he LDOV and LDOEN rai ls rise
above t heir lockout points.
To be most effective, the l inear FET Rds(on) should
not be selected artificial ly low, the FET should be chosen so that, at m aximum requi r ed c ur r ent, it is almost
fully turned on
If, for ex ample, a linear supply of 1.5V at 4A is required f rom a 3.3V ± 5% r ail, max al lowable Rds(on)
would be.
Rds(on)max = (0.95*3.3-1. 5) /4 ≈ 400m
Ω
Temperature rise (oC)
FET type Top FET Bottom FET
IRL34025 67.6 53.2
IRL2203 47.6 37.2
Si4410 180.8 141.6
It is apparent that single SO-8 Si4410 are not adequate
for this applicat ion, but by usi ng par allel pairs in each position, power dissipation will be approximat ely halved and
temperature rise reduced by a factor of 4.
© 1999 SEMTECH CORP.
To allow for temperature effects 200mΩ would be a
suitable room temperature maxim um, allowing a peak
short circuit current of approx imately 15A f or a short
tim e before shutdown.
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652 MITCHELL ROA D NE WBURY P A RK CA 91320
Page 12
PRELIMINA RY - Dec ember 2, 1999
OUTLINE DRAWING
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
JEDEC MS-013AD
B17104B
SC1186
ECN99-600 9-22-99
ECN99-719 12-2-99
© 1999 SEMTECH CORP.
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652 MITCHELL ROA D NE WBURY P A RK CA 91320
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