Datasheet SC1185-1.5ACSW.TR, SC1185-1.5CSW.TR, SC1185-2.5ACSW.TR, SC1185-2.5CSW.TR Datasheet (Semtech Corporation)

PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER

© 1999 SEMTECH CORP.

PRELIMINARY - January 6, 1999

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC1185

SC1185A

1

DESCRIPTION

The SC1185 combines a synchronous voltage mode
controller with two low-dropout linear regulators
providing most of the circuitry necessary to
implement three DC/DC converters for powering
advanced microprocessors such as Pentium

®

II .

The SC1185 switching section features an integrated
5 bit D/A converter, pulse by pulse current limiting,
integrated power good signaling, and logic compatible
shutdown. The SC1185 switching section operates at
a fixed frequency of 140kHz, providing an optimum
compromise between size, efficiency and cost in the
intended application areas. The integrated D/A con­verter provides programmability of output voltage
from 2.0V to 3.5V in 100mV increments and 1.30V to

2.05V in 50mV increments with no external compo­nents.

The SC1185 linear sections are low dropout regula­tors supplying 1.5V for GTL bus and 2.5V for non­GTL I/O. The Reference voltage is made available for
external linear regulators.

Pentium is a registered trademark of Intel Corporation

TEL:[phone] FAX:[phone] WEB:http://www.semtech.com

BLOCK DIAGRAM

2.5V/ADJ.

1.5V/ADJ.

1.265V

FET

CONTROLLER

REF.

FET

CONTROLLER

REF.

VCC CS- CS+ EN

BSTH

DH

PGNDH

BSTL

DL

PGNDL

LDOV GATE2 LDOS2 AGNDREF

VID4
VID3
VID2
VID1
VID0

VOSENSE

PWRGOOD

LDOS1

GATE1

D/A

PIN CONFIGURATION

AGND

GATE1
LDOS1
LDOS2

VCC

REF

PWRGOOD

CS-

CS+

PGNDH

DH

PGNDL

1
2
3

LDOV

4
5
6
7
8

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

VOSENSE
EN
BSTH
BSTL
DL

VID0
VID1
VID2
VID3
VID4

GATE2

Top View

(24 Pin SOIC)

FEATURES

•

Synchronous design, enables no heatsink solution

•

95% efficiency (switching section)

•

5 bit DAC for output programmability

•

On chip power good function

•

Designed for Intel Pentium® ll requirements

•

1.5V, 2.5V @ 1% for linear section

•

1.265V ± 1.5% Reference available

APPLICATIONS

•

Pentium® ll microprocessor supplies

•

Flexible motherboards

•

1.3V to 3.5V microprocessor supplies

•

Programmable triple power supplies

ORDERING INFORMATION

Part Number

(1)

Package

Linear

Voltage

Temp.

Range (T

J

)

SC1185CSW SO-24 1.5V/2.5V 0° to 125°C
SC1185ACSW

(2)

SO-24 1.5V/2.5V 0° to 125°C

Note:
(1) Add suffix ‘TR’ for tape and reel.
(2) SC1185A provides improved output tolerance. See
Output Voltage Table.

PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER

© 1999 SEMTECH CORP.

PRELIMINARY - January 6, 1999

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC1185

SC1185A

2

Parameter Symbol Maximum Units

VCC to GND V

IN

-0.3 to +7 V
PGND to GND ± 1 V
BST to GND -0.3 to +15 V

Operating Temperature Range T

A

0 to +70 °C

Junction Temperature Range T

J

0 to +125 °C

Storage Temperature Range T

STG

-65 to +150 °C

Lead Temperature (Soldering) 10 seconds T

L

300 °C

Thermal Impedance Junction to Ambient

θ

JA

80 °C/W

Thermal Impedance Junction to Case

θ

JC

25 °C/W

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

Unless specified: VCC = 4.75V to 5.25V; GND = P

GND

= 0V; V

OSENSE

= VO; 0mV < (CS+-CS-) < 60mV ; LDOV = 11.4V to 12.6V; TA = 0 to 70°C

PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching Section

Output Voltage I

O

= 2A in Application Circuit See Output Voltage Table
Supply Voltage VCC 4.5 7 V
Supply Current VCC = 5.0V 8 15 mA
Load Regulation I

O

= 0.8A to 15A 1 %
Line Regulation ±0.15 %
Current Limit Voltage 60 70 85 mV
Oscillator Frequency 125 140 160 kHz
Oscillator Max Duty Cycle 90 95 %
Peak DH Sink/Source Current BSTH-DH = 4.5V, DH-PGNDH = 3.1V

DH-PGNDH = 1.5V1100

A

mA

Peak DL Sink/Source Current BSTL-DL = 4.5V, DL-PGNDL = 3.1V

DL-PGNDL = 1.5V1100

A

mA

Gain (A

OL

) VOSENSE to V

O

35 dB

VID Source Current

VIDx ≤ 2.4V

110 µA
VID Leakage VIDx = 5V 10 µA
Power good threshold voltage 88 112 %
Dead time 40 100 ns

Linear Sections

Quiescent current LDOV = 12V 5 mA
Output Voltage LDO1 2.469 2.500 2.531 V
Output Voltage LDO2 1.481 1.500 1.519 V
Reference Voltage

Iref ≤ 100µA

1.246 1.265 1.284 V

Gain (A

OL

) LDOS (1,2) to GATE (1,2) 90 dB

Load Regulation I

O

= 0 to 8A 0.3 %
Line Regulation 0.3 %
Output Impedance V

GATE

= 6.5V 1 1.5

k

Ω

Gate Pulldown Impedance GATE(1,2)-AGND;VCC=LDOV=0V 80 300 750

k

Ω

VOSENSE Impedance 10

k

Ω

PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER

© 1999 SEMTECH CORP.

PRELIMINARY - January 6, 1999

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC1185

SC1185A

3

Note:
(1) All logic level inputs and outputs are open
collector TTL compatible.

PIN DESCRIPTION

Pin Pin Name Pin Function

1 AGND Small Signal Analog and Digital Ground
2 GATE1 Gate Drive Output LDO1
3 LDOS1 Sense Input for LDO1
4 LDOS2 Sense Input for LDO2
5 VCC Input Voltage
6 REF Buffered Reference Voltage output

7 PWRGOOD

(1)

Open collector logic output, high if V

O

within 10% of setpoint

8 CS- Current Sense Input (negative)

9 CS+ Current Sense Input (positive)
10 PGNDH Power Ground for High Side Switch
11 DH High Side Driver Output
12 PGNDL Power Ground for Low Side Switch
13 DL Low Side Driver Output
14 BSTL Supply for Low Side Driver
15 BSTH Supply for High Side Driver
16 EN

(1)

Logic low shuts down the converter;
High or open for normal operation.

17 VOSENSE Top end of internal feedback chain
18

VID4

(1)

Programming Input (MSB)

19

VID3

(1)

Programming Input

20

VID2

(1)

Programming Input

21

VID1

(1)

Programming Input

22

VID0

(1)

Programming Input (LSB)

23 LDOV +12V for LDO section
24 GATE2 Gate Drive Output LDO2

AGND

GATE1
LDOS1
LDOS2

VCC

REF

PWRGOOD

CS-

CS+

PGNDH

DH

PGNDL

1
2
3

LDOV

4
5
6
7
8

9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

VOSENSE
EN
BSTH
BSTL
DL

VID0
VID1
VID2
VID3
VID4

GATE2

Top View

(24 Pin SOIC)

PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER

© 1999 SEMTECH CORP.

PRELIMINARY - January 6, 1999

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC1185

SC1185A

4

OUTPUT VOLTAGE

Unless specified: 4. 75V < VCC < 5.25V; GND = PGND = 0V; VOSENS E = VO; 0mV < (CS+-CS-) < 60mV ; = 0°C < Tj < 85°C

Standard “A” Version

PARAMETER VID

43210

MIN TYP MAX MIN TYP MAX UNITS

Output Voltage 01111 1.277 1.300 1.323 1.287 1.300 1.313 V

01110 1.326 1.350 1.374 1.337 1.350 1.364
01101 1.375 1.400 1.425 1.386 1.400 1.414
01100 1.424 1.450 1.476 1.436 1.450 1.465
01011 1.478 1.500 1.523 1.485 1.500 1.515
01010 1.527 1.550 1.573 1.535 1.550 1.566
01001 1.576 1.600 1.624 1.584 1.600 1.616
01000 1.625 1.650 1.675 1.634 1.650 1.667
00111 1.675 1.700 1.726 1.683 1.700 1.717
00110 1.724 1.750 1.776 1.733 1.750 1.768
00101 1.782 1.800 1.818 1.782 1.800 1.818
00100 1.832 1.850 1.869 1.832 1.850 1.869
00011 1.881 1.900 1.919 1.881 1.900 1.919
00010 1.931 1.950 1.970 1.931 1.950 1.970
00001 1.980 2.000 2.020 1.980 2.000 2.020
00000 2.030 2.050 2.071 2.030 2.050 2.071
11111 1.970 2.000 2.030 1.970 2.000 2.030
11110 2.069 2.100 2.132 2.069 2.100 2.132
11101 2.167 2.200 2.233 2.167 2.200 2.233
11100 2.266 2.300 2.335 2.266 2.300 2.335
11011 2.364 2.400 2.436 2.364 2.400 2.436
11010 2.463 2.500 2.538 2.463 2.500 2.538
11001 2.561 2.600 2.639 2.561 2.600 2.639
11000 2.660 2.700 2.741 2.660 2.700 2.741
10111 2.758 2.800 2.842 2.758 2.800 2.842
10110 2.842 2.900 2.958 2.842 2.900 2.958
10101 2.940 3.000 3.060 2.940 3.000 3.060
10100 3.038 3.100 3.162 3.038 3.100 3.162
10011 3.136 3.200 3.264 3.136 3.200 3.264
10010 3.234 3.300 3.366 3.234 3.300 3.366
10001 3.332 3.400 3.468 3.332 3.400 3.468
10000 3.430 3.500 3.570 3.430 3.500 3.570

PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER

© 1999 SEMTECH CORP.

PRELIMINARY - January 6, 1999

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC1185

SC1185A

5

VCC_CORE

2.5V

1.5V

GND

VID0

VID1

VID2

VID3

VID4

12V

5V

EN

REF

PWRGD

3.3V

C1

0.1uF

L1

4uH

R4

5mOhm

C18

0.1uF

+

C14

1500uF

+

C15

1500uF

+

C16

1500uF

+

C17

1500uF

+

C3

1500uF

+

C2

1500uF

R1

10

C13

0.1uF

Q2

IRL34025

Q1

IRL34025

C5

0.1uF

Q3

IRLML2803

+

C11

330uF

R5

2.32k

U1

SC1185CSW

AGND

1

VCC5REF

6

PWRGOOD

7

CS-

8

CS+

9

PGNDH

10DH11

BSTH

15

EN

16

VO SENSE

17

VID4

18

VID319VID220VID121VID0

22

DL

13

PGNDL

12

BSTL

14

GATE224GATE1

2

LDOV

23

LDOS1

3

LDOS2

4

Q4

IRFZ14S

+

C9

1000uF

R6

1.00k

C21

+

330uF

R16

10k

APPLICATION CIRCUIT

PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER

© 1999 SEMTECH CORP.

PRELIMINARY - January 6, 1999

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC1185

SC1185A

6

MATERIALS LIST

Qty. Reference Part/Description Vendor Notes

4 C1,C5,C13,C18 0.1µF Ceramic Various
6 C2,C3,C14-C17 1500µF/6.3V SANYO MV-GX or equiv. Low ESR
1 C9 1000µF
2 C11,C21 330µF/6.3V Various
1 L1 4µH 8 Turns 16AWG on MICROMETALS T50-52D core
2 Q1,Q2 See notes See notes FET selection requires trade-off between efficiency and

cost. Absolute maximum R

DS(ON)

= 22 mΩ for Q1,Q2

1 Q3 IRLML2803 IR

.25Ω 30V SOT23 (or equavilent)
1 Q4 IRFZ14S IR Or equivalent
1R4

5m

Ω

IRC OAR-1 Series

1R5

2.32kΩ, 1%, 1/8W

Various

1R6

1kΩ, 1%, 1/8W

Various

1R1

10Ω, 5%, 1/8W

Various

1 U1 SC1185CSW SEMTECH

PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER

© 1999 SEMTECH CORP.

PRELIMINARY - January 6, 1999

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC1185

SC1185A

7

70%

75%

80%

85%

90%

95%

0 2 4 6 8 10121416

Io (Amps)

Efficiency

3.5V Std

3.5V Sync

3.5V Sync Lo Rds

70%

75%

80%

85%

90%

95%

0 2 4 6 8 10 12 14 16

Io (Amps)

Efficiency

2.5V Std

2.5V Sync

2.5V Sync Lo Rds

70%

75%

80%

85%

90%

95%

0 2 4 6 8 10 12 14 16

Io (Amps)

Efficiency

2.8V Std

2.8V Sync

2.8V Sync Lo Rds

70%

75%

80%

85%

90%

95%

0 2 4 6 8 10 12 14 16

Io (Amps)

Efficiency

2.0V Std

2.0V Sync

2.0V Sync Lo Rds

Typical Ripple, Vo=2.8V, Io=10A

Typical Efficiency at Vo=2.5V

Typical Efficiency at Vo=3.5V Typical Efficiency at Vo=2.8V

Typical Efficiency at Vo=2.0V

Transient Response Vo=2.8V, Io=300mA to 10A

PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER

© 1999 SEMTECH CORP.

PRELIMINARY - January 6, 1999

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC1185

SC1185A

8

LAYOUT GUIDELINES

Careful attention to layout requirements are necessary
for successful implementation of the SC1185 PWM
controller. High currents switching at 140kHz are pre­sent in the application and their effect on ground plane
voltage differentials must be understood and mini­mized.

1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such
as to not unnecessarily compromise ground plane in­tegrity. Isolated or semi-isolated areas of the ground
plane may be deliberately introduced to constrain
ground currents to particular areas, for example the in­put capacitor and bottom FET ground.

2). The loop formed by the Input Capacitor(s) (Cin), the
Top FET (Q1) and the Bottom FET (Q2) must be kept

as small as possible. This loop contains all the high cur­rent, fast transition switching. Connections should be as
wide and as short as possible to minimize loop induc­tance. Minimizing this loop area will a) reduce EMI, b)
lower ground injection currents, resulting in electrically
“cleaner” grounds for the rest of the system and c) mini­mize source ringing, resulting in more reliable gate
switching signals.

3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper
region. It should be as short as practical. Since this
connection has fast voltage transitions, keeping this
connection short will minimize EMI. The connection be­tween the output inductor and the sense resistor should
be a wide trace or copper area, there are no fast volt­age or current transitions in this connection and length
is not so important, however adding unnecessary
impedance will reduce efficiency.

Vout

12V IN

3.3V Vo Lin1

Vo Lin2

5V

4uH

5mOhm

+

Cout

+

Cin

10

Q2

0.1uF

Q3

+

Cout Lin1

2.32k

Q4

+

Cout Lin2

1.00k

+

Cin Lin

SC1185

AGND

1

VCC

5

REF

6

PWRGOOD

7

CS-

8

CS+

9

PGNDH

10

DH

11

BSTH

15

EN

16

VOSENSE

17

VID4

18

VID3

19

VID2

20

VID1

21

VID0

22

DL

13

PGNDL

12

BSTL

14

GATE2

24

GATE1

2

LDVO

23

LDOS1

3

LDOS2

4 Q1

0.1uF

Heavy lines indicate
high current paths.

Layout diagram for the SC1185

PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER

© 1999 SEMTECH CORP.

PRELIMINARY - January 6, 1999

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC1185

SC1185A

9

Vout

5V

+

+

4) The Output Capacitor(s) (Cout) should be located
as close to the load as possible, fast transient load
currents are supplied by Cout only, and connections
between Cout and the load must be short, wide cop­per areas to minimize inductance and resistance.

5) The SC1185 is best placed over a quiet ground
plane area, avoid pulse currents in the Cin, Q1, Q2
loop flowing in this area. PGNDH and PGNDL should
be returned to the ground plane close to the package.
The AGND pin should be connected to the ground
side of (one of) the output capacitor(s). If this is not
possible, the AGND pin may be connected to the
ground path between the Output Capacitor(s) and the
Cin, Q1, Q2 loop. Under no circumstances should
AGND be returned to a ground inside the Cin, Q1, Q2
loop.

6) Vcc for the SC1185 should be supplied from the 5V

supply through a 10Ω resistor, the Vcc pin should be
decoupled directly to AGND by a 0.1µF ceramic ca­pacitor, trace lengths should be as short as possible.

7) The Current Sense resistor and the divider across
it should form as small a loop as possible, the traces
running back to CS+ and CS- on the SC1185 should
run parallel and close to each other. The 0.1µF ca­pacitor should be mounted as close to the CS+ and
CS- pins as possible.

8) Ideally, the grounds for the two LDO sections
should be returned to the ground side of (one of) the
output capacitor(s).

Currents in various parts of the power section

PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER

© 1999 SEMTECH CORP.

PRELIMINARY - January 6, 1999

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC1185

SC1185A

10

COMPONENT SELECTION

SWITCHING SECTION
OUTPUT CAPACITORS - Selection begins with the
most critical component. Because of fast transient load
current requirements in modern microprocessor core
supplies, the output capacitors must supply all transient
load current requirements until the current in the output
inductor ramps up to the new level. Output capacitor
ESR is therefore one of the most important criteria. The
maximum ESR can be simply calculated from:

step current Transient I

excursion voltage transient MaximumV

Where

I

V

R

t

t

t

t

ESR

=

=

≤

Each Capacitor Total

Technology C

(µF)

ESR

(mΩ)

Qty.

Rqd.C(µF)

ESR

(mΩ)

Low ESR Tantalum 330 60 6 2000 10
OS-CON 330 25 3 990 8.3
Low ESR Aluminum 1500 44 5 7500 8.8

()

OIN

t

ESR

VV

I

CR

L

−≤

OSC

IN

L

fL4

V

I

RIPPLE

⋅⋅

=

IN

O

)on(DS

2
OCOND

V

V

cycleduty =

where

RIP

≈δ

δ⋅⋅=

2

INOSW

10VIP

−

⋅⋅=

4

f)tt(VI

P

OSCfrINO

SW

⋅+⋅⋅

=

OSCINRRRR

fVQP

⋅⋅=

For example, to meet a 100mV transient limit with a
10A load step, the output capacitor ESR must be less
than 10mΩ. To meet this kind of ESR level, there are
three available capacitor technologies.

The choice of which to use is simply a cost/perfor­mance issue, with Low ESR Aluminum being the
cheapest, but taking up the most space.

INDUCTOR - Having decided on a suitable type and
value of output capacitor, the maximum allowable
value of inductor can be calculated. Too large an in­ductor will produce a slow current ramp rate and will
cause the output capacitor to supply more of the tran­sient load current for longer - leading to an output volt­age sag below the ESR excursion calculated above.
The maximum inductor value may be calculated from:

The calculated maximum inductor value assumes 100%
duty cycle, so some allowance must be made. Choosing
an inductor value of 50 to 75% of the calculated maxi­mum will guarantee that the inductor current will ramp

fast enough to reduce the voltage dropped across the
ESR at a faster rate than the capacitor sags, hence en­suring a good recovery from transient with no additional
excursions.
We must also be concerned with ripple current in the
output inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current.
Note that most of the output voltage ripple is produced
by the inductor ripple current flowing in the output capac­itor ESR. Ripple current can be calculated from:

Ripple current allowance will define the minimum permit­ted inductor value.

POWER FETS - The FETs are chosen based on several
criteria with probably the most important being power
dissipation and power handling capability.
TOP FET - The power dissipation in the top FET is a
combination of conduction losses, switching losses and
bottom FET body diode recovery losses.
a) Conduction losses are simply calculated as:

b) Switching losses can be estimated by assuming a
switching time, if we assume 100ns then:

or more generally,

c) Body diode recovery losses are more difficult to esti­mate, but to a first approximation, it is reasonable to as­sume that the stored charge on the bottom FET body
diode will be moved through the top FET as it starts to
turn on. The resulting power dissipation in the top FET
will be:

To a first order approximation, it is convenient to only
consider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:

PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER

© 1999 SEMTECH CORP.

PRELIMINARY - January 6, 1999

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC1185

SC1185A

11

)1(RIP

)on(DS

2
OCOND

δ−⋅⋅=

FET type

R

DS(on)

(mΩ)

P

D

(W) Package

IRL34025 15 1.69 D

2

PAK

IRL2203 10.5 1.19 D

2

PAK

Si4410 20 2.26 SO-8

FET type

R

DS(on)

(mΩ)

P

D

(W) Package

IRL34025 15 1.33 D

2

PAK

IRL2203 10.5 0.93 D

2

PAK

Si4410 20 1.77 SO-8

BOTTOM FET - Bottom FET losses are almost entirely
due to conduction. The body diode is forced into conduc­tion at the beginning and end of the bottom switch con­duction period, so when the FET turns on and off, there
is very little voltage across it, resulting in low switching
losses. Conduction losses for the FET can be deter­mined by:

For the example above:

Each of the package types has a characteristic thermal
impedance, for the TO-220 package, thermal impedance
is mostly determined by the heatsink used. For the sur­face mount packages on double sided FR4, 2 oz printed
circuit board material, thermal impedances of 40

o

C/W

for the D

2

PAK and 80oC/W for the SO-8 are readily
achievable. The corresponding temperature rise is de­tailed below:

Temperature rise (oC)
FET type Top FET Bottom FET
IRL34025 67.6 53.2

IRL2203 47.6 37.2
Si4410 180.8 141.6

It is apparent that single SO-8 Si4410 are not adequate for
this application, but by using parallel pairs in each posi­tion, power dissipation will be approximately halved and
temperature rise reduced by a factor of 4.

INPUT CAPACITORS - since the RMS ripple current in
the input capacitors may be as high as 50% of the out­put current, suitable capacitors must be chosen ac­cordingly. Also, during fast load transients, there may
be restrictions on input di/dt. These restrictions require
useable energy storage within the converter circuitry,
either as extra output capacitance or, more usually,
additional input capacitors. Choosing low ESR input
capacitors will help maximize ripple rating for a given
size.

Using 1.5X Room temp R

DS(ON)

to allow for temperature

rise.

PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER

© 1999 SEMTECH CORP.

PRELIMINARY - January 6, 1999

652 MITCHELL ROAD NEWBURY PARK CA 91320

SC1185

SC1185A

12

OUTLINE DRAWING

JEDEC MS-013AD

B17104B