Page 1
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1998 SEMTECH CORP.
August 25, 1998
652 MITCHELL ROA D NE WBURY PARK CA 91320
SC1182/3
1
ORDERING INFORMATION
DESCRIPTION
The SC1182/3 combines a synchronous voltage mode
controller with two low-dropout linear regulators
providing most of t he c ircuitry necessary to implement
three DC/DC converters for powering advanced
micr opr oc essors such as Pentium
®
II (Kl amath) or
Deschutes.
The SC1182/3 switchi ng sect ion features an integrat -
ed 5 bit D/A c onverter, pulse by pulse current limiting,
integrated power good signaling, and logic compatible
shutdown. The SC1182/3 switching sect ion operates
at a fixed frequency of 200kHz, providing an optimum
compromise between size, efficiency and cost in the
intended application areas. The int egr ated D/A converter provides programmability of output voltage
from 2.0V to 3.5V in 100m V increments and 1.30V to
2.05V in 50mV increments with no external components.
The SC1182/3 linear sections are low dropout regulators. The SC1182 supplies 1.5V for GTL bus and 2.5V
for non-G TL I/O.
For the SC1183 both LDO’s are adjustable.
Pentium is a registered tradem ark of Intel Corporation
TEL:805-498-2111 F A X:805- 498- 3804 WEB:http://www.semtech.com
BLOCK DIAGRAM
2.5V/ADJ.
1.5V/ADJ.
1.265V
FET
CONTROLLER
REF.
FET
CONTROLLER
REF.
LDOV
PIN CONFIGURATION
AGND
GATE1
LDOS1
LDOS2
VCC
OVP
PWRGOOD
CS-
CS+
PGNDH
DH
PGNDL
1
2
3
LDOV
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VOSENSE
EN
BSTH
BSTL
DL
VID0
VID1
VID2
VID3
VID4
GATE2
Top View
(24 Pin SOIC)
FEATURES
•
Synchronous design, enables no heatsi nk sol ution
• 95% efficiency (switching sect ion)
• 5 bit DAC for output programmability
• On chip power good function
• Designed for I ntel Pentium
®
ll VRM8.1 require-
ments
• 1.5V, 2.5V or A dj. @ 1% for linear section
APPLICATIONS
•
Pentium® ll or Deschutes microprocessor supplies
• Flex ible motherboards
• 1.3V to 3.5V microprocessor supplies
• Programmable triple power suppli es
Part Number
(1)
Package
Linear
Voltage
Temp.
Range (T
J
)
SC1182CSW SO-24 1.5V/2.5V 0° to 125°C
SC1183CSW SO-24 Adj. 0° to 125°C
Note:
(1) Add suffix ‘TR’ f or tape and reel.
Page 2
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1998 SEMTECH CORP.
August 25, 1998
652 MITCHELL ROA D NE WBURY PARK CA 91320
SC1182/3
2
Parameter Symbol Maximum Units
V
CC
to GND V
IN
-0.3 to +7 V
PGND to GND ± 1 V
BST to GND -0.3 to +15 V
Operating Temperature Range T
A
0 to +70 °C
Junction T emperature Range T
J
0 to +125 °C
Storage Temperature Range T
STG
-65 to +150 °C
Lead Temperat ur e ( S oldering) 10 seconds T
L
300 °C
Thermal Impedance Junction to Ambient
θ
JA
80 °C/W
Thermal Impedance Junction to Case
θ
JC
25 °C/W
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
Unless specified: VCC = 4.75V to 5.25V; GND = P
GND
= 0V; V
OSENSE
= VO; 0mV < (CSp-CSm) < 60mV; LDOV = 11.4V to 12.6V; TA = 25°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching Section
Output Voltage I
O
= 2A See Note 1.
Supply Vol tage V
CC
4.2 7 V
Supply Current V
CC
= 5.0 8 15 mA
Load Regulation I
O
= 0.8A to 15A 1 %
Line Regulation 0.5 %
Minimum operating voltage 4.2 V
Current Limit Voltage 60 70 80 mV
Oscillator Frequency 180 200 220 kHz
Oscillator Max Duty Cycle 90 95 %
Peak DH Sink/ S our c e Cur r ent BSTH-DH = 4. 5V , DH-PGNDH = 2V 1 A
Peak DL Sink/ S our c e Cur r ent BSTL-DL = 4. 5V , DL-PGNDL = 2V 1 A
Output Voltage Tempco 30 100 ppm/
o
C
Gain (A
OL
)V
OSENSE
to V
O
35 dB
OVP threshold voltage 120 %
OVP source current V
OVP
= 3.0V 10 mA
Power good threshold voltage 88 112 %
Dead tim e 50 100 ns
Linear Sections
Quiescent curr ent LDOV = 12V 5 mA
Output Voltage (LDO1 SC1182) 2.475 2.500 2. 525 V
Output Voltage (LDO2 SC1182) 1.485 1.500 1. 515 V
Reference Voltage (SC1183) 1.252 1.265 1. 278 V
Feedback Pin B ias Current (SC1183) 10 uA
Gain (A
OL
) LDOS (1,2) to GATE (1,2) 90 dB
Load Regulation I
O
= 0 to 8A
(2)
0.3 %
Line Regulation 0.3 %
Output Impedance 200
Ω
Notes:
(1) See Output V oltage table.
(2) In application circuit.
Page 3
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1998 SEMTECH CORP.
August 25, 1998
652 MITCHELL ROA D NE WBURY PARK CA 91320
SC1182/3
3
Note:
(1) All logic lev el inputs and outputs are open
collector TTL compatible.
PIN DESCRIPTION
Pin Pin Name Pin Function
1 AGND Small Signal Analog and Di gital Ground
2 GATE1 Gate Drive Output LDO1
3 LDOS1 Sense Input for LDO1
4 LDOS2 Sense Input for LDO2
5 VCC Input Voltage
6 OVP High Signal out i f V
O
>setpoint +20%
7 PWRGOOD
(1)
Open coll ec tor logic output, high if V
O
within 10% of setpoint
8 CS- Current Sense Input (negative)
9 CS+ Current Sense Input (positive)
10 PGNDH Power Ground for High Side Switch
11 DH High Side Driver Output
12 PGNDL Power Ground for Low Side Switch
13 DL Low Side Driver Output
14 BSTL Supply for Low Side Driver
15 BSTH Supply for High Side Driver
16 EN
(1)
Logic low shuts down the conv er ter;
High or open f or nor mal operation.
17 VOSENS E Top end of internal feedback c hain
18
VID4
(1)
Programming Input (MSB)
19
VID3
(1)
Programming Input
20
VID2
(1)
Programming Input
21
VID1
(1)
Programming Input
22
VID0
(1)
Programming Input (LSB)
23 LDOV +12V for LDO section
24 GATE 2 Gate Drive Output LDO2
AGND
GATE1
LDOS1
LDOS2
VCC
OVP
PWRGOOD
CS-
CS+
PGNDH
DH
PGNDL
1
2
3
LDOV
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VOSENSE
EN
BSTH
BSTL
DL
VID0
VID1
VID2
VID3
VID4
GATE2
Top View
(24 Pin SOIC)
Page 4
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1998 SEMTECH CORP.
August 25, 1998
652 MITCHELL ROA D NE WBURY PARK CA 91320
SC1182/3
4
OUTPUT VOLTAGE
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; V
OSENSE
= VO; 0mV < (CSp-CSm) < 60mV; TA = 25°C
PARAMETER CONDITIONS VID
43210
MIN TYP MAX UNITS
Output Voltage I
O
= 2A in Application circ uit 01111 1.287 1.300 1.313 V
01110 1.336 1.350 1.364
01101 1.386 1.400 1.414
01100 1.435 1.450 1.465
01011 1.485 1.500 1.515
01010 1.534 1.550 1.566
01001 1.584 1.600 1.616
01000 1.633 1.650 1.667
00111 1.683 1.700 1.717
00110 1.732 1.750 1.768
00101 1.782 1.800 1.818
00100 1.831 1.850 1.869
00011 1.881 1.900 1.919
00010 1.930 1.950 1.970
00001 1.980 2.000 2.020
00000 2.029 2.050 2.071
11111 1.980 2.000 2.020
11110 2.079 2.100 2.121
11101 2.178 2.200 2.222
11100 2.277 2.300 2.323
11011 2.376 2.400 2.424
11010 2.475 2.500 2.525
11001 2.574 2.600 2.626
11000 2.673 2.700 2.727
10111 2.772 2.800 2.828
10110 2.871 2.900 2.929
10101 2.970 3.000 3.030
10100 3.069 3.100 3.131
10011 3.168 3.200 3.232
10010 3.267 3.300 3.333
10001 3.366 3.400 3.434
10000 3.465 3.500 3.535
Page 5
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1998 SEMTECH CORP.
August 25, 1998
652 MITCHELL ROA D NE WBURY PARK CA 91320
SC1182/3
5
VCC_CORE
VLIN1
VLIN2
GND
VID0 VID1 VID2 VID3 VID4
12V 5V
EN
OVP
PWRGD
5V 5V
C1
0.1uF
L1
4uH
R4
5mOhm
C18
0.1uF
+
C14
1500uF
+
C15
1500uF
+
C16
1500uF
+
C17
1500uF
+
C3
1500uF
+
C2
1500uF
R1
10
C13
0.1uF
Q2
BUK556
Q1
BUK556
C5
0.1uF
Q3
BUK556
+
C11 330uF
+
C12 330uF
R5 2.32k
U1
SC1182/3CSW
AGND
1
VCC
5
OVP
6
PWRGOOD
7
CS-
8
CS+
9
PGNDH
10
DH
11
BSTH
15
EN
16
VO SENSE
17
VID4
18
VID3
19
VID2
20
VID1
21
VID0
22
DL
13
PGNDL
12
BSTL
14
GATE2
24
GATE1
2
LDOV
23
LDOS1
3
LDOS2
4
Q4
BUK556
+
C9
330uF
+
C10 330uF
R6 1.00k
R12
R13
*
R15
R14
+
C21
330uF
+
C22 330uF
R16
10k
*
*
*
NOTE: FOR SC1182, R12,R13,R14 AND R15 ARE NOT REQUIRED.
CONNECT LDOS1 (PIN3) AND LDOS2 (PIN4)
DIRECTLY GENERATE 2.5V AND 1.5V OUTPUTS.
TO VLIN1 AND VLIN2 RESPECTIVELY TO
* SEE "SETTING LDO OUTPUT VOLTAGE" TABLE
R17
100K
R18
100K
APPLICATION CIRCUIT
Page 6
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1998 SEMTECH CORP.
August 25, 1998
652 MITCHELL ROA D NE WBURY PARK CA 91320
SC1182/3
6
SETTING LDO OUTPUT VOLTAGE
MATERIALS LIST
Qty. Reference Part/Description Vendor Notes
4 C1,C5,C13,
C18
0.1µF Ceramic Various
6 C2,C3,C14-
C17
1500µF/6.3V SANYO MV-GX or equiv. Low ESR
6 C9-C12,
C21, C22
330µF/6. 3V Various
1 L1 4µH 8 Turns 16AWG on MICROMETA LS T50-52D core
4 Q1,Q2,Q3,Q4See notes S ee notes FET selection requires trade-off between efficiency and
cost. Absolute maximum R
DS(ON)
= 22 mΩ for Q1,Q2
1R4
5m
Ω
IRC OAR-1 Series
1R5
2.32kΩ, 1%, 1/8W
Various
1R6
1kΩ, 1%, 1/8W
Various
1R1
10Ω, 5%, 1/8W
Various
1 R12 1%, 1/8W Various See Table Below (Not required f or S C1182)
1 R13 1%, 1/8W Various See Table Below (Not required f or S C1182)
1 R14 1%, 1/8W Various See Table Below (Not required f or S C1182)
1 R15 1%, 1/8W Various See Table Below (Not required f or S C1182)
2 R17, R18 100K, 5%, 1/8W Various
1 U1 SC1182/ 3CSW SEMTECH
error tsignifican
cause not does term )RI( the that
so enoughlow be must R and R
ionclarificat for diagram layout See
resistor feedback Bottom R
resistor feedback Top R
current bias pin FeedbackI
:Where
)RI(
R
)RR(265.1
V
AFB
BA
B
A
FB
AFB
B
BA
OUT
⋅
=
=
=
⋅+
+⋅
=
R
B
R
A
VOUT LDO1 (LDO2) R12 ( R14) R13 (R15)
3.45V
105
Ω
182
Ω
3.30V
105
Ω
169
Ω
3.10V
102
Ω
147
Ω
2.90V
100
Ω
130
Ω
2.80V
100
Ω
121
Ω
2.50V
100
Ω
97.6
Ω
1.50V
100
Ω
18.7
Ω
Page 7
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1998 SEMTECH CORP.
August 25, 1998
652 MITCHELL ROA D NE WBURY PARK CA 91320
SC1182/3
7
70%
75%
80%
85%
90%
95%
0 2 4 6 8 10 12 14 16
Io (Amps)
Efficiency
3.5V Std
3.5V Sync
3.5V Sync Lo Rds
70%
75%
80%
85%
90%
95%
0246810121416
Io (Amps)
Efficiency
2.5V Std
2.5V Sync
2.5V Sync Lo Rds
70%
75%
80%
85%
90%
95%
0 2 4 6 8 10 12 14 16
Io (Amps)
Efficiency
2.8V Std
2.8V Sync
2.8V Sync Lo Rds
70%
75%
80%
85%
90%
95%
0 2 4 6 8 10 12 14 16
Io (Amps)
Efficiency
2.0V Std
2.0V Sync
2.0V Sync Lo Rds
Typical Ripple, Vo=2.8V, Io=10A
Typical Efficiency at Vo=2.5V
Typical Efficiency at Vo=3.5V Typical Efficiency at Vo=2.8V
Typical Efficiency at Vo=2.0V
Transient Response Vo=2.8V, Io=300mA to 10A
Page 8
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1998 SEMTECH CORP.
August 25, 1998
652 MITCHELL ROA D NE WBURY PARK CA 91320
SC1182/3
8
LAYOUT GUIDELINES
Careful attention to layout r equirements are necessary
for successful implementation of the SC1182/ 3 P WM
controller. High currents switching at 200k Hz are present in the application and their effect on ground plane
voltage diff er entials must be understood and minimized.
1). The high power part s of the circuit shoul d be laid
out first. A ground plane should be used, the num ber
and position of ground plane interruptions should be
such as to not unnecessarily compromise ground plane
integri ty. Isolated or semi- isolated areas of the ground
plane may be deliberately introduced to constrain
ground currents to part icular areas, for example the
input capacitor and bottom FET ground.
2). The loop formed by the Input Capac itor(s) (Cin), the
Top FET (Q1) and the Bottom FE T (Q2) must be kept
as small as possible. This loop contains all the high
current, fast transition switchi ng. Connections should
be as wide and as short as possible to minimize loop
inductance. M inimizi ng this loop area will a) reduce
EMI, b) lower ground injection currents, result ing in
electrically “cleaner” gr ounds for the rest of the system
and c) mi nimize source ringing, resulting in more reliable gate switchi ng si gnals.
3). The connect ion between the junction of Q1, Q2 and
the output i nduc tor should be a wide trace or copper
region. It should be as short as practi c al. Since this
connection has fast voltage tr ansi tions, keeping this
connection short will minimize EMI. The connection
between the output induc tor and the sense resistor
should be a wide trace or copper ar ea, there are no
fast voltage or current t r ansi tions in this connection
and length is not so i mportant, however adding unnecessary impedance will reduce efficiency.
Vout
12V IN
5V Vo Lin1
Vo Lin2
5V
4uH
5mOhm
+
Cout
+
Cin
10
Q2
0.1uF
Q3
+
Cout Lin1
2.32k
Q4
+
Cout Lin2
1.00k
RB1
RA1
RA2
RB2
+
Cin Lin
SC1182/3
AGND
1
VCC
5
OVP
6
PWRGOOD
7
CS-
8
CS+
9
PGNDH
10
DH
11
BSTH
15
EN
16
VO SENSE
17
VID4
18
VID3
19
VID2
20
VID1
21
VID0
22
DL
13
PGNDL
12
BSTL
14
GATE2
24
GATE1
2
LDVO
23
LDOS1
3
LDOS2
4 Q1
0.1uF
Heavy lines indicate
high current paths.
are not required. LDOS1 connects to
For SC1182, RA1, RA2, RB1 and RB2
Vo Lin1, LDOS2 connects to Vo Lin2
Layout diagram for the SC1182/3
Page 9
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1998 SEMTECH CORP.
August 25, 1998
652 MITCHELL ROA D NE WBURY PARK CA 91320
SC1182/3
9
Vout
5V
+
+
4) The Output Capac itor(s) (Cout) should be locat ed
as close to the load as possible, fast transient load
currents are supplied by Cout only, and connections
between Cout and the load must be short, wide copper areas to mi nimize induct anc e and r esi stanc e.
5) The SC1182/3 i s best pl ac ed over a quiet ground
plane area, avoid pulse currents in t he Cin, Q1, Q2
loop flowing in this area. PGNDH and PGNDL should
be returned to the gr ound plane close to the package.
The AGND pin shoul d be c onnec ted to the ground
side of (one of) the output capacitor(s). If thi s i s not
possible, the AG ND pin may be connected to the
ground path between the Output Capacitor(s) and the
Cin, Q1, Q2 loop. Under no circumstances should
AGND be returned t o a gr ound inside the Cin, Q1, Q 2
loop.
6) Vcc for the SC1182/3 shoul d be supplied from the
5V supply through a 10Ω resistor, the Vcc pin should
be decoupled direc tly to AGND by a 0.1µF ceramic
capacitor, trace lengths should be as short as possi-
ble.
7) The Current Sense resistor and the divider ac r oss
it should form as small a l oop as possible, the traces
running back to CS + and CS- on the SC1182/3
should run parall el and close to each other. The
0.1µF capacit or shoul d be mounted as close to the
CS+ and CS- pins as possible.
8) Ideall y , the grounds for the two LDO sections
should be returned to t he gr ound si de of (one of) the
output capaci tor(s).
Currents in various parts of the power section
Page 10
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1998 SEMTECH CORP.
August 25, 1998
652 MITCHELL ROA D NE WBURY PARK CA 91320
SC1182/3
10
COMPONENT SELECTION
SWITCHING SECTION
OUTPUT CAPACITORS - Selection begins with the
most cri tical component. Because of fast transient load
current requi r ements in modern microprocessor core
supplies, the output capacitors must supply al l transient
load current r equirements until the current in the output
inductor ramps up to the new level. Output capacitor
ESR is therefore one of the most important criteria. The
maximum ESR can be simply calculat ed from:
step current Transient I
excursion voltage transient MaximumV
Where
I
V
R
t
t
t
t
ESR
=
=
≤
Each Capacitor Total
Technology C
(µF)
ESR
(mΩ)
Qty.
Rqd.C(µF)
ESR
(mΩ)
Low ESR Tantalum 330 60 6 2000 10
OS-CON 330 25 3 990 8.3
Low ESR Aluminum 1500 44 5 7500 8.8
()
OIN
t
ESR
VV
I
CR
L
−≤
OSC
IN
L
fL4
V
I
RIPPLE
⋅⋅
=
IN
O
)on(DS
2
OCOND
V
V
cycleduty =
where
RIP
≈δ
δ⋅⋅=
2
INOSW
10VIP
−
⋅⋅=
4
f)tt(VI
P
OSCfrINO
SW
⋅+⋅⋅
=
OSCINRRRR
fVQP
⋅⋅=
For example, to meet a 100mV transient li mit with a
10A load step, the output capacitor ESR must be less
than 10mΩ. To meet this kind of ESR level, t her e ar e
three available capacitor technologies.
The choice of which to use is simply a cost/performance issue, with Low ESR Aluminum bei ng the
cheapest, but taking up the most space.
INDUCTOR - Having decided on a suitable type and
value of output capacitor, the maximum allowable
value of inductor can be calculated. Too lar ge an inductor will produce a slow current ramp rate and will
cause the output capacitor to supply more of the transient load curr ent for longer - leading to an output voltage sag below the ESR excursi on c alculated above.
The maximum induc tor value m ay be c alculated from:
The calculated maximum inductor value assumes 100%
duty cycle, so some allowance must be made. Choosing
an inductor value of 50 to 75% of the calculat ed maximum will guarantee that the inductor c ur r ent will ramp
fast enough to reduc e the voltage dropped acr oss the
ESR at a f aster r ate than the capacitor sags, hence ensuring a good recovery from t r ansi ent with no additional
excursions.
We must also be concerned with rippl e c ur r ent in the
output inductor and a general rule of thumb has been to
allow 10% of maximum output current as rippl e c ur r ent.
Note that most of the output voltage ripple is produced
by the induct or r ipple current flowing in the output capacitor ES R. Ripple current can be calculated from:
Ripple current allowance will define the minimum permit ted inductor value.
POWER FETS - The FETs are chosen based on several cri teria with probably the most important being
power dissipation and power handli ng c apability.
TOP FET - The power dissipation in the t op FET is a
combination of conducti on losses, switching l osses and
bottom FET body diode recovery losses.
a) Conduction losses are simply c alculated as:
b) Switching losses can be estimated by assuming a
switching ti me, if we assume 100ns then:
or more generally,
c) Body diode rec overy losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stor ed c har ge on the bottom FET body
diode will be moved through the top FET as it start s to
turn on. The resul ting power dissipation in the t op FET
will be:
To a first order approxim ation, it is convenient to only
consider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:
Page 11
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1998 SEMTECH CORP.
August 25, 1998
652 MITCHELL ROA D NE WBURY PARK CA 91320
SC1182/3
11
)1(RIP
)on(DS
2
OCOND
δ−⋅⋅=
FET type
R
DS(on)
(mΩ)
P
D
(W) Package
BUK556H 22 2.48 TO220
IRL2203 7.0 0.79 D
2
PAK
Si4410 13.5 1.53 SO-8
FET type
R
DS(on)
(mΩ)
P
D
(W) Package
BUK556H 22 1.95 TO220
IRL2203 7.0 0.62 D
2
PAK
Si4410 13.5 1.20 SO-8
BOTTOM FET - Bottom FET losses are almost entirely
due to conducti on. The body diode is forced into conduction at the beginning and end of the bot tom switch
conduction period, so when the FET turns on and off,
there is very little voltage across it , resulting in low
switching losses. Conducti on losses for the FET can be
determined by:
For the ex ample above:
Each of t he pac k age types has a characteristic thermal
impedance, for the TO-220 pack age, thermal
impedance is mostly determined by the heatsink used.
For the surf ac e mount packages on double sided FR4, 2
oz printed circuit board mat er ial, thermal impedances of
40
o
C/W for the D2PAK and 80oC/W for the SO-8 are
readily ac hievable. T he c or r espondi ng temperature rise
is detail ed below:
Temperat ur e r ise (oC)
FET type Top FET Bottom FET
BUK556H 49.6
(1)
39.0
(1)
IRL2203 31.6 24.8
Si4410 122.4 96
(1) Wit h 20
o
C/W Heatsink
It is apparent that single SO-8 Si4410 ar e not adequate
for this application, but by usi ng parallel pairs in each position, power dissipation will be approximately halved and
temperat ur e r ise reduced by a factor of 4.
INPUT CAPACITORS - since the RMS ripple current
in the input capacitors may be as high as 50% of the
output current , suitable capacitors must be chosen accordingly . Also, during fast load transients, there may
be restrictions on input di/dt. T hese restrictions require
useable energy storage withi n the converter circuitry,
either as extra output capacitance or, more usually,
additional input capacitors. Choosi ng low ESR input
capacitors will help maximize ripple rating for a given
size.
Page 12
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER, DUAL LOW DROPOUT
REGULATOR CONTROLLER
© 1998 SEMTECH CORP.
August 25, 1998
652 MITCHELL ROA D NE WBURY PARK CA 91320
SC1182/3
12
OUTLINE DRAWING
JEDEC MS-013AD
B17104B
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