Page 1
查询SC1172供应商
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
October 25, 1999
TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com
DESCRIPTION
The SC1172/3 combines a synchronous voltage mode
controller with a low-dropout linear regulator providing
most of the circuitry necessary to implement two DC/DC
converters for powering advanced microprocessors such
as Pentium
The SC1172/3 switching section features an integrated 5
bit D/A converter, pulse by pulse current limiting,
integrated power good signaling, and logic compatible
shutdown. The SC1172/3 switching section operates at
a fixed frequency of 200kHz, providing an optimum
compromise between size, efficiency and cost in the
intended application areas. The integrated D/A converter provides programmability of output voltage from
2.0V to 3.5V in 100mV increments and 1.30V to 2.05V
in 50mV increments with no external components.
The SC1172/3 linear section is a high performance
positive voltage regulator design for either the GTL bus
supply at 1.5V (SC1172) or an adjustable output
(SC1173).
The output of the linear regulator can provide up to 5A or
more with the appropriate external MOSFET.
®
II (Klamath) or Deschutes.
SC1172/3
FEATURES
•
Synchronous design, enables no heatsink solution
•
95% efficiency (switching section)
•
5 bit DAC for output programmability
•
On chip power good function
•
Designed for Intel Pentium® II VRM8.1 requirements
•
1.5V or Adj. @ 1% for linear section
APPLICATIONS
•
Pentium® ll or Deschutes microprocessor supplies
•
Flexible motherboards
•
1.3V to 3.5V microprocessor supplies
•
Programmable dual power supplies
ORDERING INFORMATION
Part Number
(1)
Package
Linear
Voltage
SC1172CSW SO-24 1.5V 0° to 125°C
SC1173CSW SO-24 Adj. 0° to 125°C
Temp.
Range (T
J
)
PIN CONFIGURATION
Top View
AGND
LDOS
VCC
OVP
PWRGOOD
CS+
PGNDH
PGNDL
1
NC
2
NC
3
4
5
6
7
CS-
8
9
10
DH
11
12
(24 Pin SOIC)
24
23
22
21
20
19
18
17
16
15
14
13
GATE
LDOV
VID0
VID1
VID2
VID3
VID4
VOSENSE
EN
BSTH
BSTL
DL
Note:
(1) Add suffix ‘TR’ for tape and reel.
BLOCK DIAGRAM
VCC CS+CS-
1.25 REF
VCC
VID4
VID3
VID2
VID1
VID0
VOSENSE
PWRGOOD
OVP
D/A &
SHUTDOWN
LOGIC
OPEN
COLLECTORS
VCC
70mV
AGND
CURRENT LIMIT
OSCILLATOR
ERROR
AMP
1.25V
REF
R
Q
S
FET
CONTROLLER
EN
BSTH
LEVEL SHIFT
AND HIGH SIDE
MOSFET DRIVE
SHOOT-
THRU
CONTROL
SYNCHRONOUS
MOSFET DRIVER
DH
PGNDH
BSTL
DL
PGNDL
© 1999 SEMTECH CORP.
LDOV
Pentium is a registered trademark of Intel Corporation
GATE LDOS
1
652 MITCHELL ROAD NEWBURY PARK CA 91320
Page 2
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
SC1172/3
REGULATOR CONTROLLER
October 25, 1999
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Maximum Units
V
to GND V
CC
IN
-0.3 to +7 V
PGND to GND ± 1 V
BST to GND -0.3 to +15 V
Operating Temperature Range T
Junction Temperature Range T
Storage Temperature Range T
Lead Temperature (Soldering) 10 seconds T
Thermal Impedance Junction to Ambient
Thermal Impedance Junction to Case
θ
θ
A
J
STG
L
JA
JC
0 to +70 °C
0 to +125 °C
-65 to +150 °C
300 °C
80
25
°
C/W
°
C/W
ELECTRICAL CHARACTERISTICS
Unless specified: V
PARAMETER CONDITIONS MIN TYP MAX UNITS
Switching Section
Output Voltage I
Supply Voltage V
Supply Current V
Load Regulation I
Line Regulation 0.5 %
Minimum operating voltage 4.2 V
Current Limit Voltage 60 70 80 mV
Oscillator Frequency 180 200 220 kHz
Oscillator Max Duty Cycle 90 95 %
DH Sink/Source Current
DL Sink/Source Current
Output Voltage Tempco 30 100 ppm/
Gain (A
)V
OL
OVP threshold voltage 120 %
OVP source current V
Power good threshold voltage 88 112 %
Dead time 50 100 ns
Linear Section
Quiescent current LDOV = 12V 5 mA
Output Voltage (SC1172) 1.485 1.500 1.515 V
Reference Voltage (SC1173) 1.252 1.265 1.278 V
Feedback Pin Bias Current (SC1173) 10 uA
Gain (A
) LDOS to GATE 90 dB
OL
Load Regulation I
Line Regulation 0.3 %
Output Impedance 200
= 4.75V to 5.25V; GND = P
CC
GND
= 0V; V
= VO; 0mV < (CSp-CSm) < 60mV; LDOV = 11.4V to 12.6V; TA = 25oC
OSENSE
= 2A See Note 1.
O
CC
= 5.0 8 15 mA
CC
= 0.8A to 15A 1 %
O
BSTH-DH = 4.5V, DH-PGNDH = 2V
BSTL-DL = 4.5V, DL-PGNDL = 2V
to V
OSENSE
= 3.0V 10 mA
OVP
= 0 to 8A
O
O
(2)
4.2 7 V
1A
1A
35 dB
0.3 %
o
Ω
C
Notes:
(1) See Output Voltage table
(2) In application circuit
© 1999 SEMTECH CORP.
2
652 MITCHELL ROAD NEWBURY PARK CA 91320
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PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
October 25, 1999
PIN DESCRIPTION
Pin Pin Name Pin Function
1 AGND Small Signal Analog and Digital Ground
2 NC No connection
3 NC No Connection
4 LDOS Sense Input for LDO
5 VCC Input Voltage
6 OVP High Signal out if V
(1)
7 PWRGOOD
Open collector logic output, high if V
within 10% of setpoint
8 CS- Current Sense Input (negative)
9 CS+ Current Sense Input (positive)
10 PGNDH Power Ground for High Side Switch
11 DH High Side Driver Output
12 PGNDL Power Ground for Low Side Switch
13 DL Low Side Driver Output
14 BSTL Supply for Low Side Driver
15 BSTH Supply for High Side Driver
16 EN
(1)
Logic low shuts down the converter;
High or open for normal operation.
17 VOSENSE Top end of internal feedback chain
18 VID4
19 VID3
20 VID2
21 VID1
22 VID0
(1)
(1)
(1)
(1)
(1)
Programming Input (MSB)
Programming Input
Programming Input
Programming Input
Programming Input (LSB)
23 LDOV +12V for LDO section
24 GATE Gate Drive Output LDO
>setpoint +20%
O
Top View
NC
NC
CS-
DH
1
2
3
4
5
6
7
8
9
10
11
12
AGND
LDOS
O
VCC
OVP
PWRGOOD
CS+
PGNDH
PGNDL
24
23
22
21
20
19
18
17
16
15
14
13
(24 Pin SOIC)
Note:
(1) All logic level inputs and outputs are open
collector TTL compatible.
SC1172/3
GATE
LDOV
VID0
VID1
VID2
VID3
VID4
VOSENSE
EN
BSTH
BSTL
DL
© 1999 SEMTECH CORP.
3
652 MITCHELL ROAD NEWBURY PARK CA 91320
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PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
October 25, 1999
OUTPUT VOLTAGE
Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; V
PARAMETER CONDITIONS VID
Output Voltage I
= 2A in Application Circuit 01111 1.287 1.300 1.313 V
O
= VO; 0mV < (CSp-CSm) < 60mV; T
OSENSE
SC1172/3
= 25oC
A
MIN TYP MAX UNITS
43210
01110 1.336 1.350 1.364
01101 1.386 1.400 1.414
01100 1.435 1.450 1.465
01011 1.485 1.500 1.515
01010 1.534 1.550 1.566
01001 1.584 1.600 1.616
01000 1.633 1.650 1.667
00111 1.683 1.700 1.717
00110 1.732 1.750 1.768
00101 1.782 1.800 1.818
00100 1.831 1.850 1.869
00011 1.881 1.900 1.919
00010 1.930 1.950 1.970
00001 1.980 2.000 2.020
00000 2.029 2.050 2.071
11111 1.980 2.000 2.020
11110 2.079 2.100 2.121
11101 2.178 2.200 2.222
11100 2.277 2.300 2.323
11011 2.376 2.400 2.424
11010 2.475 2.500 2.525
11001 2.574 2.600 2.626
11000 2.673 2.700 2.727
10111 2.772 2.800 2.828
10110 2.871 2.900 2.929
10101 2.970 3.000 3.030
10100 3.069 3.100 3.131
10011 3.168 3.200 3.232
10010 3.267 3.300 3.333
10001 3.366 3.400 3.434
10000 3.465 3.500 3.535
© 1999 SEMTECH CORP.
4
652 MITCHELL ROAD NEWBURY PARK CA 91320
Page 5
October 25, 1999
APPLICATION CIRCUIT
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1172/3
R4 2.32k
R3 1.00k
C4
R16
10k
0.1uF
Q1
BUK556
C7
C6
R5
5mOhm
L1
VCC_CORE
1500uF
1500uF
4uH
+
+
Q2
C10 0.1uF
+
+
BUK556
VLIN
C12
330uF
+
C11
330uF
+
C9
1500uF
C8
1500uF
**
R17 100k
*
R13
*
R12
Q3
BUK556
+
C21
330uF
WITHOUT 12V BEING PRESENT.
* SEE "SETTING LDO OUTPUT VOLTAGE" TABLE.
FOR SC1172, R12 AND R13 ARE NOT REQUIRED.
CONNECT LDOS (PIN4) DIRECTLY TO VLIN TO
GENERATE 1.5V TO OUTPUT.
** R17 REQUIRED IF VINLIN CAN BE PRESENT
NOTE:
12V
9
17
18
CS-
CS+
VO SENSE
PWRGOOD
VID4
15
BSTH
10
11
13
14
23
4
DL
DH
PGNDH
BSTL
LDOV
LDOS
7
8
U1
VCC
C3
C2
5 6
1500uF
1500uF
R1 10
+
+
5V
C1
0.1uF
OVP
VID0
VID1
VID2
20 21 22
19
VID3
EN
PGNDL
GATE
NC
AGND
1
16
12
24
C5
0.1uF
EN
OVP
VID0
VID1
2
VID2
NC
3
VID3
SC1172/3CS
VID4
PWRGD
VINLIN
(NORMALLY 3.3V)
5
© 1999 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
Page 6
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
October 25, 1999
MATERIALS LIST
Qty. Reference Part/Description Vendor Notes
4 C1,C5,C13,C180.1µF Ceramic Various
SC1172/3
6 C2,C3,C14-
C17
3 C11,C12,
C21
1 L1 4µH 8 Turns 16AWG on MICROMETALS T50-52D core
3 Q1,Q2,Q3 See notes See notes FET selection requires trade-off between efficiency and
1R4
1R5
1R6
1R1
1 R12 1%, 1/8W Various See Table (Not required for SC1172)
1 R13 1%, 1/8W Various See Table (Not required for SC1172)
1 R17 100K, 5% 1/8W Various
1 U1 SC1172/3CSW SEMTECH
1500µF/6.3V SANYO MV-GX or equiv. Low ESR
330µF/6.3V Various
cost. Absolute maximum R
Ω
5m
2.32kΩ, 1%, 1/8W
1kΩ, 1%, 1/8W
10Ω, 5%, 1/8W
IRC OAR-1 Series
Various
Various
Various
= 22 mΩ for Q1,Q2
DS(ON)
SETTING LDO OUTPUT VOLTAGE
R
B
VO LDO R12 R13
3.45V
3.30V
3.10V
2.90V
2.80V
2.50V
1.50V
© 1999 SEMTECH CORP.
105
105
102
100
100
100
100
Ω
Ω
Ω
Ω
Ω
Ω
Ω
R
A
182
169
147
130
121
97.6
18.7
)RR(265.1
+⋅
V
=
OUT
Ω
Ω
Ω
Ω
Ω
Ω
Ω
FB
B
:Where
=
=
A
=
652 MITCHELL ROAD NEWBURY PARK CA 91320
R
B
BA
⋅
AFB
error tsignifican
BA
current bias pin FeedbackI
resistor feedback Top R
resistor feedback Bottom R
)RI(
⋅+
AFB
ionclarificat for diagram layout See
so enoughlow be must R and R
cause not does term )RI( the that
6
Page 7
October 25, 1999
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1172/3
95%
90%
85%
Efficiency
80%
75%
70%
0 2 4 6 8 10121416
3.5V Std
3.5V Sync
3.5V Sync Lo Rds
Io (Amps)
Typical Efficiency at Vo=3.5V
95%
90%
85%
Efficiency
80%
75%
2.5V Std
2.5V Sync
2.5V Sync Lo Rds
95%
90%
85%
Efficiency
80%
75%
70%
0 2 4 6 8 10 12 14 16
2.8V Std
2.8V Sync
2.8V Sync Lo Rds
Io (Amps)
Typical Efficiency at Vo=2.8V
95%
90%
85%
Efficiency
80%
75%
2.0V Std
2.0V Sync
2.0V Sync Lo Rds
70%
0 2 4 6 8 10 12 14 16
Io (Amps)
Typical Efficiency at Vo=2.5V
Typical Ripple, Vo=2.8V, Io=10A
70%
0 2 4 6 8 10 12 14 16
Io (Amps)
Typical Efficiency at Vo=2.0V
Transient Response Vo=2.8V, Io=300mA to 10A
© 1999 SEMTECH CORP.
7
652 MITCHELL ROAD NEWBURY PARK CA 91320
Page 8
October 25, 1999
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1172/3
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary
for successful implementation of the SC1172/3 PWM
controller. High currents switching at 200kHz are present in the application and their effect on ground plane
voltage differentials must be understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such
as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground
plane may be deliberately introduced to constrain
ground currents to particular areas, for example the input capacitor and bottom FET ground.
2). The loop formed by the Input Capacitor(s) (Cin), the
Top FET (Q1) and the Bottom FET (Q2) must be kept
10
1
AGND
2
NC
3
NC
4 Q1
LDOS
0.1uF
5
VCC
6
OVP
7
PWRGOOD
0.1uF
8
CS-
9
CS+
10
PGNDH
11
DH
12
PGNDL
VO SENSE
SC1172/3
GATE
LDOV
VID0
VID1
VID2
VID3
VID4
BSTH
BSTL
24
23
22
21
20
19
18
17
16
EN
15
14
13
DL
as small as possible. This loop contains all the high current, fast transition switching. Connections should be as
wide and as short as possible to minimize loop inductance. Minimizing this loop area will a) reduce EMI, b)
lower ground injection currents, resulting in electrically
“cleaner” grounds for the rest of the system and c) minimize source ringing, resulting in more reliable gate
switching signals.
3). The connection between the junction of Q1, Q2 and
the output inductor should be a wide trace or copper
region. It should be as short as practical. Since this
connection has fast voltage transitions, keeping this
connection short will minimize EMI. The connection between the output inductor and the sense resistor should
be a wide trace or copper area, there are no fast voltage or current transitions in this connection and length
is not so important, however adding unnecessary
impedance will reduce efficiency.
12V IN
5V
Cin
+
Q2
4uH
1.00k
2.32k
5mOhm
Cout
Vout
+
5V Vo Lin
+
Cin Lin
Layout diagram for the SC1172/3
© 1999 SEMTECH CORP.
RA
Q3
RB
Cout Lin
+
For SC1172, RA and RB
Heavy lines indicate
high current paths.
are not required. LDOS connects to
Vo Lin
8
652 MITCHELL ROAD NEWBURY PARK CA 91320
Page 9
October 25, 1999
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1172/3
4) The Output Capacitor(s) (Cout) should be located
as close to the load as possible, fast transient load
currents are supplied by Cout only, and connections
between Cout and the load must be short, wide copper areas to minimize inductance and resistance.
5) The SC1172/3 is best placed over a quite ground
plane area, avoid pulse currents in the Cin, Q1, Q2
loop flowing in this area. PGNDH and PGNDL should
be returned to the ground plane close to the package.
The AGND pin should be connected to the ground
side of (one of) the output capacitor(s). If this is not
possible, the AGND pin may be connected to the
ground path between the Output Capacitor(s) and the
Cin, Q1, Q2 loop. Under no circumstances should
AGND be returned to a ground inside the Cin, Q1, Q2
loop.
6) Vcc for the SC1172/3 should be supplied from the
5V
5V supply through a 10Ω resistor, the Vcc pin should
be decoupled directly to AGND by a 0.1µF ceramic
capacitor, trace lengths should be as short as possi-
ble.
7) The Current Sense resistor and the divider across
it should form as small a loop as possible, the traces
running back to CS+ and CS- on the SC1172/3 should
run parallel and close to each other. The 0.1µF capacitor should be mounted as close to the CS+ and
CS- pins as possible.
8) Ideally, the ground for the LDO section should be
returned to the ground side of (one of) the switching
section output capacitor(s).
+
Currents in various parts of the power section
Vout
+
9
© 1999 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
Page 10
October 25, 1999
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1172/3
COMPONENT SELECTION
SWITCHING SECTION
OUTPUT CAPACITORS - Selection begins with the
most critical component. Because of fast transient load
current requirements in modern microprocessor core
supplies, the output capacitors must supply all transient
load current requirements until the current in the output
inductor ramps up to the new level. Output capacitor
ESR is therefore one of the most important criteria. The
maximum ESR can be simply calculated from:
V
R
ESR
t
≤
I
t
Where
=
t
=
t
step current Transient I
For example, to meet a 100mV transient limit with a
10A load step, the output capacitor ESR must be less
than 10mΩ. To meet this kind of ESR level, there are
three available capacitor technologies:
Each Capacitor Total
Technology C
(µF)
Low ESR Tantalum 330 60 6 2000 10
OS-CON 330 25 3 990 8.3
Low ESR Aluminum 1500 44 5 7500 8.8
ESR
(mΩ)
The choice of which to use is simply a cost /performance issue, with Low ESR Aluminum being the
cheapest, but taking up the most space.
INDUCTOR - Having decided on a suitable type and
value of output capacitor, the maximum allowable
value of inductor can be calculated. Too large an inductor will produce a slow current ramp rate and will
cause the output capacitor to supply more of the transient load current for longer - leading to an output voltage sag below the ESR excursion calculated above.
The maximum inductor value may be calculated from:
CR
ESR
L
()
VV
−≤
I
t
OIN
The calculated maximum inductor value assumes 100%
duty cycle, so some allowance must be made. Choosing
an inductor value of 50 to 75% of the calculated maximum will guarantee that the inductor current will ramp
excursion voltage transient MaximumV
Qty.
Rqd.C(µF)
ESR
(mΩ)
fast enough to reduce the voltage dropped across the
ESR at a faster rate than the capacitor sags, hence ensuring a good recovery from transient with no additional
excursions.
We must also be concerned with ripple current in the
output inductor and a general rule of thumb has been to
allow 10% of maximum output current as ripple current.
Note that most of the output voltage ripple is produced
by the inductor ripple current flowing in the output capacitor ESR. Ripple current can be calculated from:
V
I
L
RIPPLE
IN
=
fL4
⋅⋅
OSC
Ripple current allowance will define the minimum permitted inductor value.
POWER FETS - The FETs are chosen based on several
criteria with probably the most important being power
dissipation and power handling capability.
TOP FET - The power dissipation in the top FET is a
combination of conduction losses, switching losses and
bottom FET body diode recovery losses.
a) Conduction losses are simply calculated as:
2
RIP
OCOND
δ⋅⋅=
)on(DS
where
V
O
cycleduty =
≈δ
V
IN
b) Switching losses can be estimated by assuming a
switching time, if we assume 100ns then:
2
−
⋅⋅=
10VIP
INOSW
or more generally,
f)tt(VI
⋅+⋅⋅
P
=
SW
4
c) Body diode recovery losses are more difficult to estimate, but to a first approximation, it is reasonable to assume that the stored charge on the bottom FET body
diode will be moved through the top FET as it starts to
turn on. The resulting power dissipation in the top FET
will be:
To a first order approximation, it is convenient to only
consider conduction losses to determine FET suitability.
For a 5V in; 2.8V out at 14.2A requirement, typical FET
losses would be:
OSCfrINO
fVQP
⋅⋅=
OSCINRRRR
© 1999 SEMTECH CORP.
10
652 MITCHELL ROAD NEWBURY PARK CA 91320
Page 11
October 25, 1999
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
SC1172/3
FET type
R
DS(on)
(mΩ)
(W) Package
P
D
BUK556H 22 2.48 TO220
2
IRL2203 7.0 0.79 D
PAK
Si4410 13.5 1.53 SO-8
BOTTOM FET - Bottom FET losses are almost entirely
due to conduction. The body diode is forced into conduction at the beginning and end of the bottom switch conduction period, so when the FET turns on and off, there
is very little voltage across it, resulting in low switching
losses. Conduction losses for the FET can be determined by:
2
OCOND
δ−⋅⋅=
)on(DS
)1(RIP
For the example above:
FET type
R
DS(on)
(mΩ)
(W) Package
P
D
BUK556H 22 1.95 TO220
2
IRL2203 7.0 0.62 D
PAK
Si4410 13.5 1.20 SO-8
INPUT CAPACITORS - since the RMS ripple current in
the input capacitors may be as high as 50% of the output current, suitable capacitors must be chosen accordingly. Also, during fast load transients, there may
be restrictions on input di/dt. These restrictions require
useable energy storage within the converter circuitry,
either as extra output capacitance or, more usually,
additional input capacitors. Choosing low ESR input
capacitors will help maximize ripple rating for a given
size.
Each of the package types has a characteristic thermal
impedance, for the TO-220 package, thermal impedance
is mostly determined by the heatsink used. For the surface mount packages on double sided FR4, 2 oz printed
circuit board material, thermal impedances of 40
for the D
2
PAK and 80oC/W for the SO-8 are readily
o
C/W
achievable. The corresponding temperature rise is detailed below:
Temperature rise (oC)
FET type Top FET Bottom FET
BUK556H 49.6
(1)
39.0
(1)
IRL2203 31.6 24.8
Si4410 122.4 96
o
(1) With 20
C/W Heatsink
It is apparent that single SO-8 Si4410 are not adequate for
this application, but by using parallel pairs in each position, power dissipation will be approximately halved and
temperature rise reduced by a factor of 4.
© 1999 SEMTECH CORP.
11
652 MITCHELL ROAD NEWBURY PARK CA 91320
Page 12
October 25, 1999
OUTLINE DRAWING
PROGRAMMABLE SYNCHRONOUS DC/DC
CONVERTER WITH LOW DROPOUT
REGULATOR CONTROLLER
JEDEC MS-013AD
B17104B
SC1172/3
ECN99-667
© 1999 SEMTECH CORP.
12
652 MITCHELL ROAD NEWBURY PARK CA 91320
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