Datasheet SC1158CS.TR Datasheet (Semtech Corporation)

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

SC1158

Preliminary - August 7, 2000

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DESCRIPTION

The SC1158 is a low-cost, full featured, synchronous
voltage-mode controller designed for use in single
ended power supply applications where efficiency is of
primary concern. Synchronous operation allows for the
elimination of heat sinks in many applications. The
SC1158 is ideal for implementing DC/DC converters
needed to power advanced microprocessors such as
Pentium

®

ll and K6-2. Internal level-shift, high-side
drive circuitry, and preset shoot-thru control, allows for
use of inexpensive N-channel power switches.

SC1158 features include an integrated 4-bit V

DAC,

ID

temperature compensated voltage reference, triangle
wave oscillator, current limit comparator, frequency
shift over-current protection, and an internally compen­sated error amplifier.

The SC1158 operates at a fixed 140KHz, providing an
optimum compromise between efficiency, external
component size, and cost.

PIN CONFIGURATION

FEATURES

•= Low cost / full featured

•= Synchronous operation

•= 4 Bit V

(1% tolerance)

•= Meets Intel VRM8.2 (Pentium

DAC programmable output

ID

®

II) high range

•= 1.5% Reference

APPLICATIONS

•= Pentium® II, K6-2 Core Supplies

•= Multiple Microprocessor Supplies

•= Voltage Regulator Modules (VRM)

•= Programmable Power Supplies

•= High Efficiency DC/DC Conversion

ORDERING INFORMATION

DEVICE

(1)

PACKAGE

SC1158CS.TR SO-16NB 0 - 125°C

Note:
(1) Only available in tape and reel packaging. A reel
contains 2500 devices.
(2) “NB” indicates 150 MIL body.

(2)

TEMP. RANGE (TJ)

BLOCK DIAGRAM

Top View

(16-Pin SOIC)

REF

VID3
VID2

VID1
VID0

VOSENSE

GND

VCC CS-

CURRENT

REF

D/A

+

-

ERROR
AMP

OSCILLATOR

LIMIT

+

70mV

-

-

+

Pentium is a registered trademark of Intel Corporation

SHUTDOWNCS+

BSTH

LEVEL SHIFT AND
HIGH SIDE DRIVE

R

Q

S

SHOOT-THRU
CONTROL

SYNCHRONOUS
MOSFET DRIVE

DH

BSTL

DL

PGND

1

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

SC1158

CONTROLLER FOR ADVANCED PROCESSORS

Preliminary - August 7, 2000

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Maximum Units

to GND V

V

CC

IN

-0.3 to 7 V
PGND to GND ± 1 V
BST to GND -0.3 to 15 V
Thermal Resistance Junction to Case

Thermal Resistance Junction to Ambient
Operating Temperature Range
Storage Temperature Range

Lead Temperature (Soldering) 10 sec
ESD Rating (Human Body Model)

θ

JC

θ

JA

T

A

T

STG

T

LEAD

ESD 1.5 kV

30 °C/W

130 °C/W

0 to 70 °C

-65 to +150 °C
300 °C

ELECTRICAL CHARACTERISTICS

Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV; TJ = 25oC

PARAMETER CONDITIONS MIN TYP MAX UNITS

Output Voltage See Table 1.
Supply Voltage V
Supply Current V
Load Regulation I

CC

= 5.0 8 15 mA

CC

= 0.3A to 15A

O

Line Regulation All VID codes
Gain (A

)V

OL

OSENSE

to V

(1)

(1)

O

4.5 7 V

1%

+ 0.15 %

35 dB
Current Limit Voltage 60 70 80 mV
Oscillator Frequency 125 140 155 kHz
Buffered Reference Voltage

I

REF

≤=1mA

1.25 V
Oscillator Max Duty Cycle 90 95 %
DH Sink/Source Current BST
DL Sink/Source Current BST

- DH = 4.5V, DH - PGNDH = 3V 1 A

H

- DL = 4.5V, DL - PGNDL = 3V 1 A

L

Dead Time 50 100 ns
VID Pin Source current VIDx <

2.4V 30 100 uA

NOTE:

(1) Specification refers to application circuit (Figure 1.).
(2) This device is ESD sensitive. Use of standard ESD handling precautions is required.

2

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

Preliminary - August 7, 2000

PIN DESCRIPTION

Pin # Pin Name Pin Function

1 GND Small Signal Analog and Digital Ground
2 REF Buffered Reference output

SC1158

3V

CC

Chip Supply Voltage
4 CS(-) Current Sense Input (negative)
5 CS(+) Current Sense Input (positive)
6 PGND Power Ground for High and Low Side Drivers

7 DH High Side Driver Output
8 DL Low Side Driver Output
9 BSTL Vcc for Low Side Driver (Boost)

10 BSTH Vcc for High Side Driver (Boost)
11 SHUTDOWN Logic Low shuts down the converter; High or open for normal operation.
12 VOSENSE Top end of internal feedback chain
13 VID3
14 VID2
15 VID1
16 VID0

(1)

(1)

(1)

(1)

Programming Input (MSB)

Programming Input

Programming Input

Programming Input (LSB)

NOTE:

(1) All logic level inputs and outputs are open collector TTL compatible.

PIN CONFIGURATION

3

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

Preliminary - August 7, 2000

OUTPUT VOLTAGE TABLE

Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV;

= 0°C to 85°C

T

J

PARAMETER CONDITIONS VID

3210

1101 2.178 2.200 2.222
1100 2.277 2.300 2.323
1011 2.376 2.400 2.424
1010 2.475 2.500 2.525
1001 2.574 2.600 2.626
1000 2.673 2.700 2.727
0111 2.772 2.800 2.828
0110 2.871 2.900 2.929
0101 2.970 3.000 3.030
0100 3.069 3.100 3.131
0011 3.168 3.200 3.232
0010 3.267 3.300 3.333
0001 3.366 3.400 3.434
0000 3.465 3.500 3.535

Output Voltage

(1)

IO = 2A in Application Circuit 1111 1.980 2.000 2.020 V
(Figure 1) 1110 2.079 2.100 2.121

MIN TYP MAX UNITS

SC1158

THEORY OF OPERATION

The voltage at the VOSENSE pin is applied, through the internal precision resistor feedback chain, to the inverting
input of the error amplifier. The non-inverting input of the error amplifier is supplied with a DC voltage derived by
the DAC from the internal trimmed bandgap voltage reference. The output of the error amplifier is compared to the
triangular output of the internal oscillator to generate a fixed frequency, variable duty cycle pulse train. The internal
oscillator uses an on-chip capacitor and precision trimmed current sources to set the frequency to 140 kHz.
The generated pulse train is gated with the output of the current limit latch and the inhibit signal to produce a drive
signal for the upper FET. It is also inverted to produce a drive signal for the lower FET. These FET drive signals
are modified by the “shoot-through control” circuitry so that the top FET turn-on is delayed until the bottom FET has
turned off, and visa-versa.
The current limit latch is set (ending the upper FET drive pulse early) if the current limit comparator indicates an
overcurrent condition. The latch is reset at the start of each oscillator period.

4

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

Preliminary - August 7, 2000

OUTLINE DRAWING SO-16

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

Jedec MS-012AC

SC1158

LAND PATTERN SO-16

ECN00-1243

5

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320