Datasheet SC1154 Datasheet (SEMTECH)

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PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS

SC1154

PRELIMINARY - March 1, 2000

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DESCRIPTION

The SC1154 is a synchronous-buck switch-mode con­troller designed for use in single ended power supply
applications where efficiency is the primary concern.
The controller is a hysteretic type, with a user se­lectable hysteresis. The SC1154 is ideal for imple­menting DC/DC converters needed to power advanced
microprocessors such as Pentium
and multiple processor configurations. Inhibit, under­voltage lockout and soft-start functions are included for
controlled power-up.

SC1154 features include an integrated 5 bit D/A con­verter, temperature compensated voltage reference,
current limit comparator, over-current protection, and
an adaptive deadtime circuit to prevent shoot-through
of the power MOSFET during switching transitions.
Power good signaling, logic compatible shutdown, and
over-voltage protection are also provided. The inte­grated D/A converter provides programmability of out­put voltage from 2.0V to 3.5V in 100mV increments
and 1.3V to 2.05V in 50mV increments with no external
components.

The SC1154 high side driver can be configured as ei­ther a grounded reference or as a floating bootstrap
driver. High and low side drivers have a peak current
rating of 2 amps.

®

ll, in both single

FEATURES

•

Programmable hysteresis

•

5 bit DAC programmable output (1.3V-3.5V)

•

On-chip power good and OVP functions

•

Designed to meet latest Intel specifications

•

Up to 95% efficiency

•

+ 1% tolerance over temperature

APPLICATIONS

•

Server Systems and Workstations

•

Pentium® II Core Supply

•

Multiple Microprocessor Supplies

•

Voltage Regulator Modules

ORDERING INFORMATION

DEVICE

SC1154CSW SO-28 0 - 125°C

Note:
(1) Add suffix ‘TR’ for tape and reel.

(1)

PACKAGE TEMP. RANGE (TJ)

PIN CONFIGURATION

Top View

(28-Pin SOIC)

SIMPLIFIED BLOCK DIAGRAM

Pentium is a registered trademark of Intel Corporation

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

1

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER

SC1154

FOR ADVANCED PROCESSORS

PRELIMINARY - March 1, 2000

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Maximum Units

VIN12V VIN

MAX

14 V
BOOT to DRVGND 25 V
BOOT to BOOTLO 15 V
Digital Inputs -0.3 to +7.3 V
AGND to DRVGND +

0.5V V
LOHIB to AGND 14 V
LOSENSE to AGND 14 V
IOUTLO to AGND 14 V
HISENSE to AGND 14 V
VSENSE to AGND 5V
Continuous Power Dissipation, T
Continuous Power Dissipation, T
Operating Junction Temperature T
Lead Temperature (Soldering) 10 seconds T
Storage Temperature T

= 25°C P

A

= 25°C P

C

D

D

J

L

STG

1.2 W

6.25 W

0 to +125 °C

300 °C

-65 to 150 °C

2

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER

SC1154

FOR ADVANCED PROCESSORS

PRELIMINARY - March 1, 2000

PIN DESCRIPTION

Pin Pin Name Pin Function

1 IOUT Current Out. The output voltage on this pin is proportional to the load current as measured

across the high side MOSFET, and is approximately equal to 2 x R

2 DROOP Droop Voltage. This pin is used to set the amount of output voltage set-point droop as a

function of load current. The voltage is set by a resistor divider between IOUT and AGND.

3 OCP Over Current Protection. This pin is used to set the trip point for over current protection by a

resistor divider between IOUT and AGND.

4 VHYST Hysteresis Set Pin. This pin is used to set the amount of hysteresis required by a resistor

divider between VREFB and AGND.
5 VREFB Buffered Reference Voltage (from VID circuitry).
6 VSENSE Output Voltage Sense.
7 AGND Small Signal Analog and Digital Ground.
8 SOFTST Soft Start. Connecting a capacitor from this pin to AGND sets the time delay.

DS(ON)

x I

LOAD

.

9 NC Not connected

10 LODRV Low Drive Control. Connecting this pin to +5V enables normal operation. When LOHIB is

grounded, this pin can be used to control LOWDR.

11 LOHIB Low Side Inhibit. This pin is used to eliminate shoot-thru current.
12 DRVGND Power Ground.
13 LOWDR Low Side Driver Output.
14 DRV Drive Regulator for the MOSFET Drivers.
15 VIN12V 12V Supply.
16 BOOT Bootstrap. This pin is used to generate a floating drive for the high side FET driver.
17 HIGHDR High Side Driver Output.
18 BOOTLO Bootstrap Low. In desktop applications, this pin connects to DRVGND.
19 HISENSE High Current Sense. Connected to the drain of the high side FET, or the input side of a current

sense resistor between the input and the high side FET.

20 LOSENSE Low Current Sense. Connected to the source of the high side FET, or the FET side of a current

sense resistor between the input and the high side FET.

21 IOUTLO This is the sampling capacitors bottom leg. Voltage on this pin is voltage on the LOSENSE pin

when the high side FET is on.

22 INHIBIT Inhibit. If this pin is grounded, the MOSFET drivers are disabled. Usually connected to +5V

through a pull-up resistor.

(1)

23 VID4
24 VID3
25 VID2
26 VID1
27 VID0
28 PWRGD

Programming Input (MSB).

(1)

Programming Input.

(1)

Programming Input.

(1)

Programming Input.

(1)

Programming Input (LSB).

(1)

Power Good. This open collector logic output is high if the output voltage is within 5% of the set

point.

3

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER

SC1154

FOR ADVANCED PROCESSORS

PRELIMINARY - March 1, 2000

ELECTRICAL CHARACTERISTICS

Unless specified: 0 < TJ < 125°C, VIN = 12V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage Range VIN12V 11.4 12 13 V

I

BOOT

q

IN

q

Supply Current (Quiescent) I

High Side Driver Supply
Current (Quiescent)

REFERENCE/VOLTAGE IDENTIFICATION

Reference Voltage Accuracy V

VID0 - VID4 High Threshold

V

REF

TH(H)

Voltage
VID0 - VID4 Low Threshold

V

TH(L)

Voltage

POWER GOOD

Undervoltage Threshold V
Output Saturation Voltage V
Hysteresis V

TH(PWRGD)

SAT

HYS(PWRGD)

OVER VOLTAGE PROTECTION

INH = 5V, VID not 11111,

15 mA

VIN above UVLO threshold during start-up,

= 200kHz, BOOTLO = 0V,

f

SW

= CDL = 50pF

C

DH

INH = 0V or VID = 11111 or VIN below

10 µA
UVLO threshold during start-up,
BOOT = 13V, BOOTLO = 0V

INH = 5V, VID not 11111, VIN

5mA

above UVLO threshold during start-up,

= 200kHz, BOOT = 13V, BOOTLO = 0V,

f

SW

= 50pF

C

DH

11.4V < VIN12V < 12.6V, over full VID

-1 1 %

range (see Output Voltage Table)

2.25 V

1V

90 95 % V

IO = 5mA 0.5 V

10 mV

REF

OVP Trip Point V
Hysteresis

(1)

V

HYS(OVP)

OVP

12 15 20 %V

10 mV

REF

4

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER

SC1154

FOR ADVANCED PROCESSORS

PRELIMINARY - March 1, 2000

ELECTRICAL CHARACTERISTICS (cont.)

Unless specified: 0 < TJ < 125°C, VIN = 12V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SOFT START

Charge Current I

CHG

Discharge Current Idischg V

INHIBIT COMPARATOR

Start Threshold Vstart

INH

VIN12V UVLO

Start Threshold Vstart
Hysteresis Vhys

UVLO

UVLO

HYSTERETIC COMPARATOR

Input Offset Voltage Vos
Input Bias Current Ibias
Hysteresis Accuracy V
Hysteresis Setting V

HYSCMPVDROOP

HYSCMP

HYS_ACC

HYS_SET

DROOP COMPENSATION

Initial Accuracy V

DROOP_ACCVDROOP

OVERCURRENT PROTECTION

VSS = 0.5V, resistance from

10.4 13 15.6 µA

VREFB pin to AGND = 20kΩ,

= 1.3V

V

REFB

Note: I

(S/S)

CHG

= (I

VREFB

/ 5)

= 1V 1 mA

12.02.4 V

9.25 10 10.75 V

1.8 2 2.2 V

pin grounded 5 mV

1µA
7mV

60 mV

= 50mV 5 mV

OCP Trip Point V
Input Bias Current Ibias

OCP

OCP

0.09 0.1 0.11 V
100 nA

HIGH-SIDE VDS SENSING

Gain 2V/V
Initial Accuracy V

IOUT_ACC

IOUT Source Isource

IOUT Sink Current Isink

Output Voltage Swing V

V

IOUTVIOUT

V
V

IOUT

V

R

HISENSE

= 0.5V, V

= 11.5V

IOUTLO

= 0.05V, V

IOUT

= 12V

IOUTLO

HISENSE

= 10k0hm

IOUT

= 12V, V

HISENSE

= 11V,

= 11.9V 6 mV

IOUTLO

500 µA

40 50 µA

HISENSE

= 12V,

= 12V,

03.75V

5

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER

SC1154

FOR ADVANCED PROCESSORS

PRELIMINARY - March 1, 2000

ELECTRICAL CHARACTERISTICS (cont.)

Unless specified: 0 < TJ < 125°C, VIN12V = 12V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
HIGH-SIDE VDS SENSING (cont.)

LOSENSE High Level Input

Vih

LOSENSEVHISENSE

Voltage
LOSENSE Low Level Input

Vil

LOSENSEVHISENSE

Voltage
Sample/Hold Resistance R

BUFFERED REFERENCE

VREFB Load Regulation Vldreg

DEADTIME CIRCUIT

LOHIB High Level Voltage Vih
LOHIB Low Level Input

Vil

LOHIB

Voltage
LOWDR High Level Input

Vih

LOWDR

Voltage
LOWDR Low Level Input

Vil

LOWDR

Voltage

DRIVE REGULATOR

S/H

REFB

LOHIB

V

HISENSE

R

IOUT

V

HISENSE

= 4.5V,

= 10kOhm

= 3V, R

= 10kOhm 0 1.0 V

IOUT

02.0V

= 4.5V (Note 1) 2.85 V

= 4.5V (Note 1) 1.8 V

4.5V < = 13V 50 65 80

10µA < I

< 500µA 2 mV

REFB

2V

1.0 V

(Note 1) 2 V

(Note 1) 1.0 V

Ω

Output Voltage V

DRV

Load Regulation Vldreg
Short Circuit Current Ishort

HIGH-SIDE OUTPUT DRIVER

Peak Output Current Isrc

Isink

HIGHDR’

HIGHDR

11.4 < VIN12V < 12.6V,
= 50mA

I

DRV

DRV

DRV

1mA < I

< 50mA 100 mV

DRV

duty cycle < 2%, tpw < 100us,

= 125°C

T

J

V

BOOT

- V

BOOTLO

= 6.5V, V
= 1.5V (src), or V
(sink) (Note 1)

HIGHDR

79V

100 mA

2

A

HIGHDR

= 5V

6

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER

SC1154

FOR ADVANCED PROCESSORS

PRELIMINARY - March 1, 2000

ELECTRICAL CHARACTERISTICS (cont.)

Unless specified: 0 < T

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
HIGH-SIDE OUTPUT DRIVER (cont.)

125°C, VIN12V = 12V

J <

Output Resistance Rsrc

Rsink

LOW-SIDE OUTPUT DRIVER

Peak Outout Current Isrc

Isink

Output Resistance Rsrc

Rsink

HYSTERETIC COMPARATORS

Propagation Delay Time

(1)

t

HCPROP

from
VSENSE to HIGHDR or
LOWDR (excluding
deadtime)

HIGHDR’

HIGHDR

LOWDR’

LOWDR

LOWDR’

LOWDR

TJ = 125°C
V

BOOT

V

HIGHDR

- V
= 6V

BOOTLO

= 6.5V,

TJ = 125°C
V

BOOT

V

HIGHDR

- V

= 0.5V

BOOTLO

= 6.5V,

duty cycle < 2%, tpw < 100us,
T

= 125°C

J

= 6.5V, V

V

DRV

(src), or V

LOWDR

= 1.5V

LOWDR

= 5V (sink)

(Note 1)
TJ = 125°C

V

DRV

= 6.5V, V

LOWDR

= 6V

TJ = 125°C
V

DRV

= 6.5V, V

LOWDR

= 0.5V

10mV overdrive,

Vref < 3.5V

1.3V <

45

Ω

5

2

A

45

Ω

5

150 250 ns

OUTPUT DRIVERS

HIGHDR rise/fall time tr

LOWDR rise/fall time tr

OVERCURRENT PROTECTION

Comparator Propagation

HIGHDR

,tfHIGHDR

LOWDR ,

tf

LOWDR

(1)

t

OCPROP

Cl = 9nF, V

BOOTLO

= 125 °C

J

= grounded,

V
T

Cl = 9nF, V

= 125 °C

T

J

BOOT

DRV

= 6.5v,

= 6.5v,

1µs

60 ns

60 ns

Delay Time
Deglitch Time t

OCDGL

13µs

OVERVOLTAGE PROTECTION

Comparator Propagation

t

OVPROP

1µs

Delay Time
Deglitch Time t

OVDGL

13µs

7

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER

SC1154

FOR ADVANCED PROCESSORS

PRELIMINARY - March 1, 2000

ELECTRICAL CHARACTERISTICS (cont.)

Unless specified: 0 < TJ < 125° C, VIN12V = 12V

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
HIGH-SIDE Vds SENSING

(1)

Response Time t

Short Circuit Protection

VDSRESP

t

Rising Edge Delay
Sample/Hold Switch turn-

t

on/turn-off Delay

POWER GOOD

Comparator Propagation

t

Delay

SOFTSTART

Comparator Propagation
Delay

DEADTIME

Driver Nonoverlap Time t

VDSRED

SWXDLY

PWRGD

t

SLST

NUL

V

HISENSE

= 12v, V

IOUTLO

2µs
pulsed from 12v to 11.9v,
100ns rise and fall times

V

HISENSE

= 4.5v, V

IOUTLO

3µs
pulsed from 4.5v to 4.4v,
100ns rise and fall times

V

HISENSE

= 3v, V

IOUTLO

3µs
pulsed from 3.0v to 2.9v,
100ns rise and fall times

LOSENSE grounded 300 500 ns

3v < V
V

LOSENSE

HISENSE

= V

< 11v

HISENSE

30 100 ns

1µs

overdrive = 10mv 560 900 ns

30 100 ns

Note 1: Guaranteed, but not tested

8

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PRELIMINARY - March 1, 2000

BLOCK DIAGRAM

Vcc

VIN12V

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS

DRV

BOOT

DRIVE

REGULATOR

HIGHDR

BOOTLO

LOWDR

DRVGND

SC1154

SOFTST

LOSENSE

IOUTLOHISENSEIOUT

PREREG

ANALOG BIAS

I(VREFB) / 5

LOWDR

FILTER

LODRV

VREF

DELAY

RISING EDGE

+

--+

+

--+

+

-

VREFB

VHYST

FILTER

HIGHDR

FILTER

VSENSE LOHIB

-

1.15VREF 0.93VREF

SHUTDOWN

+-

+

VREF

VID

DAC

DROOP

VID4

VID3

VID2

VID1

VID0

+

-

+

-

G=2

+

-

11111

DECODE

50uA

PWRGD

FAULT

Q

R

BANDGAP

+

-

+

-

INH

+

S

UVLO

DEGLITCH

-

DEGLITCH

0.93VREF

Vcc

10V

+

-

2V

+

-

VSENSE

INHIBIT

AGND

OCP

100mV

1.15VREF

9

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PRELIMINARY - March 1, 2000

OUTPUT VOLTAGE TABLE

0 = GND; 1 = Floating or +5V pull-up

VID4 VID3 VID2 VID1 VID0 VDC

0 1 1 1 1 1.30
0 1 1 1 0 1.35
0 1 1 0 1 1.40
0 1 1 0 0 1.45
0 1 0 1 1 1.50
0 1 0 1 0 1.55
0 1 0 0 1 1.60
0 1 0 0 0 1.65
0 0 1 1 1 1.70
0 0 1 1 0 1.75
0 0 1 0 1 1.80
0 0 1 0 0 1.85
0 0 0 1 1 1.90
0 0 0 1 0 1.95
0 0 0 0 1 2.00
0 0 0 0 0 2.05
1 1 1 1 1 NO CPU
1 1 1 1 0 2.10
1 1 1 0 1 2.20
1 1 1 0 0 2.30
1 1 0 1 1 2.40
1 1 0 1 0 2.50
1 1 0 0 1 2.60
1 1 0 0 0 2.70
1 0 1 1 1 2.80
1 0 1 1 0 2.90
1 0 1 0 1 3.00
1 0 1 0 0 3.10
1 0 0 1 1 3.20
1 0 0 1 0 3.30
1 0 0 0 1 3.40
1 0 0 0 0 3.50

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS

SC1154

(V)

NOTE:

(1) If the VID bits are set to 11111, then the high-side and the low-side driver outputs will be set low, and the con­troller will be set to a low-Iq state.

10

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PRELIMINARY - March 1, 2000

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS

SC1154

FUNCTIONAL DESCRIPTION

Reference/Voltage Identification

The reference/voltage identification (VID) section con­sists of a temperature compensated bandgap refer­ence and a 5-bit voltage selection network. The 5 VID
pins are TTL compatable inputs to the VID selection
network. They are internally pulled up to +5V gener­ated from the +12V supply by a resistor divider, and
provide programmability of output voltage from 2.0V to

3.5V in 100mV increments and 1.3V to 2.05V in 50mV
increments.
Refer to the Output Voltage Table for the VID code
settings. The output voltage of the VID network, VREF
is within 1% of the nominal setting over the full input
and output voltage range and junction temperature
range. The output of the reference/VID network is indi­rectly brought out through a buffer to the REFB pin.
The voltage on this pin will be within 3mV of VREF. It
is not recommended to drive loads with REFB other
than setting the hysteresis of the hysteretic compara­tor, because the current drawn from REFB sets the
charging current for the soft start capacitor. Refer to
the soft start section for additional information.

Hysteretic Comparator

The hysteretic comparator regulates the output voltage
of the synchronous-buck converter. The hysteresis is
set by connecting the center point of a resistor divider
from REFB to AGND to the HYST pin. The hysteresis
of the comparator will be equal to twice the voltage dif­ference between REFB and HYST, and has a maxi­mum value of 60mV. The maximum propagation delay
from the comparator inputs to the driver outputs is
250ns.

Low Side Driver

The low side driver is designed to drive a low R
channel MOSFET, and is rated for 2 amps source and
sink. The bias for the low side driver is provided inter­nally from VDRV.

High Side Driver

The high side driver is designed to drive a low R
N-channel MOSFET, and is rated for 2 amps source
and sink. It can be configured either as a ground refer­enced driver or as a floating bootstrap driver. When
configured as a floating driver, the bias voltage to the
driver is developed from the DRV regulator. The inter-

DS(ON)

DS(ON)

N-

nal bootstrap diode, connected between the DRV and
BOOT pins, is a Schottky for improved drive efficiency.
The maximum voltage that can be applied between the
BOOT pin and ground is 25V. The driver can be refer­enced to ground by connecting BOOTLO to PGND,
and connecting +12V to the BOOT pin.

Deadtime Control

Deadtime control prevents shoot-through current from
flowing through the main power FETs during switching
transitions by actively controlling the turn-on times of
the FET drivers. The high side driver is not allowed to
turn on until the gate drive voltage to the low-side FET
is below 2 volts, and the low side driver is not allowed
to turn on until the voltage at the junction of the 2 FETs
(VPHASE) is below 2 volts. An internal low-pass filter
with an 11MHz pole is located between the output of
the low-side driver (DL) and the input of the deadtime
circuit that controls the high-side driver, to filter out
noise that could appear on DL when the high-side
driver turns on.

Current Sensing

Current sensing is achieved by sampling and holding
the voltage across the high side FET while it is turned
on. The sampling network consists of an internal 50
switch and an external 0.1µF hold capacitor. Internal
logic controls the turn-on and turn-off of the sample/
hold switch such that the switch does not turn on until
VPHASE transitions high and turns off when the input
to the high side driver goes low. Thus sampling will
occur only when the high side FET is conducting cur­rent. The voltage at the IO pin equals 2 times the
sensed voltage. In applications where a higher accu­racy in current sensing is required, a sense resistor
can be placed in series with the high side FET and the
voltage across the sense resistor can be sampled by
the current sensing circuit.

Droop Compensation

The droop compensation network reduces the load
transient overshoot/undershoot at VOUT, relative to
VREF. VOUT is programmed to a voltage greater than
VREF (equal to VREF x (1+R5/R6)) by an external re­sistor divider from VOUT to the VSENSE pin to reduce
the undershoot on VOUT during a low to high load
current transient. The overshoot during a high to low
load current transient is reduced by subtracting the
voltage that is on the DROOP pin from VREF. The
voltage on the IO pin is divided down with an external

Ω

11

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PRELIMINARY - March 1, 2000

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS

SC1154

FUNCTIONAL DESCRIPTION (cont.)

resistor divider, and connected to the DROOP pin.
Thus, under loaded conditions, VOUT is regulated to
Vout = Vref • (1+R7/R8) - IOUT • R2/(R1+R2).

Inhibit

The inhibit pin is a TTL compatible digital pin that is
used to enable the controller. When INH is low, the
output drivers are low, the soft start capacitor is dis­charged, the soft start current source is disabled, and
the controller is in a low I
the short across the soft start capacitor is removed, the
soft start current source is enabled, and normal con­verter operation begins. When the system logic supply
is connected to INH, it controls power sequencing by
locking out controller operation until the system logic
supply exceeds the input threshold voltage of the INH
circuit; thus the +12V supply and the system logic sup­ply (either +5V or 3.3V) must be above UVLO thresh­olds before the controller is allowed to start up.

VIN

The VIN undervoltage lockout circuit disables the con­troller while the +12V supply is below the 10V start
threshold during power-up. While the controller is dis­abled, the output drivers will be low, the soft start ca­pacitor will be shorted and the soft start current is dis­abled and the controller will be in a low I
VIN exceeds the start threshold, the short across the
soft start capacitor is removed, the soft start current
source is enabled and normal converter operation be­gins. There is a 2V hysteresis in the undervoltage
lockout circuit for noise immunity.

state. When INH goes high,

Q

state. When

Q

Thus these resistor values will determine the soft start
charging current. The maximum current that can be
sourced by REFB is 500µA.

Power Good

The power good circuit monitors for an undervoltage
condition on VOUT. If VSENSE is 7% (nominal) below
VREF, then the power good pin is pulled low. The
PWRGD pin is an open drain output.

Overvoltage Protection

The overvoltage protection circuit monitors VOUT for
an overvoltage condition. If VSENSE is 15% above
VREF, than a fault latch is set and both output drivers
are turned off. The latch will remain set until VIN goes
below the undervoltage lockout value. A 1ms deglitch
timer is included for noise immunity.

Overcurrent Protection

The overcurrent protection circuit monitors the current
through the high side FET. The overcurrent threshold
is adjustable with an external resistor divider between
IO and AGND, with the divider voltage connected to
the OCP pin. If the voltage on the OCP pin exceeds
100mV, then a fault latch is set and the output drivers
are turned off. The latch will remain set until VIN goes
below the undervoltage lockout value. A 1ms deglitch
timer is included for noise immunity. The OCP circuit
is also designed to protect the high side FET against a
short-to-ground fault on the terminal common to both
power FETs (VPHASE).

Drive Regulator

Soft Start

The drive regulator provides drive voltage to the low
side driver, and to the high side driver when the high

The soft start circuit controls the rate at which VOUT
powers up. A capacitor is connected between SS and
AGND and is charged by an internal current source.

side driver is configured as a floating driver. The mini­mum drive voltage is 7V. The minimum short circuit
current is 100mA.

The value of the current source is proportional to the
reference voltage so the charging rate of C

is also

SS

proportional to the reference voltage. By making the
charging current proportional to VREF, the power-up
time for VOUT will be independent of VREF. Thus, C

SS

can remain the same value for all VID settings. The
soft start charging current is determined by the follow­ing equation: I

SS

/5. Where I

REFB

is the current

REFB

= I
flowing out of the REFB pin. It is recommended that
no additional loads be connected to REFB, other than
the resistor divider for setting the hysteresis voltage.

12

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PRELIMINARY - March 1, 2000

APPLICATION CIRCUIT

+12V

+12V

+5V

+5V

C9

+5V

+12V

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER

SC1154

FOR ADVANCED PROCESSORS

+

_

Vout

Vout

GND

Vin +5 to +12V

+

_

J1

123

4

0.1

C20

0.1

L1

1uH

C19

150uF 16V

C18

150uF 16V

J2

12345

C27

C26

C25

C24

C23

C22

C21

6

0.1

460uF 6.3V

470uF 6.3V

470uF 6.3V

470uF 6.3V

470uF 6.3V

470uF 6.3V

C17

PWRGD

INHIB

R10

10k

+5V

C11

0.01

R9

10k

+5V

28

PwrGd

U1

SC1154

Iout1Droop2OCP3Vhyst4Vrefb5Vsense6AnaGnd7Slowst8Bias9Lodrv10Lohib11DrvGnd12LowDr13DRV

109876

S1

12345

23

24

25

26

27

VID4

VID3

VID2

VID1

VID0

C6

0.1

R5

100

R6

20k

C3

0.01

C4

R3

2.7k

R4

1k

0.01

150uF 16V

Ra*

C16

0.1

C12

0.1

22

21

Ioutlo

Inhibit

C5

0.001

19

20

Hisense

Losense

+5V

C8

0.01

C7

0.1

0

18

BootLo

pin18

Q1

R11

Dopt.

IRL3103S

2.2

17

MBR0530

L2

1.5uH

Rb*

0

D1

MBRD1035

C14

0.33

Q2

IRL2203S

+12V

R12

C13

0.33

16

HiDr

3.9

C9

2.2uF 16V

15

Boot

Vin12

C8

14

2.2uF 16V

* Only one resistor/jumper to be installed, either Ra or Rb.

R7

150

R8

10k

R1

2k

R2

1k

C2

0.01

13

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER

SC1154

FOR ADVANCED PROCESSORS

PRELIMINARY - March 1, 2000

MATERIALS LIST

Quantity Reference Part/Description Vendor Notes

1 C5 0.001µF
6 C1-C4, C8, C11 0.01µF
3 C17-C19 150µF, 16V (TPS) AVX
7 C6,C7,C9,C12,C16,C20, C27 0.1µF
2 C13,C14 0.33µF
6 C21-C26 470µF, 6.3V (TPS) AVX
2 C10,C15 2.2µF, 16V
1 D1 MBRD1035 MOT
1 L1 1µH, DO5022P-102 Coilc raf t
1 L2 1.5µH, DO5022P-152HC Coil craft
1 Q1 IRL3103NS, D2PAK Int. Rect.
1 Q2 IRL2203NS, D2PAK Int. Rect.
2RA,RB

1R1 2K
2 R2,R4 1K
1R3 2.7K
1 R5 100
1 R6 20K
1 R7 150
3 R8,R9,R10 10K
1 R11 2.2
1 R12 3.9
1 U1 SC1154, SO-28 SEMTECH

Ω

0

Layout guidelines

1. Locate R8 and C5 close to pins 6 and 7.

2. Locate C6 close to pins 5 and 7.

3. Components connected to IOUT, DROOP, OCP, VHYST, VREFB, VSENSE, and SOFTST should be refer­enced to AGND.

4. The bypass capacitors C10 and C15 should be placed close to the IC and referenced to DRVGND.

5. Locate bootstrap capacitor C13 close to the IC.

6. Place bypass capacitor C14 close to Drain of the top FET and Source of the bottom FET to be effective.

7. Route HISENSE and LOSENSE close to each other to minimize induced differential mode noise.

8. Bypass a high frequency disturbance with ceramic capacitor at the point where HISENSE is connected to Vin.

9. Input bulk capacitors should placed as close as possible to the power FETs because of the very high ripple cur­rent flow in this pass.

10. If Schottky diode used in parallel with a synchronous (bottom) FET, to achieve a greater efficiency at lower
Vout settings, it needs to be placed next to the aforementioned FET in very close proximity.

11. Since the feedback path relies on the accurate sampling of the output ripple voltage, the best results can be
achieved by connecting the AGND to the ground side of the bulk output capacitors.

12. DRVGND pin should be tight to the main ground plane utilizing very low impedance connection, e.g., multiple
vias.

13. In order to prevent substrate glitching, a small (0.5A) Schottky diode should be placed in close proximity to the
chip with the cathode connected to BOOTLO and anode connected to DRVGND.

14

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PRELIMINARY - March 1, 2000

EVALUATION BOARD ARTWORK

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS

SC1154

TOP LAYER

BOTTOM LAYER

15

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PRELIMINARY - March 1, 2000

EVALUATION BOARD LAYOUT

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS

SC1154

TOP VIEW

BOTTOM VIEW

16

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PRELIMINARY - March 1, 2000

TEST DATA

100.0

95.0

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS

SC1154 Efficiency

SC1154

%

%

90.0

85.0

80.0

75.0

70.0

65.0

60.0
0 5 10 15 20

Vin =

Output Current, A

SC1154 Voltage Regulation

5.00

4.00

3.00

2.00

1.00

0.00
02468101214

-1.00

-2.00

-3.00

-4.00

-5.00
Output Current, A

3.5

2.8

2.0

1.5

3.5

2.8
2

1.5

17

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PRELIMINARY - March 1, 2000

OUTLINE - SO-28

PROGRAMMABLE SYNCHRONOUS
DC/DC HYSTERETIC CONTROLLER
FOR ADVANCED PROCESSORS

SC1154

ECN00-904

18

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320