Datasheet SC1153CSW.TR Datasheet (Semtech Corporation)

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

SC1153

PRELIMINARY - October 3, 2000

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DESCRIPTION

The SC1153 is a low-cost, full featured, synchronous
voltage-mode controller designed for use in single
ended power supply applications where efficiency is of
primary concern. Synchronous operation allows for the
elimination of heat sinks in many applications. The
SC1153 is ideal for implementing DC/DC converters
needed to power advanced microprocessors, such as
Pentium
figurations. Internal level-shift, high-side drive circuitry,
and preset shoot-thru control, allows for use of inex­pensive n-channel power switches.

SC1153 features include an integrated 5-bit VID
temperature compensated voltage reference, triangle
wave oscillator, current limit comparator, frequency
shift over-current protection, and an accessible, inter­nally compensated error amplifier. Power good signal­ing, logic compatible shutdown, and over voltage pro­tection are also provided.

The SC1153 operates at a fixed 200KHz, providing an
optimum compromise between efficiency, external
component size, and cost.

®

lll, in both single and multiple processor con-

DAC,

FEATURES

•= Low cost / full featured

•= Synchronous operation

•= 5 Bit VID programmable output

•= On-chip power good and OVP functions

•= Designed to meet Intel VRM 8.4 (Pentium

®

IlI)

•= 1.3V to 3.5V Range, 1% tolerance

APPLICATIONS

•= Pentium

®

IlI Core Supply

•= Multiple Microprocessor Supplies

•= Voltage Regulator Modules (VRM)

•= Programmable Power Supplies

•= High Efficiency DC/DC Conversion

ORDERING INFORMATION

DEVICE

SC1153CSW.TR SO-20 0 - 125°C

Note:
(1) Only available in tape and reel packaging. A reel
contains 1000 devices.

(1)

PACKAGE TEMP. RANGE (TJ)

Top View

(20-Pin SOIC)

BLOCK DIAGRAMPIN CONFIGURATION

VID4
VID3
VID2
VID1
VID0

VOSENSE

PWRGOOD

OVP

1.25V REF

D/A

OPEN COLLECTORS

VCC

VCC CS- CS+

70mV

OSCILLATOR

200kHz

ERROR
AMP

CURRENT LIMIT

GND

SHUTDOWN

BSTH

UPPER FET
LEVEL SHIFT
AND DRIVE

R

Q

S

SHOOT-THRU

CONTROL

SYNCHRONOUS

FET DRIVE

DH

PGNDH

BSTL

DL

PGNDL

Pentium is a registered trademark of Intel Corporation

1

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

PRELIMINARY - October 3, 2000

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Maximum Units

to GND V

V

CC

IN

PGND to GND ± 1 V
BST to GND -0.3 to 15 V
Thermal Resistance

Junction to Case
Thermal Resistance

Junction to Ambient
Operating

Temperature Range
Storage

Temperature Range
Lead Temperature

(Soldering) 10 sec

T

T

θ

JC

θ

JA

T

STG

LEAD

A

-0.3 to 7 V

30 °C/W

90 °C/W

0 to 70 °C

-65 to +150 °C

300 °C

SC1153

ELECTRICAL CHARACTERISTICS

Unless specified: VCC = 4.75V to 5.25V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV; TJ = 25oC

PARAMETER CONDITIONS MIN TYP MAX UNITS

Output Voltage I
Supply Voltage V
Supply Current V
Load Regulation I
Line Regulation All VID codes
Gain (A

)V

OL

Current Limit Voltage 60 70 80 mV
Oscillator Frequency 180 200 220 kHz
Oscillator Max Duty Cycle 90 95 %
DH Sink/Source Current BST
DL Sink/Source Current BST
OVP Threshold Voltage 120 %
OVP Source Current V
Power Good Threshold

Voltage

(1)

= 2A

O

CC

= 5.0 5 mA

CC

= 0.3A to 15A

O

to V

OSENSE

- DH = 4.5V, DH - PGNDH = 2V 1 A

H

- DL = 4.5V, DL - PGNDL = 2V 1 A

L

= 3V 10 mA

OVP

(1)

(1)

O

See Output Voltage Table.

4.2 7 V

1%

0.5 %
35 dB

90 110 %

Dead Time 50 100 ns

NOTE:

(1) Specification refers to application circuit (Figure 1.).
(2) This part is ESD sensitive. Use of standard ESD handling precautions is required.

2

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

PRELIMINARY - October 3, 2000

PIN DESCRIPTION

Pin # Pin Name Pin Function

1 GND Small Signal Analog and Digital Ground
2 VCC Chip Supply Voltage

SC1153

3 OVP High Signal Out if V
4 PWRGOOD

(1)

Open collector logic output, high if VO within 10% of setpoint

> Setpoint + 20%

O

5 CS(-) Current Sense Input (negative)
6 CS(+) Current Sense Input (positive)
7 PGNDH Power Ground for High Side Switch
8 DH High Side Driver Output

9 NC Not Connected
10 PGNDL Power Ground for Low Side Switch
11 DL Low Side Driver Output
12 BSTL Vcc for Low Side Driver (Boost)
13 BSTH Vcc for High Side Driver (Boost)
14 SHUTDOWN

(1)

Logic Low shuts down the converter
15 VOSENSE Top end of internal feedback chain
16 VID4
17 VID3
18 VID2
19 VID1
20 VID0

(1)

(1)

(1)

(1)

(1)

Programming Input (MSB)

Programming Input

Programming Input

Programming Input

Programming Input (LSB)

NOTE:

(1) All logic level inputs and outputs are open collector TTL compatible.

PIN CONFIGURATION

3

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PRELIMINARY - October 3, 2000

APPLICATION CIRCUIT

5V IN

+

0.1uF

C3

1000uF

1000uF

+

C2

C1

C4

1000uF

R2
10k

+

R5
10

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

L1

Q1

4 uH

Q2

D1
1N5817

R1
5mOhm

C5
1000uF

C6

C8

1000uF

1000uF

+

+

+

+

C7
1000uF

1000uF

+

C9
1000uF

SC1153

C10

VCCP

+

C12

0.1uF

12V IN

OVP
VID0
VID1
VID2
VID3
VID4

SHUTDOWN
PWRGOOD

C13

0.1uF

2

3
20
19
18
17
14

1
10

9

U1

VCC
OVP
VID0
VID1
VID2
VID3
SHUTDOWN
GND
PGNDL
NC

SC1153CS

CS+

VOSENSE

PWRGOOD

VID4

BSTH

PGNDH

BSTL

R4 1.00k

6
5

CS-

15
4
16
13
8

DH

7
11

DL

12

R3 2.32k

C11

0.1uF

Pentium® ll Power Supply

Figure 1.

MATERIALS LIST

Quantity Reference Part/Description Vendor Notes

4 C1,C11-C13 0.1µF Ceramic Various
9 C2-C10 1000µF/6.3V SANYO MV-GX or equiv. Low ESR
1 D1 1N5817 Various
1 L1 4µH 8 Turns 16AWG on MICROMETALS T50-52D core
2 Q1, Q2 See notes See notes FET selection requires trade-off between efficiency

DS(ON)

= 22 mΩ

1R1
1R2
1R3
1R4
1R5

5mΩ
10kΩ, 5%, 1/8W

2.32kΩ, 1%, 1/8W
1kΩ, 1%, 1/8W
10Ω, 5%, 1/8W

and cost. Absolute maximum R

IRC OAR-1 Series
Various
Various
Various
Various

1 U1 SC1153CS SEMTECH

4

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

PRELIMINARY - October 3, 2000

OUTPUT VOLTAGE TABLE

Unless specified: VCC = 5.00V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV; TJ = 25°C

SC1153

PARAMETER CONDITIONS VID

43210

Output Voltage I

= 2A in Application Circuit 01111 1.287 1.300 1.313 V

O

(Figure 1) 01110 1.336 1.350 1.364

01101 1.386 1.400 1.414
01100 1.435 1.450 1.465
01011 1.485 1.500 1.515
01010 1.534 1.550 1.566
01001 1.584 1.600 1.616
01000 1.633 1.650 1.667
00111 1.683 1.700 1.717
00110 1.732 1.750 1.768
00101 1.782 1.800 1.818
00100 1.832 1.850 1.868
00011 1.881 1.900 1.919
00010 1.931 1.950 1.969
00001 1.980 2.000 2.020
00000 2.030 2.050 2.070
11111 1.980 2.000 2.020
11110 2.079 2.100 2.121
11101 2.178 2.200 2.222
11100 2.277 2.300 2.323
11011 2.376 2.400 2.424
11010 2.475 2.500 2.525
11001 2.574 2.600 2.626
11000 2.673 2.700 2.727
10111 2.772 2.800 2.828
10110 2.871 2.900 2.929
10101 2.970 3.000 3.030
10100 3.069 3.100 3.131
10011 3.168 3.200 3.232
10010 3.267 3.300 3.333
10001 3.366 3.400 3.434
10000 3.465 3.500 3.535

MIN TYP MAX UNITS

5

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

PRELIMINARY - October 3, 2000

CHARACTERISTIC CURVES

SC1153 Efficiency in Application Circuit (Figure 1).

100%

95%

90%

SC1153

Vo=3.5V

85%

Efficiency

80%

75%

70%

0246810121416

Output Current (Amps)

SC1153 Regulation in Application Circuit (Figure 1).

0

-5

-10

1.8V

3.0V

2.5V

2.0V

Vout (mV)

-15

∆

∆

∆

∆

-20

-25
0246810121416

Output Current (Amps)

6

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320

PRELIMINARY - October 3, 2000

OUTLINE DRAWING SO-20

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

SC1153

Ref. MS-013AC

THEORY OF OPERATION

The voltage at the VOSENSE pin is applied, through the internal precision resistor feedback chain, to the inverting
input of the error amplifier. The non-inverting input of the error amplifier is supplied with a DC voltage derived by
the DAC from the internal trimmed bandgap voltage reference. The output of the error amplifier is compared to the
triangular output of the internal oscillator to generate a fixed frequency, variable duty cycle pulse train. The internal
oscillator uses an on-chip capacitor and precision trimmed current sources to set the frequency to 200kHz.

The generated pulse train is gated with the output of the current limit latch and the inhibit signal to produce a drive
signal for the upper FET. It is also inverted to produce a drive signal for the lower FET. These FET drive signals
are modified by the “shoot-through control” circuitry so that the top FET turn-on is delayed until the bottom FET has
turned off, and visa-versa.

The current limit latch is set (ending the upper FET drive pulse early) if the current limit comparator indicates an
overcurrent condition. The latch is reset at the start of each oscillator period.

The PWRGOOD and OVP signals are derived from the voltage at the VOSENSE pin by comparators fed from the
internal feedback chain.

ECN00-1346

7

© 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320