Datasheet SC1152 Datasheet (SEMTECH)

V

V

查询SC1152供应商

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

April 28, 1998

TEL:[phone] F A X:805- 498- 3804 WEB:http://www.semtech.com

DESCRIPTION

The SC1152 is a low-cost, full featured, synchronous
voltage-mode controller designed for use in single
ended power supply applicat ions where efficiency is of
primar y c onc er n. Synchronous operation allows for the
elimination of heat si nk s i n many applicati ons. The
SC1152 is ideal for implementing DC/DC converters
needed to power advanced microprocessors such as
Pentium
cessor configurations. Internal level-shif t, high-side
drive circuitry, and preset shoot-thru control, allows for
use of inexpensive n-channel power switches.

SC1152 featur es i nc lude an integrated 5-bit V
temperat ur e c ompensated voltage r eference, triangle
wave oscillator, current limit comparator, frequency
shift over-current protection, and an accessible, inter­nally compensated error ampli fier. Power good signal­ing, logic compatibl e shutdown, and over voltage pro­tection ar e also provided.

The SC1152 operates at a fixed 200KHz, providing an
optim um compromi se between efficiency, external
component siz e, and cost.

®

ll (Klamath), in bot h si ngle and multiple pro-

DAC,

ID

SC1152

FEATURES

Low cost / full featured

•

• Synchronous operation

• 5 Bit V

• On-chip power good and OVP functions

• Designed to meet Intel VRM8.1 (Pentium

APPLICATIONS

Pentium® II (Klamath) Core Supply

•

• Multiple Microprocessor Supplies

• Voltage Regulator Modules (VRM)

• Programmable Power Supplies

• High Ef ficiency DC/DC Conversion

ORDERING INFORMATION

DEVICE

SC1152CS SO-20 0 - 125°C

Note:
(1) Add suffix ‘TR’ f or tape and reel.

DAC programmable output

ID

(1)

PACKAGE TEMP. RANGE (TJ)

®

II)

PIN CONFIGURATION

BLOCK DIAGRAM

Top View

CS(-)

70mV

OSCILLATOR

CS(+)

CURRENT LIMIT

+

-

200 kHz

+

­ERROR

AMP

GND

GND

VCC

1.25V REF

ID4

D/A AND

VID3

SHUT-

VID2

DOWN

VID1

LOGIC

ID0

VOSENSE

OPEN COLLECTORS

(20-Pin SOIC)

PWRGOOD

VCC

OVP

VCC

DECODED SHUTDOWN SIGNAL

+

­+

-

+

-

SHUTDOWN

BSTH

UPPER FET

R

Q

S

­+

LEVEL SHIFT

AND DRIVE

SHOOT-THRU

CONTROL

SYNCHRONOUS

FET

DRIVE

DH

PGNDH

BSTL

DL

PGNDL

Pentium is a registered trademark of Intel Corporation

1

© 1998 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

April 28, 1998

ABSOLU TE MAXIMUM RATINGS

Parameter Symbol Maximum Units

to GND V

V

CC

IN

PGND to GND ± 1 V
BST to GND -0.3 to 15 V
Thermal Resistance

Junction t o Case
Thermal Resistance

Junction t o A mbient
Operating

Temperat ur e Range
Storage

Temperat ur e Range
Lead Temperat ur e

(Solderi ng) 10 sec

T

T

θ

JC

θ

JA

T

STG

LEAD

A

-0.3 to 7 V

30 °C/W

90 °C/W

0 to 70 °C

-65 to +150 °C

300 °C

SC1152

ELECTRICAL CHARACTERISTICS

Unless specifi ed: VCC = 4.75V to 5.25V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV; TJ = 25oC

PARAMETER CONDITIONS MIN TYP MAX UNITS

(1)

Output Voltage I
Supply Vol tage V
Supply Current V
Load Regulation I
Line Regulation All VID codes
Gain (A

)V

OL

= 2A

O

CC

= 5.0 5 mA

CC

= 0.3A to 15A

O

to V

OSENSE

(1)

(1)

O

Current Limit Voltage 60 70 80 mV
Oscillator Frequency 180 200 220 kHz
Oscillator Max Duty Cycle 90 95 %
DH Sink/Sour c e Cur r ent BST
DL Sink/Sour c e Cur r ent BST

- DH = 4.5V, DH - P GNDH = 2V 1 A

H

- DL = 4.5V, DL - P GNDL = 2V 1 A

L

OVP Threshold V oltage 120 %
OVP Source Current V

= 3V 10 mA

OVP

Power Good Threshold
Voltage

See Table 1.

4.2 7 V

1%

0.5 %
35 dB

90 110 %

Dead Tim e 50 100 ns

NOTE:

(1) Specification refers to application c ircuit (Figur e 1.).

2

© 1998 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

April 28, 1998

PIN DESCRIPTION

Pin # Pin Name Pin Function

1 GND Small Signal Analog and Di gital Ground

SC1152

2V

CC

3 OVP High Signal Out if V
4 PWRGOOD

(1)

Chip Supply V oltage

> Setpoi nt + 20%

O

Open coll ec tor logic output, high if VO within 10% of setpoint
5 CS(-) Current Sense Input (negative)
6 CS(+) Current Sense Input (posi tive)
7 PGNDH Power Ground for High Side Switc h
8 DH High Side Driver Output
9 NC Not Connected

10 PGNDL Power Ground for Low Si de S wi tch
11 DL Low Side Driver Output
12 BSTL Vcc for Low Side Driver (Boost)
13 BSTH Vcc for High Side Driv er (Boost)
14 SHUTDOWN

(1)

Logic Low shuts down the convert er

15 VOSENSE Top end of internal feedback chain
16 VID4
17 VID3
18 VID2
19 VID1
20 VID0

(1)

(1)

(1)

(1)

(1)

Programming Input (MSB)

Programming Input

Programming Input

Programming Input

Programming Input (LSB)

NOTE:

(1) All logic lev el inputs and outputs are open collec tor TTL compati ble.

PIN CONFIGURATION

3

© 1998 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY PARK CA 91320

April 28, 1998

APPLICATION CIRCUIT

5V IN

+

0.1uF

C3

1000uF

C2

1000uF

+

C1

C4

1000uF

R2
10k

+

PROGRAMMABLE SYNCHRONOUS DC/DC

SC1152

CONTROLLER FOR ADVANCED PROCESSORS

L1

Q1

4 uH

Q2

R5
10

D1
1N5817

R1
5mOhm

C5
1000uF

+

C6
1000uF

C8

C10

1000uF

1000uF

+

+

+

+

C7

C9

1000uF

1000uF

VCCP

+

C12

0.1uF

12V IN

OVP
VID0
VID1
VID2
VID3
VID4

SHUTDOWN
PWRGOOD

C13

0.1uF

2

3
20
19
18
17
14

1
10

9

U1

VCC
OVP
VID0
VID1
VID2
VID3
SHUTDOWN
GND
PGNDL
NC

SC1152CS

CS(+)

CS(-)

VOSENSE

PWRGOOD

BSTH

PGNDH

BSTL

VID4

6
5
15
4
16
13
8

DH

7
11

DL

12

R4 1.00kR3 2.32k

C11

0.1uF

Pentium® ll Power Supply

Figure 1.

MATERIALS LIST

Quantity Reference Part/Description Vendor Notes

4 C1,C11-C13 0.1µF Ceramic Various
9 C2-C10 1000µF/6.3V SANYO MV-GX or equiv. Low ESR
1 D1 1N5817 Various
1 L1 4µH 8 Turns 16AWG on MICROMETALS T 50- 52D c or e
2 Q1, Q2 See notes See notes FET select ion requires trade-off between effic iency

DS(ON)

= 22 m

Ω

1R1
1R2
1R3
1R4
1R5

5m

Ω

10kΩ, 5%, 1/8W

2.32kΩ, 1%, 1/8W
1kΩ, 1%, 1/8W
10Ω, 5%, 1/8W

and cost. Absolute maximum R
IRC OAR-1 Series
Various
Various
Various
Various

1 U1 SC1152CS SEMTECH

4

© 1998 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC

SC1152

CONTROLLER FOR ADVANCED PROCESSORS

April 28, 1998

OUTPUT VOLTAGE TABLE

Unless specifi ed: VCC = 4.75V to 5.25V; GND = PGND = 0V; FB = VO; 0mV < (CS(+) - CS(-)) < 60mV; TJ = 25°C

PARAMETER CONDITIONS VID

43210

Output Voltage

(1)

IO = 2A in Application Circ uit 00101 1.782 1.800 1.818 V
(Figure 1) 00100 1.832 1.850 1.868

00011 1.881 1.900 1.919
00010 1.931 1.950 1.969
00001 1.980 2.000 2.020
00000 2.030 2.050 2.070
11111 1.980 2.000 2.020
11110 2.079 2.100 2.121
11101 2.178 2.200 2.222
11100 2.277 2.300 2.323
11011 2.376 2.400 2.424
11010 2.475 2.500 2.525
11001 2.574 2.600 2.626
11000 2.673 2.700 2.727
10111 2.772 2.800 2.828
10110 2.871 2.900 2.929
10101 2.970 3.000 3.030
10100 3.069 3.100 3.131
10011 3.168 3.200 3.232
10010 3.267 3.300 3.333
10001 3.366 3.400 3.434
10000 3.465 3.500 3.535

MIN TYP MAX UNIT S

NOTE:

(1) All V ID codes not specifical ly listed are invalid and cause shutdown exactl y as i f the shutdown pin had been
asserted.

THEORY OF OPERATION

The v oltage at the V
input of the error ampli fier. The non-i nverting input of the error amplifier is supplied wit h a DC voltage derived by
the DAC fr om the internal t r immed bandgap voltage reference. The output of the error amplifier is compared to
the triangular output of the internal oscillator to generate a fix ed frequency, variable duty cycle pulse train. The
internal oscillator uses an on-chip capacitor and precision trimmed current sources to set the frequency to 200
kHz.
The generated pulse tr ain is gated with the output of the current limit latch and t he inhibit signal t o pr oduc e a
drive signal for the upper FET. It is also inverted to produce a drive signal for the lower FET. These FET drive
signals are modified by the “shoot-t hr ough c ontrol” circuitry so that the top FET t ur n- on is delayed until the bot tom
FET has turned off, and v isa-versa.
The current limit l atch is set (ending the upper FET dr ive pulse early) if the current limit comparator indicates an
overc ur r ent condition. The latch is reset at the start of each oscillator period.
The PWRGOOD and OVP signals are derived from the voltage at the V
internal feedback chain.

pin is applied, through the internal precision resistor feedbac k c hain, to the inverting

OSENSE

pin by com par ators fed from the

OSENSE

5

© 1998 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY PARK CA 91320

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

April 28, 1998

CHARACTERISTIC CURVES

SC1152 Efficiency in A pplication Circ uit (Figure 1).

95.0%

90.0%

3.50 Volts

85.0%

Efficiency

80.0%

75.0%

2.00 Volts

1.80 Volts

3.00 Volts

2.50 Volts

SC1152

70.0%

0.000 2.000 4.000 6.000 8.000 10.000 12.000 14.000 16.000

Output Current (Amps)

SC1152 Regulati on in Application Circuit (Figur e 1) .

0.000

-0.005

Delta 1.8

-0.010

Delta 3.5

Vout (V)

∆

-0.015

Delta 2.0

-0.020

Delta 2.5

-0.025

0.000 2.000 4.000 6.000 8.000 10.000 12.000 14.000 16.000

Output Current (Amps)

Delta 3.0

6

© 1998 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY PARK CA 91320

April 28, 1998

OUTLINE DRAWING SO-20

PROGRAMMABLE SYNCHRONOUS DC/DC
CONTROLLER FOR ADVANCED PROCESSORS

SC1152

Ref. MS-013AC

7

© 1998 SEMTECH CORP. 652 MITCHELL ROA D NE WBURY PARK CA 91320