The SC1104A/B is a versatile voltage-mode PWM controller designed for use in single ended DC/DC power
supply applications. A simple, fixed frequency high efficiency buck regulator can be implemented using the
SC1104A/B with a minimum of external components.
Internal level shift and drive circuitry eliminates the need
for an expensive P-channel, high-side switch. The small
device footprint allows for compact circuit design.
SC1104A/B features include temperature compensated
voltage reference, triangle wave oscillator, current limit
comparator and an externally compensated error amplifier. Current limit is implemented by sensing the voltage
drop across the top FET’s R
DS(ON)
.
The SC1104 operates at fixed frequencies of
300kHz(A) or 600kHz(B) providing an optimum compromise between efficiency, external component size,
and cost. 600kHz switching frequency is reserved for
the SC1104B, +5VCC operation only.
SC1104A/B has a thermal protection circuit, which is
activated if the junction temperature exceeds 150°C.
Up to +14V input, 300kHz operation (SC1104A)
Up to +7V input, 600kHz operation (SC1104B)
High efficiency (>90%)
1% Reference voltage accuracy
Hiccup mode over current protection
Robust output drive
R
Current sensing
DS(ON)
Industrial temperature range
8-Lead SOIC package. Pb-free package available,
fully WEEE and RoHS compliant
Applications
Termination supplies
Low cost microprocessor supplies
Peripheral card supplies
Industrial power supplies
High density DC/DC conversion
Typical Application Circuit
Typical Distributed Power Supply
C1
510-1500pF
U1
COMP /SS
GND
DL
DH
SC1104A/B
SENSE
VCC
PHASE
BST
R1
200-2k
C2
0.01
1
2
3
4
C3
1
8
7
6
5
R6
1-5.1
R7
1-5.1
Q1
Si4884DY
Q2
Si4874DY
R3
1.00k
D1
MBRA130L
C9
0.1
(opt)
+
C4
10.0
R4
2.32k
R5
0.1-0.33
L1
1.5-6.8uH
C8
C10
220/4V
200-1k
R8
opt
D2
C5
47/16V
C11
220/4V
C6
47/16V
C12
220/4V
C7
47/16V
C13
220/4V
Vin 5 to 12V
_
+
C14-17
3.3V
1.0
_
Revision: November 22, 2006
Figure 1
1
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Page 2
SC1104A/B
POWER MANAGEMENT
Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device
reliability.
Notes:
(1) In place of “X”: A = 300kHz, V
B = 600kHz, V
(2) Only available in tape and reel packaging. A reel
contains 2500 devices.
(3) Lead free product. This product is fully WEEE and
RoHS compliant.
yyww = Date Code (Example: 0012)
xxxxxxxx = Semtech Lot No. (Example: E90101-1)
5
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Page 6
POWER MANAGEMENT
Theory of Operation
Synchronous Buck Converter
SC1104A/B
The output voltage of the synchronous converter is set
and controlled by the output of the error amplifier. The
inverting input of the error amplifier receives its voltage
from the SENSE pin. The non-inverting input of the error
amplifier is connected to an internal 1V reference.
The error amplifier output is connected to the
COMPensation pin. The error amplifier generates a current proportional to (Vsense – 1V), which is the COMP
pin output current (Transconductance ~ 12mS). The
voltage on the COMP pin is the integral of the error amplifier current. The COMP voltage is the non-inverting
input to the PWM comparator and controls the duty cycle
of the MOSFET drivers. The size of capacitor Ccomp controls the stability and transient response of the regulator. The larger the capacitor, the slower the COMP voltage changes, and the slower the duty cycle changes.
The inverting input voltage of the PWM comparator is
the triangular output of the oscillator.
When the oscillator output voltage drops below the COMP
voltage, the comparator output goes high. This pulls DL
low, turning off the low-side FET. After a short delay (“dead
time”), DH is pulled high, turning on the high-side FET.
When the oscillator voltage rises back above the error
amplifier output voltage, the comparator output goes low.
This pulls DH low, turning off the high-side FET, and after
a dead time delay, DL is pulled high, turning on the lowside FET. The dead time delay is determined by a
monostable on the chip.
The triangle wave minimum is about 1V, and the maximum is about 2V. Thus, if Vcomp = 0.9V, high side duty
cycle is the minimum (~0%) , but if Vcomp is 2.0V, duty
cycle is at maximum ( ~90%).The internal oscillator uses
an on-chip capacitor and trimmed precision current
sources to set the oscillation frequency to 300kHz
(SC1104A) or 600kHz (SC1104B).
Figure 1 shows a 3.3V output converter. If the Vout <3.3V,
then the SENSE voltage < 1V. In this case the error
amplifier will be sourcing current into the COMP pin so
that COMP voltage and duty cycle will gradually increase.
If Vout > 3.3V, the error amplifier will sink current and
reduce the COMP voltage, so that duty cycle will decrease.
The circuit will be in steady state when Vout =3.3V ,
Vsense = 1V, Icomp = 0 . The COMP voltage and duty
cycle depend on Vin.
Under Voltage Lockout
The under voltage lockout circuit of the SC1104A/B assures that both high-side and low-side MOSFET driver
outputs remain in the off state whenever the supply voltage drops below set parameters. Lockout occurs if V
falls below 4.2V typ.
R
Current Limiting
DS(ON)
In case of a short circuit or overload, the high-side (HS)
FET will conduct large currents. To prevent damage, in
this situation, large currents will generate a fault condition and begin a soft start cycle.
While the HS driver is on, the phase voltage is compared
to the Vcc pin voltage. If the phase voltage is 200mV
lower than Vcc, a fault is latched and the soft start cycle
begins.
The voltages are compared during the middle of the HS
pulse, to prevent transients from affecting the accuracy.
The sampling of the voltage across the top FET occurs
after a time delay t
= 100ns_typ from the time the
DELAY
DH is pulled high. This delay prevents the measurement
to be effected by ringing on the leading edge of the phase
node pulse. The duration of the sampling is t
SAMPLE
=
100ns_typ. It is being disabled at very low duty cycle when
tON < 300ns_typ. This feature allows for the orderly startup during the inrush of the current charging output capacitor and the fault free operation with extremely high
input/output voltage ratio, e.g., VIN = 12V and V
OUT
= 1V.
The over-current comparator (OC) is only active if the
phase node is > 3.3V. This means that in the case of
power source being < 3V the OC will be disabled even
though the rest of the circuitry is completely functional.
SC1104 still can be used for stepping down, e.g. 2.8V to
When choosing OC trip point one should consider the
Tempco of the MOSFETs Rds_on and SC1104’s Vtrip.
Also, any ringing on the Vcc and Phase nodes due to
parasitic L and C will have some effect on the OC Vtrip.
Example:
Iout_nom = 6A; assume I_max = 125% • Iout_nom =
7.5A
Rds_on = 0.014Ω; assume Rds_on_max
≈ 150% •
Rds_on = 0.02Ω
Voc = 7.5A • 0.02Ω = 150mV.
This proves that MOSFETs with R
= 0.014Ω @ 25°C
DS_ON
is the right choice.
Soft Start
The soft start (or hiccup) circuitry is activated when a
fault occurs. Faults occur for three reasons:
Closing the Loop
In order to have a stable closed loop system with optimum
transient response one should make sure that open-loop
frequency response has an adequate Gain & Phase
margins. The Bode plot of log. Gain vs Freq. and Phase
vs Freq. provide the necessary means for the circuit
evaluation. Loop stability defined by compensation
networks around transconductance error amplifier (EA)
and output divider, see below and output capacitor Cout
and inductor Lout.
Vout
Cn
Rn
EA
_
C
C
R
C
Gm
+
Cp
Vref
Ra
Rb
1) Under voltage (VCC < 4.2V)
2) Over temperature (die temperature > 150°C)
3) Over current in high side FET.
All faults are handled the same way. Both DH and DL are
forced low. The error amplifier is turned off, but a 2µA
current flows into the comp pin (soft start current). The
sink current reduces the Comp voltage down to 0.6V
over a period of a few milliseconds. When Vcomp ~ 0.6V,
the fault is cleared and the DL goes high. Also, the soft
start current changes polarity and begins to increase the
voltage on the Comp capacitor. The DH remains low, because Vcomp is less than the lowest excursion of the
oscillator ramp (1.0V). After a few ms, the Vcomp increases to about 1.0V and the DH will start to switch.
The duty cycle will gradually increase, and Vsns will increase. When Vsns ~ 1.00V, the error amplifier turns on
again. The circuit has now reached its operating point. If
a fault occurs during the soft start, the cycle will begin
again (drivers low, Vcomp decreasing down to 0.6V).
Typical transconductance error amplifier
The inductor and output capacitor form a “double pole”
at the frequency:
∏
1
•••
CoLo2
=
f
LC
The ESR of the output capacitor and the output capacitor
value create a “zero” at the frequency.
f
ESR
=
∏
1
•••
CoESR2
The “zero” and “pole” from the EA compensation network
are:
∏
1
•••
CcRc2
=
f
P
=
f
Z
∏
1
•••
CpRc2
The additional “lead” network RA, CN, RN can be used to
improve phase margin in case when output capacitors
with extra-low ESR are used and there is a need to
compensate for “high quality” output Lo, Co filter.