1997-07-01
Previous Releases :09.96
PageSubjects (changes since last revision)
4
19
52, 53
56, 57
62
SSC transfer rate at 10 MHz = 2.5 MHz
Figure reference corrected
Power saving modes : description of hardware power down mode added
Icc specification has been extended
for Master Mode corrected
t
SCLK
Edition 1997-07-01
Published by Siemens AG,
Bereich Halbleiter, MarketingKommunikation, Balanstraße 73,
81541 München
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Critical components
written approval of the Semiconductor Group of Siemens AG.
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2
with the express
Page 3
8-Bit CMOS Microcontroller
Advance Information
Full upward compatibility with SAB 80C515A
•
•
64k byte on-chip ROM (external program execution is possible)
•
256 byte on-chip RAM
•
2K byte of on-chip XRAM
•
Up to 64K byte external data memory
•
Superset of the 8051 architecture with 8 datapointers
•
Up to 10 MHz external operating frequency (1
•
On-chip emulation support logic (Enhanced Hooks Technology
•
Current optimized oscillator circuit and EMI optimized design
•
Eight ports : 48+1 digital I/O lines, 8 analog inputs
– Quasi-bidirectional port structure (8051 compatible)
– Port 5 selectable for bidirectional port structure (CMOS voltage levels)
•
Full-CAN controller on-chip
– 256 register/data bytes are located in external data memory area
– max.1 MBaud at 8-10 MHz operating frequency
•
Three 16-bit timer/counters
– Timer 2 can be used for compare/capture functions
µ
s instruction cycle time at 6 MHz external clock)
TM
)
C515C
(further features are on next page)
Figure 1
C515C Functional Units
Enhanced Hooks Technology
Semiconductor Group31997-07-01
TM
is a trademark of Siemens AG
.
Page 4
Features (continued) :
•
10-bit A/D converter with multiplexed inputs and built-in self calibration
•
Full duplex serial interface with programmable baudrate generator (USART)
•
SSC synchronous serial interface (SPI compatible)
– Master and slave capable
– Programmable clock polarity / clock-edge to data phase relation
– LSB/MSB first selectable
– 2.5 MHz transfer rate at 10 MHz operating frequency
•
Seventeen interrupt vectors, at four priority levels selectable
Power saving modes
– Slow-down mode
– Idle mode (can be combined with slow-down mode)
– Software power-down mode with wake-up capability through INT0
– Hardware power-down mode
•
CPU running condition output pin
•
ALE can be switched off
•
Multiple separate VCC/VSS pin pairs
•
P-MQFP-80-1 package
•
Temperature Ranges :SAB-C515C-8R
SAF-C515C-8R
SAH-C515C-8R
T
= 0 to 70 ° C
A
T
= -40 to 85 ° C
A
T
= -40 to 110 ° C
A
C515C
pin
The C515C is an enhanced, upgraded version of the SAB 80C515A 8-bit microcontroller which
additionally provides a full CAN interface, a SPI compatible synchronous serial interface, extended
power save provisions, additional on-chip RAM, 64K of on-chip program memory, two new external
interrupts and RFI related improvements. With a maximum external clock rate of 10 MHz it achieves
s at 6 MHz). The C515C is mounted in a P-MQFP-80 package.
a 600 ns instruction cycle time (1
Ordering Information
TypeOrdering CodePackageDescription
SAB-C515C-8RMQ67121-DXXXX P-MQFP-80-1with mask programmable ROM (10 MHz)
SAF-C515C-8RMQ67121-DXXXXP-MQFP-80-1with mask programmable ROM (10 MHz)
Note: Versions for extended temperature ranges – 40 ° C to 110 ° C (SAH-C515C-LM and SAH-
C515C-8RM) are available on request. The ordering number of ROM types (DXXXX
extensions) is defined after program release (verification) of the customer.
µ
(8-Bit CMOS microcontroller)
ext. temp. – 40 ° C to 85 ° C
ext. temp. – 40 ° C to 85 ° C
Semiconductor Group41997-07-01
Page 5
C515C
Figure 2
Logic Symbol
Semiconductor Group51997-07-01
Page 6
C515C
Figure 3
C515C Pin Configuration (P-MQFP-80-1, Top View)
Semiconductor Group61997-07-01
Page 7
Table 1
Pin Definitions and Functions
SymbolPin NumberI/O*)Function
P-MQFP-80
C515C
RESET
VAREF3–
VAGND4–
P6.0-P6.712-5I
*) I = Input
O = Output
1I
RESET
A low level on this pin for the duration of two machine
cycles while the oscillator is running resets the C515C. A
small internal pullup resistor permits power-on reset
using only a capacitor connected to VSS.
Reference voltage for the A/D converter
Reference ground for the A/D converter
Port 6
is an 8-bit unidirectional input port to the A/D converter.
Port pins can be used for digital input, if voltage levels
simultaneously meet the specifications high/low input
voltages and for the eight multiplexed analog inputs.
Semiconductor Group71997-07-01
Page 8
Table 1
Pin Definitions and Functions (cont’d)
SymbolPin NumberI/O*)Function
P-MQFP-80
C515C
P3.0-P3.715-22
15
16
17
18
19
20
21
22
I/O
Port 3
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 3 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 3 pins being
externally pulled low will source current ( I
, in the DC
IL
characteristics) because of the internal pullup resistors.
Port 3 also contains the interrupt, timer, serial port and
external memory strobe pins that are used by various
options. The output latch corresponding to a secondary
function must be programmed to a one (1) for that
function to operate. The secondary functions are
assigned to the pins of port 3, as follows:
P3.0 RXDReceiver data input (asynch.) or
data input/output (synch.) of serial
interface
P3.1 TXDTransmitter data output (asynch.) or
clock output (synch.) of serial
interface
P3.2 INT0
External interrupt 0 input / timer 0
gate control input
is an 1-bit quasi-bidirectional I/O port with internal pull-up
resistor. When a 1 is written to P7.0 it is pulled high by an
internal pull-up resistor, and in that state can be used as
input. As input, P7.0 being externally pulled low will
source current ( I
, in the DC characteristics) because of
IL
the internal pull-up resistor. If P7.0 is used as interrupt
input, its output latch must be programmed to a one (1).
The secondary function is assigned to the port 7 pin as
follows:
P7.0INT7
Interrupt 7 input
Port 1
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 1 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 1 pins being
externally pulled low will source current ( I
, in the DC
IL
characteristics) because of the internal pullup resistors.
The port is used for the low-order address byte during
program verification. Port 1 also contains the interrupt,
timer, clock, capture and compare pins that are used by
various options. The output latch corresponding to a
secondary function must be programmed to a one (1) for
that function to operate (except when used for the
compare functions). The secondary functions are
assigned to the port 1 pins as follows:
P1.0INT3
Input to the inverting oscillator amplifier and input to the
internal clock generator circuits.
To drive the device from an external clock source, XTAL2
should be driven, while XTAL1 is left unconnected.
Minimum and maximum high and low times as well as
rise/fall times specified in the AC characteristics must be
observed.
XTAL137OXTAL1
Output of the inverting oscillator amplifier.
C515C
P2.0-P2.738-45I/OPort 2
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 2 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 2 pins being
externally pulled low will source current (I
characteristics) because of the internal pullup resistors.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses strong
internal pullup resistors when issuing 1's. During
accesses to external data memory that use 8-bit
addresses (MOVX @Ri), port 2 issues the contents of
the P2 special function register.
CPUR
46OCPU running condition
This output pin is at low level when the CPU is running
and program fetches or data accesses in the external
data memory area are executed. In idle mode, hardware
and software power down mode, and with an active
RESET signal CPUR is set to high level.
CPUR can be typically used for switching external
memory devices into power saving modes.
, in the DC
IL
*) I = Input
O = Output
Semiconductor Group101997-07-01
Page 11
Table 1
Pin Definitions and Functions (cont’d)
SymbolPin NumberI/O*)Function
P-MQFP-80
PSEN47OThe Program Store Enable
output is a control signal that enables the external
program memory to the bus during external fetch
operations. It is activated every six oscillator periods,
except during external data memory accesses. The
signal remains high during internal program execution.
ALE48OThe Address Latch enable
output is used for latching the address into external
memory during normal operation. It is activated every six
oscillator periods, except during an external data
memory access. ALE can be switched off when the
program is executed internally.
C515C
EA49IExternal Access Enable
When held high, the C515C executes instructions always
from the internal ROM. When held low, the C515C
fetches all instructions from external program memory.
P0.0-P0.752-59I/OPort 0
is an 8-bit open-drain bidirectional I/O port.
Port 0 pins that have 1's written to them float, and in that
state can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data
bus during accesses to external program and data
memory. In this application it uses strong internal pullup
resistors when issuing 1's.
Port 0 also outputs the code bytes during program
verification in the C515C. External pullup resistors are
required during program verification.
P5.0-P5.767-60I/OPort 5
is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 5 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 5 pins being
externally pulled low will source current (I
characteristics) because of the internal pullup resistors.
Port 5 can also be switched into a bidirectional mode, in
which CMOS levels are provided. In this bidirectional
mode, each port 5 pin can be programmed individually as
input or output.
, in the DC
IL
*) I = Input
O = Output
Semiconductor Group111997-07-01
Page 12
Table 1
Pin Definitions and Functions (cont’d)
SymbolPin NumberI/O*)Function
P-MQFP-80
HWPD69IHardware Power Down
A low level on this pin for the duration of one machine
cycle while the oscillator is running resets the C515C.
A low level for a longer period will force the part to power
down mode with the pins floating.
C515C
P4.0-P4.772-74, 76-80
72
73
74
76
77
78
79
80
I/OPort 4
is an 8-bit quasi-bidirectional I/O port with internal pull-up
resistors. Port 4 pins that have 1’s written to them are
pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port 4 pins being
externally pulled low will source current (I
characteristics) because of the internal pull-up resistors.
P4 also contains the external A/D converter control pin,
the SSC pins, the CAN controller input/output lines, and
the external interrupt 8 input. The output latch
corresponding to a secondary functionmust be
programmed to a one (1) for that function to operate.
The alternate functions are assigned to port 4 as follows:
P4.0ADSTExternal A/D converter start pin
P4.1SCLKSSC Master Clock Output /
P4.2SRISSC Receive Input
P4.3STOSSC Transmit Output
P4.4SLS
P4.5INT8External interrupt 8 input
P4.6TXDCTransmitter output of the CAN controller
P4.7RXDCReceiver input of the CAN controller
A low level on this pin allows the software to enter the
power down, idle and slow down mode. In case the low
level is also seen during reset, the watchdog timer
function is off on default.
Use of the software controlled power saving modes is
blocked, when this pin is held on high level. A high level
during reset performs an automatic start of the watchdog
timer immediately after reset. When left unconnected this
pin is pulled high by a weak internal pull-up resistor.
*) I = Input
O = Output
Semiconductor Group121997-07-01
Page 13
Table 1
Pin Definitions and Functions (cont’d)
SymbolPin NumberI/O*)Function
P-MQFP-80
VSSCLK13–Ground (0 V) for on-chip oscillator
This pin is used for ground connection of the on-chip
oscillator circuit.
VCCCLK14–Supply voltage for on-chip oscillator
This pin is used for power supply of the on-chip oscillator
circuit.
C515C
VCCE1
VCCE2
32
68
–Supply voltage for I/O ports
These pins are used for power supply of the I/O ports
during normal, idle, and power-down mode.
VSSE1
VSSE2
35
70
–Ground (0 V) for I/O ports
These pins are used for ground connections of the I/O
ports during normal, idle, and power-down mode.
VCC133–Supply voltage for internal logic
This pins is used for the power supply of the internal logic
circuits during normal, idle, and power down mode.
VSS134–Ground (0 V) for internal logic
This pin is used for the ground connection of the internal
logic circuits during normal, idle, and power down mode.
VCCEXT50–Supply voltage for external access pins
This pin is used for power supply of the I/O ports and
control signals which are used during external accesses
(for Port 0, Port 2, ALE, PSEN
, P3.6/WR, and P3.7/RD).
VSSEXT51–Ground (0 V) for external access pins
This pin is used for the ground connection of the I/O ports
and control signals which are used during external
accesses (for Port 0, Port 2, ALE, PSEN
, P3.6/WR, and
P3.7/RD).
N.C.2, 71–Not connected
These pins should not be connected.
*) I = Input
O = Output
Semiconductor Group131997-07-01
Page 14
C515C
Figure 4
Block Diagram of the C515C
Semiconductor Group141997-07-01
Page 15
C515C
CPU
The C515C is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% threebyte instructions. With a 6 MHz crystal, 58% of the instructions are executed in 1 µs (10 MHz :
600 ns).
Special Function Register PSW (Address D0H) Reset Value : 00H
Bit No.MSBLSB
H
D7
CYAC
H
D6
H
D5
F0
H
D4
RS1RS0OVF1PD0
BitFunction
CYCarry Flag
Used by arithmetic instruction.
ACAuxiliary Carry Flag
Used by instructions which execute BCD operations.
F0General Purpose Flag
RS1
RS0
Register Bank select control bits
These bits are used to select one of the four register banks.
RS1RS0Function
00Bank 0 selected, data address 00H-07
01Bank 1 selected, data address 08H-0F
10Bank 2 selected, data address 10H-17
11Bank 3 selected, data address 18H-1F
H
D3
H
D2
H
D1
H
D0
H
PSW
H
H
H
H
OVOverflow Flag
Used by arithmetic instruction.
F1General Purpose Flag
PParity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.
Semiconductor Group151997-07-01
Page 16
Memory Organization
The C515C CPU manipulates data and operands in the following five address spaces:
– up to 64 Kbyte of internal/external program memory
– up to 64 Kbyte of external data memory
– 256 bytes of internal data memory
– 256 bytes CAN controller registers / data memory
– 2K bytes of internal XRAM data memory
– a 128 byte special function register area
Figure 5 illustrates the memory address spaces of the C515C.
C515C
Figure 5
C515C Memory Map
Semiconductor Group161997-07-01
Page 17
C515C
Control of XRAM/CAN Controller Access
The XRAM in the C515C is a memory area that is logically located at the upper end of the external
memory space, but is integrated on the chip. Because the XRAM and the CAN controller is used in
the same way as external data memory the same instruction types (MOVX) must be used for
accessing the XRAM. Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to the
XRAM and the CAN controller.
Special Function Register SYSCON (Address B1H) Reset Value : X010XX01
Bit No.MSBLSB
76543210
B1
H
BitFunction
XMAP1XRAM/CAN controller visible access control
–PMOD
The function of the shaded bits is not described in this section.
Control bit for RD/WR signals during XRAM/CAN Controller accesses. If
addresses are outside the XRAM/CAN controller address range or if
XRAM is disabled, this bit has no effect.
XMAP1 = 0 : The signals RD and WR are not activated during accesses to
XMAP1 = 1 : Ports 0, 2 and the signals RD and WR are activated during
EALERMAP–
the XRAM/CAN Controller
accesses to XRAM/CAN Controller. In this mode, address
and data information during XRAM/CAN Controller accesses
are visible externally.
–XMAP1
XMAP0
SYSCON
B
XMAP0Global XRAM/CAN controller access enable/disable control
XMAP0 = 0 : The access to XRAM and CAN controller is enabled.
XMAP0 = 1 : The access to XRAM and CAN controller is disabled (default
after reset). All MOVX accesses are performed via the
external bus. Further, this bit is hardware protected.
Bit XMAP0 is hardware protected. If it is reset once (XRAM/CAN controller access enabled) it
cannot be set by software. Only a reset operation will set the XMAP0 bit again.
The XRAM/CAN controller can be accessed by read/write instructions (MOVX A,DPTR, MOVX
@DPTR,A), which use the 16-bit DPTR for indirect addressing. For accessing the XRAM or CAN
controller, the effective address stored in DPTR must be in the range of F700H to FFFFH.
The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX @Ri,A), which
use only an 8-bit address (indirect addressing with registers R0 or R1). Therefore, a special page
register XPAGE which provides the upper address information (A8-A15) during 8-bit XRAM
accesses. The behaviour of Port 0 and P2 during a MOVX access depends on the control bits
XMAP0 and XMAP1 in register SYSCON and on the state of pin EA
operating conditions.
Semiconductor Group171997-07-01
. Table 2 lists the various
Page 18
Semiconductor Group181997-07-01
= 0EA = 1
EA
XMAP1, XMAP0XMAP1, XMAP0
0010X10010X1
MOVX
@DPTR
MOVX
@ Ri
DPTR
<
XRAM/CAN
address
range
DPTR
≥
XRAMCAN
address
range
XPAGE
<
XRAMCAN
addr.page
range
XPAGE
≥
XRAMCAN
addr.page
range
a)P0/P2→Bus
b)RD/WR active
c)ext.memory
is used
a)P0/P2
(RD/WR-Data)
b)RD/WR
inactive
c)XRAM is used
a)P0→Bus
P2→I/O
b)RD/WR active
c)ext.memory
is used
a)P0
(RD/WR-Data)
P2→I/O
b)RD/WR
inactive
c)XRAM is used
→Bus
→Bus
a)P0/P2→Bus
b)RD/WR active
c)ext.memory
is used
a)P0/P2→Bus
(RD/WR-Data)
b)RD/WR active
c)XRAM is used
a)P0→Bus
P2→I/O
b)RD/WR active
c)ext.memory
is used
a)P0→Bus
(RD/WR-Data
only)
P2→I/O
b)RD/WR active
c)XRAM is used
a)P0/P2→Bus
b)RD/WR active
c)ext.memory
is used
a)P0/P2→Bus
b)RD/WR active
c) ext.memory
is used
a)P0→Bus
P2→I/O
b)RD/WR active
c)ext.memory
is used
a)P0→Bus
P2→I/O
b)RD/WR active
c)ext.memory
is used
a)P0/P2→Bus
b)RD/WR active
c)ext.memory
is used
a)P0/P2→I/0
b)RD/WR
inactive
c)XRAM is used
a)P0→Bus
P2→I/O
b)RD/WR active
c)ext.memory
is used
a)P2→I/O
P0/P2→I/O
b)RD/WR
inactive
c)XRAM is used
a)P0/P2→Bus
b)RD/WR active
c)ext.memory
is used
a)P0/P2→Bus
(RD/WR-Data)
b)RD/WR active
c)XRAM is used
a)P0→Bus
P2→I/O
b)RD/WR active
c)ext.memory
is used
a)P0→Bus
(RD/WR-Data)
P2→I/O
b)RD/WR active
c)XRAM is used
a)P0/P2→Bus
b)RD/WR active
c)ext.memory
is used
a)P0/P2→Bus
b)RD/WR active
c) ext.memory
is used
a)P0→Bus
P2→I/O
b)RD/WR active
c)ext.memory
is used
a)P0→Bus
P2→I/O
b)RD/WR active
c)ext.memory
is used
modes compatible to 8051/C501 family
Table 2
Behaviour of P0/P2 and RD
C515C
/WR During MOVX Accesses
Page 19
C515C
Reset and System Clock
The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held low for at least two machine cycles (12 oscillator periods) while the
oscillator is running. A pullup resistor is internally connected to VCC to allow a power-up reset with
an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting
the RESET pin to VSS via a capacitor. Figure 6 shows the possible reset circuitries.
Figure 6
Reset Circuitries
Figure 7 shows the recommended oscillator circiutries for crystal and external clock operation.
Figure 7
Recommended Oscillator Circuitries
Semiconductor Group191997-07-01
Page 20
C515C
Multiple Datapointers
As a functional enhancement to the standard 8051 architecture, the C515C contains eight 16-bit
datapointers instead of only one datapointer. The instruction set uses just one of these datapointers
at a time. The selection of the actual datapointer is done in the special function register DPSEL.
Figure 8 illustrates the datapointer addressing mechanism.
Figure 8
External Data Memory Addressing using Multiple Datapointers
External Data Memory
MCD00779
Semiconductor Group201997-07-01
Page 21
C515C
Enhanced Hooks Emulation Concept
The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.
Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.
The Enhanced Hooks TechnologyTM, which requires embedded logic in the C500 allows the C500
together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.
Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the programm execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.
Semiconductor Group211997-07-01
Page 22
C515C
Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in
the special function register area. The special function register area consists of two portions : the
standard special function register area and the mapped special function register area. Two special
function registers of the C515C (PCON1 and DIR5) are located in the mapped special function
register area. For accessing the mapped special function register area, bit RMAP in special function
register SYSCON must be set. All other special function registers are located in the standard
special function register area which is accessed when RMAP is cleared (“0“). As long as bit RMAP
is set, mapped special function register area can be accessed. This bit is not cleared by hardware
automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must
be cleared/set by software, respectively each.
Special Function Register SYSCON (Address B1H) Reset Value : 1010XX01
Bit No.MSBLSB
76543210
B1
BitFunction
RMAPSpecial function register map bit
The 59 special function registers (SFRs) in the standard and mapped SFR area include pointers
and registers that provide an interface between the CPU and the other on-chip peripherals. The
SFRs of the C515C are listed in table 3 and table 4. In table 3 they are organized in groups which
refer to the functional blocks of the C515C. The CAN-SFRs are also included in table 3. Table 4
illustrates the contents of the SFRs in numeric order of their addresses. Table 5 list the CAN-SFRs
in numeric order of their addresses.
CLKPPMOD
H
RMAP = 0 : The access to the non-mapped (standard) special function
RMAP = 1 : The access to the mapped special function register area is
1RMAP–
register area is enabled (reset value).
enabled.
–XMAP1
XMAP0
SYSCON
B
Semiconductor Group221997-07-01
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C515C
Table 3
Special Function Registers - Functional Blocks
BlockSymbolNameAddressContents after
Reset
CPUACC
B
DPH
DPL
DPSEL
PSW
SP
SYSCON
A/DConverter
ADCON0
ADCON1
ADDATH
ADDATL
Interrupt
System
IEN0
IEN1
2)
2)
IEN2
2)
IP0
IP1
TCON
T2CON
SCON
IRCON
XRAMXPAGE
2)
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data Pointer Select Register
Program Status Word Register
Stack Pointer
2)
System Control Register
2)
A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Register High Byte
A/D Converter Data Register Low Byte
Power Control Register
Serial Channel Buffer Register
Serial Channel Control Register
Serial Channel Reload Register, low byte
Serial Channel Reload Register, high byte
Control Register
Status Register
Interrupt Register
Bit Timing Register Low
Bit Timing Register High
Global Mask Short Register Low
Global Mask Short Register High
Upper Global Mask Long Register Low
Upper Global Mask Long Register High
Lower Global Mask Long Register Low
Lower Global Mask Long Register High
Upper Mask of Last Message Register Low
Upper Mask of Last Message Register High
Lower Mask of Last Message Register Low
Lower Mask of Last Message Register High
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by
a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
5) The notation “n“ in the message object address definition defines the number of the related message object.
Message Control Register Low
Message Control Register High
Upper Arbitration Register Low
Upper Arbitration Register High
Lower Arbitration Register Low
Lower Arbitration Register High
Message Configuration Register
Message Data Byte 0
Message Data Byte 1
Message Data Byte 2
Message Data Byte 3
Message Data Byte 4
Message Data Byte 5
Message Data Byte 6
Message Data Byte 7
1) The notation “n“ in the address definition defines the number of the related message object.
2) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged
by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation
UAR0UU
H
UAR1UU
H
LAR0UU
H
LAR1UUUU.
H
MCFGUUUU.
H
H
H
H
U000
UU00
ID28-21
ID20-18ID17-13
ID12-5
ID4-0000
B
DLCDIRXTD00
B
Semiconductor Group291997-07-01
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Table 5
Contents of the CAN Registers in numeric order of their addresses (cont’d)
1) The notation “n“ in the address definition defines the number of the related message object.
2) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged
by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation
The C515C allows for digital I/O on 49 lines grouped into 6 bidirectional 8-bit ports and one 1-bit
port. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses
to the I/O ports P0 through P7 are performed via their corresponding special function registers P0
to P7. The port structure of port 5 of the C515C is especially designed to operate either as a quasibidirectional port structure, compatible to the standard 8051-Family, or as a genuine bidirectional
port structure. This port operating mode can be selected by software (setting or clearing the bit
PMOD in the SFR SYSCON).
The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, timemultiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents.
Analog Input Ports
Ports 6 is available as input port only and provides two functions. When used as digital inputs, the
corresponding SFR P6 contains the digital value applied to the port 6 lines. When used for analog
inputs the desired analog channel is selected by a three-bit field in SFR ADCON0 or SFR ADCON1.
Of course, it makes no sense to output a value to these input-only ports by writing to the SFR P6.
This will have no effect.
lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications
(VIL/VIH). Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte
instructions.
Nevertheless, it is possible to use port 6 simultaneously for analog and digital input. However, care
must be taken that all bits of P6 that have an undetermined value caused by their analog function
are masked.
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C515C
Port Structure Selection of Port 5
After a reset operation of the C515C, the quasi-bidirectional 8051-compatible port structure is
selected. For selection of the bidirectional (CMOS) port 5 structure the bit PMOD of SFR SYSCON
must be set. Because each port 5 pin can be programmed as an input or an output, additionally,
after the selection of the bidirectional mode the direction register DIR5 of port 5 must be written.
This direction register is mapped to the port 5 register. This means, the port register address is
equal to its direction register address. Figure 10 illustrates the port- and direction register
configuration.
Figure 10
Port Register, Direction Register
Semiconductor Group321997-07-01
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Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in table 6 :
Table 6
Timer/Counter 0 and 1 Operating Modes
ModeDescriptionTMODTimer/Counter Input Clock
M1M0internalexternal (max)
C515C
08-bit timer/counter with a
00
f
/6 x 32f
OSC
/12 x 32
OSC
divide-by-32 prescaler
116-bit timer/counter01
28-bit timer/counter with
10
8-bit autoreload
3Timer/counter 0 used as one
11
/6f
OSC
OSC
/12
f
8-bit timer/counter and one
8-bit timer / Timer 1 stops
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is f
OSC
/6.
In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is f
/12. External inputs INT0 and INT1 (P3.2, P3.3) can be
OSC
programmed to function as a gate to facilitate pulse width measurements. Figure 11 illustrates the
input clock logic
P3.4/T0
P3.5/T1
Gate
(TMOD)
P3.2/INT0
P3.3/INT1
OSC
=1
÷
6
C/T = 0
C/T = 1
Control
TR0
TR1
_
<
1
&
f
/6
OSC
Timer 0/1
Input Clock
MCS03117
Figure 11
Timer/Counter 0 and 1 Input Clock Logic
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C515C
Timer/Counter 2 with Compare/Capture/Reload
The timer 2 of the C515C provides additional compare/capture/reload features. which allow the
selection of the following operating modes:
– Compare: up to 4 PWM signals with 16-bit/600 ns resolution
– Capture: up to 4 high speed capture inputs with 600 ns resolution
– Reload: modulation of timer 2 cycle time
The block diagram in figure 12 shows the general configuration of timer 2 with the additional
compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as
multifunctional port functions at port 1.
Figure 12
Timer 2 Block Diagram
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C515C
Timer 2 Operating Modes
The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A
roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag TF2 in SFR
IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer
2 operation.
Timer Mode : In timer function, the count rate is derived from the oscillator frequency. A prescaler
offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency.
Gated Timer Mode : In gated timer function, the external input pin T2 (P1.7) functions as a gate to
the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the
counting procedure. This facilitates pulse width measurements. The external gate signal is sampled
once every machine cycle.
Event Counter Mode : In the event counter function. the timer 2 is incremented in response to a 1to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is
sampled every machine cycle. Since it takes two machine cycles (12 oscillator periods) to recognize
a 1-to-0 transition, the maximum count rate is 1/6 of the oscillator frequency. There are no
restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled
at least once before it changes, it must be held for at least one full machine cycle.
Reload of Timer 2 : Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also causes the timer
2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.
In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the corresponding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been
set.
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C515C
Timer 2 Compare Modes
The compare function of a timer/register combination operates as follows : the 16-bit value stored
in a compare or compare/capture register is compared with the contents of the timer register; if the
count value in the timer register matches the stored value, an appropriate output signal is generated
at a corresponding port pin and an interrupt can be generated.
Compare Mode 0
In compare mode 0, upon matching the timer and compare register contents, the output signal
changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode
0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port
will have no effect. Figure 13 shows a functional diagram of a port circuit when used in compare
mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The
input line from the internal bus and the write-to-latch line of the port latch are disconnected when
compare mode 0 is enabled.
Compare Register
Circuit
Compare Reg.
16 Bit
Comparator
Bit16
Timer Register
Timer Circuit
Compare
Match
Timer
Overflow
Figure 13
Port Latch in Compare Mode 0
Port Circuit
Internal
Bus
Write to
Latch
S
D
Latch
CLK
R
Read Latch
Q
Port
Q
Read Pin
V
CC
Port
Pin
MCS02661
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C515C
Compare Mode 1
If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the
new value will not appear at the output pin until the next compare match occurs. Thus, it can be
choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the
actual pin-level) or should keep its old value at the time when the timer value matches the stored
compare value.
In compare mode 1 (see figure 14) the port circuit consists of two separate latches. One latch
(which acts as a "shadow latch") can be written under software control, but its value will only be
transferred to the port latch (and thus to the port pin) when a compare match occurs.
Port Circuit
Compare Register
Circuit
Compare Reg.
16 Bit
Comparator
16 Bit
Timer Register
Timer Circuit
Compare
Match
Internal
Bus
Write to
Latch
Figure 14
Compare Function in Compare Mode 1
D
Shadow
Latch
CLK
Read Latch
Q
D
Port
Latch
Read Pin
V
CC
Q
QCLK
Port
Pin
MCS02662
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C515C
Serial Interface (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 7.
Table 7
USART Operating Modes
Mode
SCONDescription
SM0SM1
000Shift register mode, fixed baud rate
Serial data enters and exits through R×D; T×D outputs the shift
clock; 8-bit are transmitted/received (LSB first)
1018-bit UART, variable baud rate
10 bits are transmitted (through T×D) or received (at R×D)
2109-bit UART, fixed baud rate
11 bits are transmitted (through T×D) or received (at R×D)
3119-bit UART, variable baud rate
Like mode 2
For clarification some terms regarding the difference between "baud rate clock" and "baud rate"
should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is
16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have
to provide a "baud rate clock" (output signal in figure 15 to the serial interface which - there divided
by 16 - results in the actual "baud rate". Further, the abrevation f
refers to the oscillator frequency
OSC
(crystal or external clock operation).
The variable baud rates for modes 1 and 3 of the serial interface can be derived either from timer 1
or from a decdicated baud rate generator (see figure 15).
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C515C
Figure 15
Block Diagram of Baud Rate Generation for the Serial Interface
Table 8 below lists the values/formulas for the baud rate calculation of the serial interface with itsdependencies of the control bits BD and SMOD.
Table 8
Serial Interface - Baud Rate Dependencies
Serial Interface
Operating Modes
Mode 0 (Shift Register)––
Mode 1 (8-bit UART)
Mode 3 (9-bit UART)
Active Control BitsBaud Rate Calculation
BDSMOD
f
/ 6
OSC
0XControlled by timer 1 overflow :
SMOD
(2
× timer 1 overflow rate) / 32
1XControlled by baud rate generator
SMOD
(2
× f
OSC
) /
(32 × baud rate generator overflow rate)
Mode 2 (9-bit UART)–0
1
f
/ 32
OSC
f
/ 16
OSC
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C515C
SSC Interface
The C515C microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is
compatible to the popular SPI serial bus interface. Figure 16 shows the block diagram of the SSC.
The central element of the SSC is an 8-bit shift register. The input and the output of this shift register
are each connected via a control logic to the pin P4.2 / SRI (SSC Receiver In) and P4.3 / STO (SSC
Transmitter Out). This shift register can be written to (SFR STB) and can be read through the
Receive Buffer Register SRB.
Figure 16
SSC Block Diagram
The SSC has implemented a clock control circuit, which can generate the clock via a baud rate
generator in the master mode, or receive the transfer clock in the slave mode. The clock signal is
fully programmable for clock polarity and phase. The pin used for the clock signal is P4.1/ SCLK.
When operating in slave mode, a slave select input is provided which enables the SSC interface
and also will control the transmitter output. The pin used for this is P4.4 / SLS.
The SSC control block is responsible for controlling the different modes and operation of the SSC,
checking the status, and generating the respective status and interrupt signals.
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C515C
CAN Controller
The on-chip CAN controller is the functional heart which provides all resources that are required to
run the standard CAN protocol (11-bit identifiers) as well as the extended CAN protocol (29-bit
identifiers). It provides a sophisticated object layer to relieve the CPU of as much overhead as
possible when controlling many different message objects (up to 15). This includes bus arbitration,
resending of garbled messages, error handling, interrupt generation, etc. In order to implement the
physical layer, external components have to be connected to the C515C.
The internal bus interface connects the on-chip CAN controller to the internal bus of the
microcontroller. The registers and data locations of the CAN interface are mapped to a specific 256
byte wide address range of the external data memory area (F700H to F7FFH) and can be accessed
using MOVX instructions. Figure 17 shows a block diagram of the on-chip CAN controller.
Figure 17
CAN Controller Block Diagram
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C515C
The TX/RXShift Register holds the destuffed bit stream from the bus line to allow the parallel
access to the whole data or remote frame for the acceptance match test and the parallel transfer of
the frame to and from the Intelligent Memory.
The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream between
the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also controls the EML and
the parallel data stream between the TX/RX Shift Register and the Intelligent Memory such that the
processes of reception, arbitration, transmission, and error signalling are performed according to
the CAN protocol. Note that the automatic retransmission of messages which have been corrupted
by noise or other external error conditions on the bus line is handled by the BSP.
The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy Check code to
be transmitted after the data bytes and checks the CRC code of incoming messages. This is done
by dividing the data stream by the code generator polynomial.
The Error Management Logic (EML) is responsible for the fault confinement of the CAN device. Its
counters, the Receive Error Counter and the Transmit Error Counter, are incremented and
decremented by commands from the Bit Stream Processor. According to the values of the error
counters, the CAN controller is set into the states error
active
, error
passive
and busoff.
The Bit Timing Logic (BTL) monitors the busline input RXDC and handles the busline related bit
timing according to the CAN protocol. The BTL synchronizes on a
transition at
transition, if the CAN controller itself does not transmit a
also provides programmable time segments to compensate for the propagation delay time and for
phase shifts and to define the position of the Sample Point in the bit time. The programming of the
BTL depends on the baudrate and on external physical delay times.
The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message objects of
maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of
control and status bits. After the initial configuration, the Intelligent Memory can handle the
reception and transmission of data without further microcontroller actions.
Start of Frame
(hard synchronization) and on any further
dominant
recessive
recessive
bit (resynchronization). The BTL
to
dominant
to
dominant
busline
busline
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C515C
10-Bit A/D Converter
The C515C includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog
input channels. It operates with a successive approximation technique and uses self calibration
mechanisms for reduction and compensation of offset and linearity errors. The A/D converter
provides the following features:
– 8 multiplexed input channels (port 6), which can also be used as digital inputs
– 10-bit resolution
– Single or continuous conversion mode
– Internal or external start-of-conversion trigger capability
– Interrupt request generation after each conversion
– Using successive approximation conversion technique via a capacitor array
– Built-in hidden calibration of offset and linearity errors
The main functional blocks of the A/D converter are shown in figure 19.
The A/D converter uses basically two clock signals for operation : the input clock fIN (=1/tIN) and the
conversion clock f
f
which is applied at the XTAL pins. The input clock fIN is equal to f
OSC
is limited to a maximum frequency of 2 MHz and therefore must be adapted to f
programming the conversion clock prescaler. The table in figure 18 shows the prescaler ratios and
the resulting A/D conversion times which must be selected for typical system clock rates.
ADC
(=1/t
). These clock signals are derived from the C515C system clock
ADC
. The conversion clock
OSC
OSC
by
MCU System Clock
Rate (f
OSC
)
ADCLConversion Clock
f
[MHz]
ADC
2 MHz0.5
4 MHz01
6 MHz01.5
8 MHz02
10 MHz11.25
Figure 18
A/D Converter Clock Selection
Semiconductor Group431997-07-01
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C515C
Figure 19
A/D Converter Block Diagram
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C515C
Interrupt System
The C515C provides 17 interrupt sources with four priority levels. Seven interrupts can be
generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter, SSC
interface, CAN controller), and ten interrupts may be triggered externally (P1.5/T2EX, P3.2/INT0,
P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4, P1.2/INT5, P1.3/INT6, P7.0/INT7, P4.5/INT8). The
wake-up from power-down mode interrupt has a special functionality which allows to exit from the
software power-down mode by a short low pulse at pin P3.2/INT0.
In the C515C the 17 interrupt sources are combined to six groups of two or three interrupt sources.
Each interrupt group can be programmed to one of the four interrupt priority levels. Figure 20 to 22
give a general overview of the interrupt sources and illustrate the interrupt request and control flags.
The C515C offers two on-chip peripherals which monitor the program flow and ensure an automatic
"fail-safe" reaction for cases where the controller’s hardware fails or the software hangs up:
– A programmable watchdog timer (WDT) with variable time-out period from 512 microseconds
up to approx. 1.1 seconds at 6 MHz.
– An oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.
Programmable Watchdog Timer
The watchdog timer in the C515C is a 15-bit timer, which is incremented by a count rate of f
to f
/192. For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog
OSC
timer can be written. Figure 23 shows the block diagram of the watchdog timer unit.
OSC
/6 up
Figure 23
Block Diagram of the Programmable Watchdog Timer
The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD,
but it cannot be stopped during active mode of the C515C. If the software fails to refresh the running
watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the
watchdog timer the content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog
timer. The refresh sequence consists of two consequtive instructions which set the bits WDT and
SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined
by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the
idle mode and power down mode of the processor.
Semiconductor Group501997-07-01
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Oscillator Watchdog
The oscillator watchdog unit serves for four functions:
– Monitoring of the on-chip oscillator's function
The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency
of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC
oscillator and the device is brought into reset; if the failure condition disappears (i.e. the onchip oscillator has a higher frequency than the RC oscillator), the part executes a final reset
phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset
is released and the part starts program execution again.
– Fast internal reset after power-on
The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator
has started. The oscillator watchdog unit also works identically to the monitoring function.
– Restart from the hardware power down mode.
If the hardware power down mode is terminated the oscillator watchdog has to control the
correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog
function is only part of the complete hardware power down sequence; however, the watchdog
works identically to the monitoring function.
– Control of external wake-up from software power-down mode
When the software power-down mode is left by a low level at the P3.2/INT0 pin, the oscillator
watchdog unit assures that the microcontroller resumes operation (execution of the powerdown wake-up interrupt) with the nominal clock rate. In the power-down mode the RC
oscillator and the on-chip oscillator are stopped. Both oscillators are started again when
power-down mode is released. When the on-chip oscillator has a higher frequency than the
RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to
allow the on-chip oscillator to stabilize.
C515C
Semiconductor Group511997-07-01
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C515C
Figure 24
Block Diagram of the Oscillator Watchdog
Power Saving Modes
The C515C provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock
rate in normal operating mode and it can be also used for further power reduction in idle mode.
– Idle mode
The CPU is gated off from the oscillator. All peripherals are still provided with the clock and
are able to work. Idle mode is entered by software and can be left by an interrupt or reset.
– Power down mode
The operation of the C515C is completely stopped and the oscillator is turned off. This mode
is used to save the contents of the internal RAM with a very low standby current.
Software power down mode : Software power down mode is entered by software and can
be left by reset or by a short low pulse at pin P3.2/INT0.
Hardware power down mode : Hardware power down mode is entered when the pin HWPD
is put to low level.
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C515C
– Slow-down mode
The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 32. This slows down all parts of the controller, the CPU and all
peripherals, to 1/32-th of their normal operating frequency. Slowing down the frequency
significantly reduces power consumption. The slow down mode can be combined with the idle
mode.
Table 10 gives a general overview of the entry and exit conditions of the power saving modes.
Table 10
Power Saving Modes Overview
ModeEntering
Leaving byRemarks
(2-Instruction
Example
Idle modeORL PCON, #01H
ORL PCON, #20H
Ocurrence of an
interrupt from a
peripheral unit
Hardware Reset
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Software
Power-Down Mode
Hardware
Power-Down Mode
ORL PCON, #02H
ORL PCON, #40H
Hardware ResetOscillator is stopped;
Short low pulse at
pin P3.2/INT0
contents of on-chip RAM and
SFR’s are maintained;
HWPD = low HWPD = high C515C is put into its reset state
and the oscillator is stopped;
ports become floating outputs
Slow Down ModeORL PCON,#10HANL PCON,#0EFH
or
Oscillator frequency is reduced
to 1/32 of its nominal frequency
Hardware Reset
V
In the power down mode of operation,
can be reduced to minimize power consumption. It must
CC
be ensured, however, that VCC is not reduced before the power down mode is invoked, and that V
is restored to its normal operating level, before the power down mode is terminated.
CC
If e.g. the idle mode is left through an interrupt, the microcontroller state (CPU, ports, peripherals)
remains preserved. If a power saving mode is left by a hardware reset, the microcontroller state is
disturbed and replaced by the reset state of the C515C.
Semiconductor Group531997-07-01
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C515C
Absolute Maximum Ratings
Ambient temperature under bias (TA) ......................................................... – 40 to 110 °C
Storage temperature (T
Voltage on VCC pins with respect to ground (VSS) ....................................... – 0.5 V to 6.5 V
Voltage on any pin with respect to ground (VSS)......................................... – 0.5 V to VCC +0.5 V
Input current on any pin during overload condition..................................... – 10 mA to 10 mA
Absolute sum of all input currents during overload condition ..................... I 100 mA I
Power dissipation........................................................................................ TBD
Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (
Voltage on
V
CC
absolute maximum ratings.
) .......................................................................... – 65 °C to 150 °C
stg
V
>
V
CC
or
pins with respect to ground (
IN
V
) must not exceed the values defined by the
SS
V
<
V
SS
) the
IN
Semiconductor Group541997-07-01
Page 55
C515C
DC Characteristics
V
= 5 V + 10%, – 15%; VSS = 0 VTA = 0 to 70 °Cfor the SAB-C515C-8R
CC
T
= – 40 to 85 °Cfor the SAF-C515C-8R
A
T
= – 40 to 110 °Cfor the SAH-C515C-8R
A
ParameterSymbolLimit ValuesUnitTest Condition
min.max.
Input low voltages
all except EA, RESET, HWPD
EA pin
RESET and HWPD pins
Port 5 in CMOS mode
Input high voltages
all except XTAL2, RESET
, and
HWPD)
XTAL2 pin
RESET and HWPD pins
Port 5 in CMOS mode
Power Supply Current
ParameterSymbolLimit ValuesUnit Test Condition
Active mode6 MHz
10 MHz
Idle mode6 MHz
10 MHz
Active mode with
slow-down enabled
Idle mode with
slow-down enabled
6 MHz
10 MHz
6 MHz
10 MHz
Power-down modeI
10)
typ.
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
PD
12.0
18.9
6.9
10.5
TBD
TBD
TBD
TBD
TBD50µAVCC = 2…5.5 V
max.
16.1
25.5
9.8
15
TBD
TBD
TBD
TBD
11)
mA
mA
mA
mA
mA
mA
mA
mA
4)
5)
6)
7)
3)
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.
V
2) Capacitive loading on ports 0 and 2 may cause the
V
0.9
specification when the address lines are stabilizing.
CC
on ALE and PSEN to momentarily fall below the
OH
3) IPD (power-down mode) is measured under following conditions:
6) ICC (active mode with slow-down mode) is measured : TBD
7) ICC (idle mode with slow-down mode) is measured : TBD
8) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin
V
exceeds the specified range (i.e.
> VCC + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VCC and VSS must
OV
remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.
9) Not 100% tested, guaranteed by design characterization
I
10)The typical
values are periodically measured at T
CC
11)The maximum ICC values are measured under worst case conditions (T
= +25 ˚C and V
A
= 5 V but not 100% tested.
CC
= 0 ˚C or -40 ˚C and V
A
= 5.5 V)
CC
Semiconductor Group561997-07-01
Page 57
C515C
MCD03313
25
mA
Ι
CC
20
Ι
CC max
Ι
CC typ
Active Mode
Active Mode
15
10
5
0
02457
1368MHz10
Figure 25
ICC Diagram
Power Supply Current Calculation Formulas
ParameterSymbolFormula
Idle Mode
Idle Mode
f
OSC
Active mode
Idle mode
Active mode with
slow-down enabled
Idle mode with
slow-down enabled
Note : f
is the oscillator frequency in MHz. ICC values are given in mA.
osc
I
CC typ
I
CC max
I
CC typ
I
CC max
I
CC typ
I
CC max
I
CC typ
I
CC max
1.72 * f
2.33 * f
0.9 * f
1.3 * f
TBD
TBD
TBD
TBD
OSC
OSC
OSC
OSC
+ 1.72
+ 2.15
+ 1.5
+ 2.0
Semiconductor Group571997-07-01
Page 58
A/D Converter Characteristics
V
= 5 V + 10%, – 15%; VSS = 0 VTA = 0 to 70 °Cfor the SAB-C515C-8R
CC
T
= – 40 to 85 °Cfor the SAF-C515C-8R
A
T
= – 40 to 110 °Cfor the SAH-C515C-8R
A
C515C
4 V ≤V
≤VCC+0.1 V ; VSS-0.1 V ≤V
AREF
≤VSS+0.2 V
AGND
ParameterSymbolLimit ValuesUnitTest Condition
min.max.
Analog input voltage
V
Sample timet
Conversion cycle timet
Total unadjusted errorT
Internal resistance of
R
reference voltage source
Internal resistance of
R
analog source
ADC input capacitanceC
Notes see next page.
AIN
S
ADCC
UE
AREF
ASRC
AIN
V
AGND
–16 x t
–96 x t
V
AREF
8 x t
48 x t
V
nsPrescaler ÷ 8
IN
IN
nsPrescaler ÷ 8
IN
IN
–± 2LSB
–t
ADC
/ 250
kΩ
- 0.25
–tS / 500
kΩ
- 0.25
–50pF
1)
Prescaler ÷ 4
Prescaler ÷ 4
4)
t
in [ns]
ADC
t
in [ns]
S
6)
5) 6)
2) 6)
Clock calculation table :
2)
3)
Clock Prescaler
ADCLt
ADC
Ratio
÷ 818 x t
÷ 404 x t
Further timing conditions : t
min = 500 ns
ADC
tIN = 1 / f
t
16 x tIN 96 x tIN
IN
8 x tIN 48 x tIN
IN
OSC
t
S
= t
CLP
ADCC
Semiconductor Group581997-07-01
Page 59
Notes:
1) V
2) During the sample time the input capacitance C
may exeed V
AIN
AGND
these cases will be X000
or V
or X3FFH, respectively.
H
up to the absolute maximum ratings. However, the conversion result in
AREF
can be charged/discharged by the external source. The
AIN
internal resistance of the analog source must allow the capacitance to reach their final voltage level within t
After the end of the sample time t
, changes of the analog input voltage have no effect on the conversion
S
result.
C515C
S
.
3) This parameter includes the sample time t
calibration. Values for the conversion clock t
, the time for determining the digital result and the time for the
S
depend on programming and can be taken from the table on
ADC
the previous page.
4) T
is tested at V
UE
AREF
= 5.0 V, V
= 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all
AGND
other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.
5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.
6) Not 100% tested, but guaranteed by design characterization.
Semiconductor Group591997-07-01
Page 60
C515C
AC Characteristics
V
= 5 V + 10%, – 15%; VSS = 0 VTA = 0 to 70 °Cfor the SAB-C515C-8R
CC
T
= – 40 to 85 °Cfor the SAF-C515C-8R
A
T
= – 40 to 110 °Cfor the SAH-C515C-8R
A
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics
ParameterSymbolLimit ValuesUnit
ALE pulse width
Address setup to ALE
Address hold after ALE
ALE to valid instruction in
ALE to PSEN
PSEN
PSEN
pulse widtht
to valid instruction int
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instruction in
Address float to PSEN
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
PLPH
PLIV
t
PXIX
t
PXIZ
t
PXAV
t
AVIV
t
AZPL
10-MHz clock
Duty Cycle
0.4 to 0.6
Variable Clock
1/CLP = 2 MHz to
10 MHz
min.max.min.max.
60–CLP - 40–ns
15–TCL
15–TCL
-25 –ns
Hmin
-25 –ns
Hmin
–113–2 CLP - 87ns
20–TCL
115–CLP+
TCL
–75–CLP+
-20–ns
Lmin
–ns
-30
Hmin
TCL
Hmin
ns
- 65
0–0–ns
*)
–30–TCL
*)
35–TCL
- 5–ns
Lmin
–180–2 CLP +
TCL
Lmin
Hmin
-10ns
ns
-60
00–ns
*)
Interfacing the C515C to devices with float times up to 35 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.
Semiconductor Group601997-07-01
Page 61
C515C
External Data Memory Characteristics
ParameterSymbolLimit ValuesUnit
RD
pulse width
WR
pulse width
Address hold after ALE
to valid data in
RD
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
Note: The 10 MHz values in the tables are given as an example for a typical duty cycle variation of
the oscillator clock from 0.4 to 0.6.
Semiconductor Group621997-07-01
Page 63
ALE
t
C515C
LHLL
PSEN
Port 0
Port 2
Figure 26
Program Memory Read Cycle
t
AVLLPLPH
t
t
LLPL
t
LLIV
t
PLIV
t
AZPL
t
LLAX
t
t
PXAV
t
PXIZ
PXIX
A0 - A7Instr.INA0 - A7
t
AVIV
A8 - A15A8 - A15
t
WHLH
MCT00096
ALE
PSEN
RD
Port 0
Port 2
Figure 27
Data Memory Read Cycle
t
LLDV
t
LLWL
t
AVLL
t
LLAX2
A0 - A7 from
Ri or DPLfrom PCL
t
AVWL
t
AVDV
t
RLDV
t
RLAZ
t
RLRH
Data IN
t
RHDZ
t
RHDX
A0 - A7Instr.
A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH
IN
MCT00097
Semiconductor Group631997-07-01
Page 64
ALE
PSEN
t
WHLH
C515C
WR
t
AVLL
Port 0
A0 - A7 from
Ri or DPLfrom PCL
t
AVWL
Port 2
Figure 28
Data Memory Write Cycle
t
t
LLAX2
LLWL
t
QVWX
t
WLWH
t
QVWH
Data OUT
t
WHQX
A0 - A7
A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH
Instr.IN
MCT00098
Figure 29
External Clock Drive at XTAL2
Semiconductor Group641997-07-01
Page 65
SCLK
STO
SRI
t
SCLK
t
SCL
tt
D
t
SCH
HD
~
~~
~
MSBLSB
~
~
t
StHI
~
~
MSBLSB
~
~~
t
DTC
C515C
TC
~
MCT02417
Notes : Shown is the data/clock relationship for CPOL=CPHA=1. The timing diagram is valid
for the other cases accordingly.
In the case of slave mode and CPHA=0, the output delay for the MSB applies to the
falling edge of SLS (if transmitter is enabled).
In the case of master mode and CPHA=0, the MSB becomes valid after the data has
been written into the shift register, i.e. at least one half SCLK clock cycle before the
first clock transition.
Figure 30
SSC Timing
Semiconductor Group651997-07-01
Page 66
C515C
ROM Verification Mode 1
ParameterSymbolLimit ValuesUnit
min.max.
Address to valid data
Figure 31
ROM Verification Mode 1
t
AVQV
–5 CLPns
Semiconductor Group661997-07-01
Page 67
C515C
ROM Verification Mode 2
ParameterSymbolLimit ValuesUnit
min.typmax.
ALE pulse width
ALE period
Data valid after ALE
Data stable after ALE
P3.5 setup to ALE low
Oscillator frequency
ALE
Port 0
t
AWD
t
AS
t
DVA
t
AWD
t
ACY
t
DVA
t
DSA
t
AS
1/ CLP
t
DSA
–CLP–ns
–6 CLP–ns
––2 CLPns
4 CLP––ns
–t
CL
–ns
4–6MHz
t
ACY
Data Valid
P3.5
Figure 32
ROM Verification Mode 2
MCT02613
Semiconductor Group671997-07-01
Page 68
V
-0.5 V
CC
V
+0.90.2
CC
Test Points
V
0.2-0.1
CC
0.45 V
MCT00039
AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’.
Timing measurements are made at V
for a logic ’1’ and V
IHmin
for a logic ’0’.
ILmax
Figure 33
AC Testing: Input, Output Waveforms
C515C
-0.1 V
V
OH
V
+0.1 V
OL
MCT00038
V
Load
V
V
Load
Load
+0.1 V
Timing Reference
Points
-0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.
I
OL/IOH
≥ ± 20 mA
Figure 34
AC Testing : Float Waveforms
Figure 35
Recommended Oscillator Circuits for Crystal Oscillator
Semiconductor Group681997-07-01
Page 69
P-MQFP-80-1 (SMD)
(Plastic Metric Quad Flat Package)
C515C
Figure 36
Package Outlines
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”
SMD = Surface Mounted Device
GPM05249
Dimensions in mm
Semiconductor Group691997-07-01
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