Datasheet SAB-C515C-8RM, SAB-C515C-LM, SAF-C515C-8RM, SAF-C515C-LM Datasheet (Siemens)

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Microcomputer Components
8-Bit CMOS Microcontroller
C515C
Data Sheet 07.97
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C515C Data Sheet Revision History :
1997-07-01 Previous Releases : 09.96 Page Subjects (changes since last revision) 4
19 52, 53 56, 57 62
SSC transfer rate at 10 MHz = 2.5 MHz Figure reference corrected Power saving modes : description of hardware power down mode added Icc specification has been extended
for Master Mode corrected
t
SCLK
Edition 1997-07-01 Published by Siemens AG,
Bereich Halbleiter, Marketing­Kommunikation, Balanstraße 73, 81541 München
Siemens AG 1997.
©
All Rights Reserved.
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The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
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your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer.
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1
of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems
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with the express
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8-Bit CMOS Microcontroller
Advance Information
Full upward compatibility with SAB 80C515A
64k byte on-chip ROM (external program execution is possible)
256 byte on-chip RAM
2K byte of on-chip XRAM
Up to 64K byte external data memory
Superset of the 8051 architecture with 8 datapointers
Up to 10 MHz external operating frequency (1
On-chip emulation support logic (Enhanced Hooks Technology
Current optimized oscillator circuit and EMI optimized design
Eight ports : 48+1 digital I/O lines, 8 analog inputs – Quasi-bidirectional port structure (8051 compatible) – Port 5 selectable for bidirectional port structure (CMOS voltage levels)
Full-CAN controller on-chip – 256 register/data bytes are located in external data memory area – max.1 MBaud at 8-10 MHz operating frequency
Three 16-bit timer/counters – Timer 2 can be used for compare/capture functions
µ
s instruction cycle time at 6 MHz external clock)
TM
)
C515C
(further features are on next page)
Figure 1 C515C Functional Units
Enhanced Hooks Technology
Semiconductor Group 3 1997-07-01
TM
is a trademark of Siemens AG
.
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Features (continued) :
10-bit A/D converter with multiplexed inputs and built-in self calibration
Full duplex serial interface with programmable baudrate generator (USART)
SSC synchronous serial interface (SPI compatible) – Master and slave capable – Programmable clock polarity / clock-edge to data phase relation – LSB/MSB first selectable – 2.5 MHz transfer rate at 10 MHz operating frequency
Seventeen interrupt vectors, at four priority levels selectable
Extended watchdog facilities – 15-bit programmable watchdog timer – Oscillator watchdog
Power saving modes – Slow-down mode – Idle mode (can be combined with slow-down mode) – Software power-down mode with wake-up capability through INT0 – Hardware power-down mode
CPU running condition output pin
ALE can be switched off
Multiple separate VCC/VSS pin pairs
P-MQFP-80-1 package
Temperature Ranges : SAB-C515C-8R
SAF-C515C-8R SAH-C515C-8R
T
= 0 to 70 ° C
A
T
= -40 to 85 ° C
A
T
= -40 to 110 ° C
A
C515C
pin
The C515C is an enhanced, upgraded version of the SAB 80C515A 8-bit microcontroller which additionally provides a full CAN interface, a SPI compatible synchronous serial interface, extended power save provisions, additional on-chip RAM, 64K of on-chip program memory, two new external interrupts and RFI related improvements. With a maximum external clock rate of 10 MHz it achieves
s at 6 MHz). The C515C is mounted in a P-MQFP-80 package.
a 600 ns instruction cycle time (1
Ordering Information Type Ordering Code Package Description
SAB-C515C-LM Q67121-C1066 P-MQFP-80-1 for external memory (10 MHz) SAF-C515C-LM Q67121-C1058 P-MQFP-80-1 for external memory (10 MHz)
SAB-C515C-8RM Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (10 MHz) SAF-C515C-8RM Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (10 MHz)
Note: Versions for extended temperature ranges – 40 ° C to 110 ° C (SAH-C515C-LM and SAH-
C515C-8RM) are available on request. The ordering number of ROM types (DXXXX extensions) is defined after program release (verification) of the customer.
µ
(8-Bit CMOS microcontroller)
ext. temp. – 40 ° C to 85 ° C
ext. temp. – 40 ° C to 85 ° C
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C515C
Figure 2 Logic Symbol
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C515C
Figure 3 C515C Pin Configuration (P-MQFP-80-1, Top View)
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Table 1 Pin Definitions and Functions
Symbol Pin Number I/O*) Function
P-MQFP-80
C515C
RESET
VAREF 3 – VAGND 4 – P6.0-P6.7 12-5 I
*) I = Input
O = Output
1I
RESET
A low level on this pin for the duration of two machine cycles while the oscillator is running resets the C515C. A small internal pullup resistor permits power-on reset using only a capacitor connected to VSS.
Reference voltage for the A/D converter Reference ground for the A/D converter Port 6
is an 8-bit unidirectional input port to the A/D converter. Port pins can be used for digital input, if voltage levels simultaneously meet the specifications high/low input voltages and for the eight multiplexed analog inputs.
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Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin Number I/O*) Function
P-MQFP-80
C515C
P3.0-P3.7 15-22
15
16
17
18
19 20 21
22
I/O
Port 3
is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current ( I
, in the DC
IL
characteristics) because of the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 RXD Receiver data input (asynch.) or
data input/output (synch.) of serial interface
P3.1 TXD Transmitter data output (asynch.) or
clock output (synch.) of serial interface
P3.2 INT0
External interrupt 0 input / timer 0 gate control input
P3.3 INT1 External interrupt 1 input / timer 1
gate control input P3.4 T0 Timer 0 counter input P3.5 T1 Timer 1 counter input P3.6 WR
WR control output; latches the data
byte from port 0 into the external
data memory P3.7 RD RD control output; enables the
external data memory
*) I = Input
O = Output
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Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin Number I/O*) Function
P-MQFP-80
C515C
P7.0 / INT7
23 I/O
P1.0 - P1.7 31-24
31
30
29
28
27 26
25 24
I/O
Port 7
is an 1-bit quasi-bidirectional I/O port with internal pull-up resistor. When a 1 is written to P7.0 it is pulled high by an internal pull-up resistor, and in that state can be used as input. As input, P7.0 being externally pulled low will source current ( I
, in the DC characteristics) because of
IL
the internal pull-up resistor. If P7.0 is used as interrupt input, its output latch must be programmed to a one (1). The secondary function is assigned to the port 7 pin as follows: P7.0 INT7
Interrupt 7 input
Port 1
is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current ( I
, in the DC
IL
characteristics) because of the internal pullup resistors. The port is used for the low-order address byte during program verification. Port 1 also contains the interrupt, timer, clock, capture and compare pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows: P1.0 INT3
CC0 Interrupt 3 input / compare 0 output /
capture 0 input P1.1 INT4 CC1 Interrupt 4 input / compare 1 output /
capture 1 input P1.2 INT5 CC2 Interrupt 5 input / compare 2 output /
capture 2 input P1.3 INT6 CC3 Interrupt 6 input / compare 3 output /
capture 3 input P1.4 INT2 Interrupt 2 input P1.5 T2EX Timer 2 external reload / trigger
input P1.6 CLKOUT System clock output P1.7 T2 Counter 2 input
*) I = Input
O = Output
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Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin Number I/O*) Function
P-MQFP-80
XTAL2 36 I XTAL2
Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL2 should be driven, while XTAL1 is left unconnected. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed.
XTAL1 37 O XTAL1
Output of the inverting oscillator amplifier.
C515C
P2.0-P2.7 38-45 I/O Port 2
is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current (I characteristics) because of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register.
CPUR
46 O CPU running condition
This output pin is at low level when the CPU is running and program fetches or data accesses in the external data memory area are executed. In idle mode, hardware and software power down mode, and with an active RESET signal CPUR is set to high level. CPUR can be typically used for switching external memory devices into power saving modes.
, in the DC
IL
*) I = Input
O = Output
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Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin Number I/O*) Function
P-MQFP-80
PSEN 47 O The Program Store Enable
output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods, except during external data memory accesses. The signal remains high during internal program execution.
ALE 48 O The Address Latch enable
output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods, except during an external data memory access. ALE can be switched off when the program is executed internally.
C515C
EA 49 I External Access Enable
When held high, the C515C executes instructions always from the internal ROM. When held low, the C515C fetches all instructions from external program memory.
P0.0-P0.7 52-59 I/O Port 0
is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's. Port 0 also outputs the code bytes during program verification in the C515C. External pullup resistors are required during program verification.
P5.0-P5.7 67-60 I/O Port 5
is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 5 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 5 pins being externally pulled low will source current (I characteristics) because of the internal pullup resistors. Port 5 can also be switched into a bidirectional mode, in which CMOS levels are provided. In this bidirectional mode, each port 5 pin can be programmed individually as input or output.
, in the DC
IL
*) I = Input
O = Output
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Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin Number I/O*) Function
P-MQFP-80
HWPD 69 I Hardware Power Down
A low level on this pin for the duration of one machine cycle while the oscillator is running resets the C515C. A low level for a longer period will force the part to power down mode with the pins floating.
C515C
P4.0-P4.7 72-74, 76-80
72 73
74 76 77 78 79 80
I/O Port 4
is an 8-bit quasi-bidirectional I/O port with internal pull-up resistors. Port 4 pins that have 1’s written to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, port 4 pins being externally pulled low will source current (I characteristics) because of the internal pull-up resistors. P4 also contains the external A/D converter control pin, the SSC pins, the CAN controller input/output lines, and the external interrupt 8 input. The output latch corresponding to a secondary functionmust be programmed to a one (1) for that function to operate. The alternate functions are assigned to port 4 as follows: P4.0 ADST External A/D converter start pin P4.1 SCLK SSC Master Clock Output /
P4.2 SRI SSC Receive Input P4.3 STO SSC Transmit Output P4.4 SLS P4.5 INT8 External interrupt 8 input P4.6 TXDC Transmitter output of the CAN controller P4.7 RXDC Receiver input of the CAN controller
SSC Slave Clock Input
Slave Select Input
, in the DC
IL
PE
/SWD 75 I Power saving mode enable / Start watchdog timer
A low level on this pin allows the software to enter the power down, idle and slow down mode. In case the low level is also seen during reset, the watchdog timer function is off on default. Use of the software controlled power saving modes is blocked, when this pin is held on high level. A high level during reset performs an automatic start of the watchdog timer immediately after reset. When left unconnected this pin is pulled high by a weak internal pull-up resistor.
*) I = Input
O = Output
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Table 1 Pin Definitions and Functions (cont’d)
Symbol Pin Number I/O*) Function
P-MQFP-80
VSSCLK 13 Ground (0 V) for on-chip oscillator
This pin is used for ground connection of the on-chip oscillator circuit.
VCCCLK 14 Supply voltage for on-chip oscillator
This pin is used for power supply of the on-chip oscillator circuit.
C515C
VCCE1 VCCE2
32 68
Supply voltage for I/O ports
These pins are used for power supply of the I/O ports during normal, idle, and power-down mode.
VSSE1 VSSE2
35 70
Ground (0 V) for I/O ports
These pins are used for ground connections of the I/O ports during normal, idle, and power-down mode.
VCC1 33 Supply voltage for internal logic
This pins is used for the power supply of the internal logic circuits during normal, idle, and power down mode.
VSS1 34 Ground (0 V) for internal logic
This pin is used for the ground connection of the internal logic circuits during normal, idle, and power down mode.
VCCEXT 50 Supply voltage for external access pins
This pin is used for power supply of the I/O ports and control signals which are used during external accesses (for Port 0, Port 2, ALE, PSEN
, P3.6/WR, and P3.7/RD).
VSSEXT 51 Ground (0 V) for external access pins
This pin is used for the ground connection of the I/O ports and control signals which are used during external accesses (for Port 0, Port 2, ALE, PSEN
, P3.6/WR, and
P3.7/RD).
N.C. 2, 71 Not connected
These pins should not be connected.
*) I = Input
O = Output
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C515C
Figure 4 Block Diagram of the C515C
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C515C
CPU
The C515C is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three­byte instructions. With a 6 MHz crystal, 58% of the instructions are executed in 1 µs (10 MHz : 600 ns).
Special Function Register PSW (Address D0H) Reset Value : 00H
Bit No. MSB LSB
H
D7
CY AC
H
D6
H
D5
F0
H
D4
RS1 RS0 OV F1 PD0
Bit Function
CY Carry Flag
Used by arithmetic instruction.
AC Auxiliary Carry Flag
Used by instructions which execute BCD operations. F0 General Purpose Flag RS1
RS0
Register Bank select control bits
These bits are used to select one of the four register banks.
RS1 RS0 Function
0 0 Bank 0 selected, data address 00H-07 0 1 Bank 1 selected, data address 08H-0F 1 0 Bank 2 selected, data address 10H-17 1 1 Bank 3 selected, data address 18H-1F
H
D3
H
D2
H
D1
H
D0
H
PSW
H
H
H
H
OV Overflow Flag
Used by arithmetic instruction. F1 General Purpose Flag P Parity Flag
Set/cleared by hardware after each instruction to indicate an odd/even
number of "one" bits in the accumulator, i.e. even parity.
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Memory Organization
The C515C CPU manipulates data and operands in the following five address spaces:
– up to 64 Kbyte of internal/external program memory – up to 64 Kbyte of external data memory – 256 bytes of internal data memory – 256 bytes CAN controller registers / data memory – 2K bytes of internal XRAM data memory – a 128 byte special function register area
Figure 5 illustrates the memory address spaces of the C515C.
C515C
Figure 5 C515C Memory Map
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C515C
Control of XRAM/CAN Controller Access
The XRAM in the C515C is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM and the CAN controller is used in the same way as external data memory the same instruction types (MOVX) must be used for accessing the XRAM. Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to the XRAM and the CAN controller.
Special Function Register SYSCON (Address B1H) Reset Value : X010XX01
Bit No. MSB LSB
76543210
B1
H
Bit Function
XMAP1 XRAM/CAN controller visible access control
PMOD
The function of the shaded bits is not described in this section.
Control bit for RD/WR signals during XRAM/CAN Controller accesses. If addresses are outside the XRAM/CAN controller address range or if XRAM is disabled, this bit has no effect. XMAP1 = 0 : The signals RD and WR are not activated during accesses to
XMAP1 = 1 : Ports 0, 2 and the signals RD and WR are activated during
EALE RMAP
the XRAM/CAN Controller
accesses to XRAM/CAN Controller. In this mode, address and data information during XRAM/CAN Controller accesses are visible externally.
XMAP1
XMAP0
SYSCON
B
XMAP0 Global XRAM/CAN controller access enable/disable control
XMAP0 = 0 : The access to XRAM and CAN controller is enabled. XMAP0 = 1 : The access to XRAM and CAN controller is disabled (default
after reset). All MOVX accesses are performed via the external bus. Further, this bit is hardware protected.
Bit XMAP0 is hardware protected. If it is reset once (XRAM/CAN controller access enabled) it cannot be set by software. Only a reset operation will set the XMAP0 bit again.
The XRAM/CAN controller can be accessed by read/write instructions (MOVX A,DPTR, MOVX @DPTR,A), which use the 16-bit DPTR for indirect addressing. For accessing the XRAM or CAN controller, the effective address stored in DPTR must be in the range of F700H to FFFFH.
The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX @Ri,A), which use only an 8-bit address (indirect addressing with registers R0 or R1). Therefore, a special page register XPAGE which provides the upper address information (A8-A15) during 8-bit XRAM accesses. The behaviour of Port 0 and P2 during a MOVX access depends on the control bits XMAP0 and XMAP1 in register SYSCON and on the state of pin EA operating conditions.
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. Table 2 lists the various
Page 18
Semiconductor Group 18 1997-07-01
= 0 EA = 1
EA
XMAP1, XMAP0 XMAP1, XMAP0
00 10 X1 00 10 X1
MOVX @DPTR
MOVX @ Ri
DPTR < XRAM/CAN address range
DPTR
XRAMCAN address range
XPAGE < XRAMCAN addr.page range
XPAGE
XRAMCAN addr.page range
a)P0/P2Bus b)RD/WR active c)ext.memory is used
a)P0/P2 (RD/WR-Data) b)RD/WR inactive c)XRAM is used
a)P0Bus P2I/O b)RD/WR active c)ext.memory is used
a)P0 (RD/WR-Data) P2I/O b)RD/WR inactive c)XRAM is used
Bus
Bus
a)P0/P2Bus b)RD/WR active c)ext.memory is used
a)P0/P2Bus (RD/WR-Data) b)RD/WR active c)XRAM is used
a)P0Bus P2I/O b)RD/WR active c)ext.memory is used
a)P0Bus (RD/WR-Data only) P2I/O b)RD/WR active
c)XRAM is used
a)P0/P2Bus b)RD/WR active c)ext.memory is used
a)P0/P2Bus
b)RD/WR active c) ext.memory is used
a)P0Bus P2I/O b)RD/WR active c)ext.memory is used
a)P0Bus P2I/O
b)RD/WR active
c)ext.memory is used
a)P0/P2Bus b)RD/WR active c)ext.memory is used
a)P0/P2I/0
b)RD/WR inactive c)XRAM is used
a)P0Bus P2I/O b)RD/WR active c)ext.memory is used
a)P2I/O P0/P2I/O
b)RD/WR inactive c)XRAM is used
a)P0/P2Bus b)RD/WR active c)ext.memory is used
a)P0/P2Bus (RD/WR-Data) b)RD/WR active c)XRAM is used
a)P0Bus P2I/O b)RD/WR active c)ext.memory is used
a)P0Bus (RD/WR-Data) P2I/O b)RD/WR active
c)XRAM is used
a)P0/P2Bus b)RD/WR active c)ext.memory is used
a)P0/P2Bus
b)RD/WR active c) ext.memory is used
a)P0Bus P2I/O b)RD/WR active c)ext.memory is used
a)P0Bus P2I/O
b)RD/WR active
c)ext.memory is used
modes compatible to 8051/C501 family
Table 2 Behaviour of P0/P2 and RD
C515C
/WR During MOVX Accesses
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C515C
Reset and System Clock
The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (12 oscillator periods) while the oscillator is running. A pullup resistor is internally connected to VCC to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting the RESET pin to VSS via a capacitor. Figure 6 shows the possible reset circuitries.
Figure 6 Reset Circuitries
Figure 7 shows the recommended oscillator circiutries for crystal and external clock operation.
Figure 7 Recommended Oscillator Circuitries
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C515C
Multiple Datapointers
As a functional enhancement to the standard 8051 architecture, the C515C contains eight 16-bit datapointers instead of only one datapointer. The instruction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in the special function register DPSEL. Figure 8 illustrates the datapointer addressing mechanism.
Data­pointer
DPTR 0000
.0.1.2
DPTR7
DPTR0
DPH(83 ) DPL(82 )
HH
-----
DPSEL(92 )
DPSEL Selected
.2 .1 .0
0 0 1 DPTR 1 0 1 0 DPTR 2 0 1 1 DPTR 3 1 0 0 DPTR 4 1 0 1 DPTR 5 1 1 0 DPTR 6 1 1 1 DPTR 7
H
Figure 8 External Data Memory Addressing using Multiple Datapointers
External Data Memory
MCD00779
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C515C
Enhanced Hooks Emulation Concept
The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too.
Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical.
The Enhanced Hooks TechnologyTM, which requires embedded logic in the C500 allows the C500 together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.
SYSCON
PCON TCON
Optional I/O Ports
ICE-System Interface
to Emulation Hardware
RESET
EA
ALE
PSEN
C500
0
MCU Interface Circuit
Port 3 Port 1
Port Port
2
Target System Interface
RSYSCON
RPCON
RTCON
Enhanced Hooks
RPort 0RPort 2
EH-IC
TEA TALE TPSEN
MCS03280
Figure 9 Basic C500 MCU Enhanced Hooks Concept Configuration
Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.
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C515C
Special Function Registers
The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions : the standard special function register area and the mapped special function register area. Two special function registers of the C515C (PCON1 and DIR5) are located in the mapped special function register area. For accessing the mapped special function register area, bit RMAP in special function register SYSCON must be set. All other special function registers are located in the standard special function register area which is accessed when RMAP is cleared (“0“). As long as bit RMAP is set, mapped special function register area can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set by software, respectively each.
Special Function Register SYSCON (Address B1H) Reset Value : 1010XX01
Bit No. MSB LSB
76543210
B1
Bit Function
RMAP Special function register map bit
The 59 special function registers (SFRs) in the standard and mapped SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C515C are listed in table 3 and table 4. In table 3 they are organized in groups which refer to the functional blocks of the C515C. The CAN-SFRs are also included in table 3. Table 4 illustrates the contents of the SFRs in numeric order of their addresses. Table 5 list the CAN-SFRs in numeric order of their addresses.
CLKP PMOD
H
RMAP = 0 : The access to the non-mapped (standard) special function
RMAP = 1 : The access to the mapped special function register area is
1 RMAP
register area is enabled (reset value).
enabled.
XMAP1
XMAP0
SYSCON
B
Semiconductor Group 22 1997-07-01
Page 23
C515C
Table 3 Special Function Registers - Functional Blocks
Block Symbol Name Address Contents after
Reset
CPU ACC
B DPH DPL DPSEL PSW SP SYSCON
A/D­Converter
ADCON0 ADCON1 ADDATH ADDATL
Interrupt System
IEN0 IEN1
2)
2)
IEN2
2)
IP0 IP1 TCON T2CON SCON IRCON
XRAM XPAGE
2)
Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer
2)
System Control Register
2)
A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Data Register Low Byte
Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 Interrupt Priority Register 1
2)
Timer Control Register
2)
Timer 2 Control Register Serial Channel Control Register Interrupt Request Control Register
Page Address Register for Extended on-chip
E0 F0
83 82 92
D0
81 B1
D8
DC D9 DA
A8 B8
9A A9 B9
88 C8 98 C0
91
H
H H H
H
H
H
H
H
H
H
H
H
H
H H
H H H
H
H
1)
1)
1)
1)
H
1)
1)
1)
1)
1)
1)
XRAM and CAN Controller
SYSCON
Ports P0
P1 P2 P3 P4 P5 DIR5 P6 P7 SYSCON
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved
4) This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set.
2)
System Control Register Port 0
Port 1 Port 2 Port 3 Port 4 Port 5 Port 5 Direction Register Port 6, Analog/Digital Input Port 7
2)
System Control Register
B1
80 90 A0 B0 E8 F8 F8
DB FA B1
H H
H H
H
H H H
H H
1)
1)
1) 1
1)
1)
1) 4)
H
4)
00
H
00
H
00
H
00
H
XXXXX000 00
H
07
H
X010XX01 00
H
0XXXX000 00
H
00XXXXXX 00
H
00
H
XX00X00X 00
H
0X000000 00
H
00
H
00
H
00
H
00
H
X010XX01 FF
H
FF
H
FF
H
FF
H
FF
H
FF
H
FF
H
– XXXXXXX1 X010XX01
3)
B
3)
B
3)
B
3)
B
3)
B
3)
B
3)
B
3)
B
3)
B
Semiconductor Group 23 1997-07-01
Page 24
C515C
Table 3 Special Function Registers - Functional Blocks (cont’d)
Block Symbol Name Address Contents after
Reset
Serial Channel
ADCON0 PCON SBUF SCON SRELL SRELH
CAN ControllerCRSR
IR BTR0 BTR1 GMS0 GMS1 UGML0 UGML1 LGML0 LGML1 UMLM0 UMLM1 LMLM0 LMLM1
2)
A/D Converter Control Register 0
2)
Power Control Register Serial Channel Buffer Register Serial Channel Control Register Serial Channel Reload Register, low byte Serial Channel Reload Register, high byte
Control Register Status Register Interrupt Register Bit Timing Register Low Bit Timing Register High Global Mask Short Register Low Global Mask Short Register High Upper Global Mask Long Register Low Upper Global Mask Long Register High Lower Global Mask Long Register Low Lower Global Mask Long Register High Upper Mask of Last Message Register Low Upper Mask of Last Message Register High Lower Mask of Last Message Register Low Lower Mask of Last Message Register High
Message Object Registers : MCR0 MCR1 UAR0 UAR1 LAR0 LAR1 MCFG DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
5) The notation “n“ in the message object address definition defines the number of the related message object.
Message Control Register Low Message Control Register High Upper Arbitration Register Low Upper Arbitration Register High Lower Arbitration Register Low Lower Arbitration Register High Message Configuration Register Message Data Byte 0 Message Data Byte 1 Message Data Byte 2 Message Data Byte 3 Message Data Byte 4 Message Data Byte 5 Message Data Byte 6 Message Data Byte 7
D8
H
87
H
99
H
98
H
AA
H
BA
H
F700 F701 F702 F704 F705 F706 F707 F708 F709 F70A F70B F70C F70D F70E F70F
F7n0 F7n1 F7n2 F7n3 F7n4 F7n5 F7n6 F7n7 F7n8 F7n9 F7nA F7nB F7nC F7nD F7nE
1
1)
H H H H H H H H H
H H H H H H H H H H
H H H H H H
H H H H H
5)
5)
5)
5)
5)
5)
5)
5)
5)
5)
5)
5)
5)
5)
5)
00
H
00
H
3)
XX
H
00
H
D9
H
XXXXXX11 01
H
3)
XX
H
3)
XX
H
3)
UU
H
0UUUUUUU
3)
UU
H
UUU11111
3)
UU
H
3)
UU
H
3)
UU
H
UUUUU000
3)
UU
H
3)
UU
H
3)
UU
H
UUUUU000
3)
UU
H
3)
UU
H
3)
UU
H
3)
UU
H
3)
UU
H
UUUUU000 UUUUUU00
3)
XX
H
3)
XX
H
3)
XX
H
3)
XX
H
3)
XX
H
3)
XX
H
3)
XX
H
3)
XX
H
3)
B
3)
B
3)
B
3)
B
3)
B
3)
B
3)
B
Semiconductor Group 24 1997-07-01
Page 25
C515C
Table 3 Special Function Registers - Functional Blocks (cont’d)
Block Symbol Name Address Contents after
Reset
)
SSC Interface
SSCCON STB SRB SCF SCIEN SSCMOD
Timer 0/ Timer 1
TCON TH0 TH1 TL0 TL1 TMOD
Compare/ Capture Unit / Timer 2
CCEN CCH1 CCH2 CCH3 CCL1 CCL2 CCL3 CRCH CRCL TH2 TL2 T2CON
Watchdog WDTREL
2)
IEN0
2)
IEN1
2)
IP0
Power Save
PCON PCON1
2)
Modes
SSC Control Register SSC Transmit Buffer SSC Receive Register SSC Flag Register SSC Interrupt Enable Register SSC Mode Test Register
Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register
Comp./Capture Enable Reg. Comp./Capture Reg. 1, High Byte Comp./Capture Reg. 2, High Byte Comp./Capture Reg. 3, High Byte Comp./Capture Reg. 1, Low Byte Comp./Capture Reg. 2, Low Byte Comp./Capture Reg. 3, Low Byte Com./Rel./Capt. Reg. High Byte Com./Rel./Capt. Reg. Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register
Watchdog Timer Reload Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0
Power Control Register Power Control Register 1
93 94 95 AB AC 96
88
8C 8D 8A 8B 89
C1 C3 C5 C7 C2 C4 C6 CB CA CD CC
C8
86
A8 B8
A9 87
88
H H H
H H
H
H
H H H H
H
H H H H H H H
H H H H
H
H
H H
H
H H
1
1
1)
1)
1)
1)
4)
)
07
H
3
XX
)
H
3
XX
)
H
XXXXXX00 XXXXXX00 00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
00
H
0XXXXXXX
3)
B
3)
B
3)
B
1) Bit-addressable special function registers
2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3) “X“ means that the value is undefined and the location is reserved
4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
Semiconductor Group 25 1997-07-01
Page 26
Table 4 Contents of the SFRs, SFRs in numeric order of their addresses
C515C
Addr Register Content
after Reset
2)
80 81 82 83 86
87 88 88
P0 FF
H
SP 07
H
DPL 00
H
DPH 00
H
WDTREL 00
H
PCON 00
H
2)
TCON 00
H
3)
PCON1 0XXX-
H
XXXX 89 8A 8B
TMOD 00
H
TL0 00
H
TL1 00
H
8CHTH0 00 8DHTH1 00
2)
90
P1 FF
H
1)
H H H H H
H H
B H H H H H H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 WDT
.6 .5 .4 .3 .2 .1 .0
PSEL SMOD PDS IDLS SD GF1 GF0 PDE IDLE TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 EWPD
GATE C/T
M1 M0 GATE C/T M1 M0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 T2 CLK-
T2EX INT2 INT6 INT5 INT4 INT3
OUT 91 92
93 94 95 96 98 99 9A
A0 A8
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.
XPAGE 00
H
DPSEL XXXX-
H
SSCCON
H
STB XX
H
SRB XX
H
SSCMOD
H
2)
SCON 00
H
SBUF XX
H
IEN2 X00X-
H
2)
P2 FF
H
2)
IEN0 00
H
H
X000 07
H
H H
00
H H
H
X00X
H H
.7 .6 .5 .4 .3 .2 .1 .0 –––––.2.1.0
B
SCEN TEN MSTR CPOL CPHA BRS2 BRS1 BRS0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0
LOOPB
TRIO 00000LSBSM
SM0 SM1 SM2 REN TB8 RB8 TI RI .7 .6 .5 .4 .3 .2 .1 .0 – EX8 EX7 ESSC ECAN
B
.7 .6 .5 .4 .3 .2 .1 .0 EA WDT ET2 ES ET1 EX1 ET0 EX0
Semiconductor Group 26 1997-07-01
Page 27
Table 4 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
C515C
Addr Register Content
after Reset
A9
IP0 00
H
AAHSRELL D9
1)
H
H
ABHSCF XXXX-
XX00
B
ACHSCIEN XXXX-
XX00
B
2)
B0 B1
B8 B9
P3 FF
H
SYSCON X010-
H
2)
IEN1 00
H
IP1 0X00-
H
H
XX01
H
0000
B
B
BAHSRELH XXXX-
XX11
B
2)
C0 C1HCCEN 00
IRCON 00
H
H H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
OWDS WDTS .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 ––––––WCOL TC
––––––WCEN TCEN
RD WR T1 T0 INT1 INT0 TxD RxD – PMOD EALE RMAP XMAP1 XMAP0
EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 EADC PDIR .5 .4 .3 .2 .1 .0
––––––.1.0
EXF2 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC COCAH3COCAL3COCAH2COCAL2COCAH1COCAL1COCAH0COCAL
0 C2HCCL1 00 C3HCCH1 00 C4HCCL2 00 C5HCCH2 00 C6HCCL3 00 C7HCCH3 00
2)
C8
T2CON 00
H
CAHCRCL 00 CBHCRCH 00 CCHTL2 00 CDHTH2 00
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
H H H H H H H H H H H
.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 T2PS I3FR I2FR T2R1 T2R0 T2CM T2I1 T2I0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0
Semiconductor Group 27 1997-07-01
Page 28
Table 4 Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)
C515C
Addr Register Content
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
after
H H H
1)
CY AC F0 RS1 RS0 OV F1 P BD CLK ADEX BSY ADM MX2 MX1 MX0 .9 .8 .7 .6 .5 .4 .3 .2 .1.0––––––
B
Reset
2)
D0 D8
PSW 00
H
2)
ADCON0 00
H
D9HADDATH 00 DAHADDATL 00XX-
XXXX DBHP6 – .7.6.5.4.3.2.1.0 DCHADCON1 0XXX-
X000
2)
E0 E8 F0 F8 F8
ACC 00
H
2)
P4 00
H
2)
B 00
H
2)
P5 FF
H
2)
DIR5
H
H H H H
3)
FF
H
FAHP7 XXXX-
XXX1
1) X means that the value is undefined and the location is reserved
2) Bit-addressable special function registers
3) This SFR is a mapped SFR. For accessing this SFR, bit PDIR in SFR IP1 must be set.
ADCL –––0MX2MX1MX0
B
.7 .6 .5 .4 .3 .2 .1 .0 RXDC TXDC INT8 SLS STO SRI SCLK ADST .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 –––––––.0
B
Semiconductor Group 28 1997-07-01
Page 29
Table 5 Contents of the CAN Registers in numeric order of their addresses
C515C
Addr.
n=1-F
1)
F700 F701 F702 F704 F705
Register Content
H
CR 01
H
SR XX
H
IR XX
H
BTR0 UU
H
BTR1 0UUU.
H
after Reset
H
H H
H
UUUU F706 F707
F708 F709 F70AHLGML0 UU
GMS0 UU
H
GMS1 UUU1.
H
UGML0 UU
H
UGML1 UU
H
H
1111
H H H
B
F70BHLGML1 UUUU.
U000
B
F70CHUMLM0 UU F70DHUMLM1 UU F70EHLMLM0 UU F70F
F7n0 F7n1
LMLM1 UUUU.
H
MCR0 UU
H
MCR1 UU
H
H H H
U000
H H
B
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2)
TEST CCE 0 0 EIE SIE IE INIT BOFF EWRN – RXOK TXOK LEC2 LEC1 LEC0
INTID
SJW BRP
0 TSEG2 TSEG1
B
ID28-21
ID20-18 11111
ID28-21 ID20-13
ID12-5
ID4-0 0 0 0
ID28-21
ID20-18 ID17-13
ID12-5
ID4-0 0 0 0
MSGVAL TXIE RXIE INTPND RMTPND TXRQ MSGLST
NEWDAT
CPUUPD F7n2 F7n3 F7n4 F7n5
F7n6
1) The notation “n“ in the address definition defines the number of the related message object.
2) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation
UAR0 UU
H
UAR1 UU
H
LAR0 UU
H
LAR1 UUUU.
H
MCFG UUUU.
H
H H H
U000
UU00
ID28-21
ID20-18 ID17-13
ID12-5
ID4-0 0 0 0
B
DLC DIR XTD 0 0
B
Semiconductor Group 29 1997-07-01
Page 30
Table 5 Contents of the CAN Registers in numeric order of their addresses (cont’d)
C515C
Addr.
n=1-F
1)
F7n7 F7n8 F7n9 F7nAHDB3 XX F7nBHDB4 XX F7nCHDB5 XX F7nDHDB6 XX F7nEHDB7 XX
1) The notation “n“ in the address definition defines the number of the related message object.
2) “X“ means that the value is undefined and the location is reserved. “U“ means that the value is unchanged by a reset operation. “U“ values are undefined (as “X“) after a power-on reset operation
Register Content
H
DB0 XX
H
DB1 XX
H
DB2 XX
H
after Reset
H H H H H H H H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2)
.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0
Semiconductor Group 30 1997-07-01
Page 31
C515C
Digital I/O Ports
The C515C allows for digital I/O on 49 lines grouped into 6 bidirectional 8-bit ports and one 1-bit port. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P7 are performed via their corresponding special function registers P0 to P7. The port structure of port 5 of the C515C is especially designed to operate either as a quasi­bidirectional port structure, compatible to the standard 8051-Family, or as a genuine bidirectional port structure. This port operating mode can be selected by software (setting or clearing the bit PMOD in the SFR SYSCON).
The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, time­multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents.
Analog Input Ports
Ports 6 is available as input port only and provides two functions. When used as digital inputs, the corresponding SFR P6 contains the digital value applied to the port 6 lines. When used for analog inputs the desired analog channel is selected by a three-bit field in SFR ADCON0 or SFR ADCON1. Of course, it makes no sense to output a value to these input-only ports by writing to the SFR P6. This will have no effect.
lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications (VIL/VIH). Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte instructions.
Nevertheless, it is possible to use port 6 simultaneously for analog and digital input. However, care must be taken that all bits of P6 that have an undetermined value caused by their analog function are masked.
Semiconductor Group 31 1997-07-01
Page 32
C515C
Port Structure Selection of Port 5
After a reset operation of the C515C, the quasi-bidirectional 8051-compatible port structure is selected. For selection of the bidirectional (CMOS) port 5 structure the bit PMOD of SFR SYSCON must be set. Because each port 5 pin can be programmed as an input or an output, additionally, after the selection of the bidirectional mode the direction register DIR5 of port 5 must be written. This direction register is mapped to the port 5 register. This means, the port register address is equal to its direction register address. Figure 10 illustrates the port- and direction register configuration.
Figure 10 Port Register, Direction Register
Semiconductor Group 32 1997-07-01
Page 33
Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 6 : Table 6
Timer/Counter 0 and 1 Operating Modes Mode Description TMOD Timer/Counter Input Clock
M1 M0 internal external (max)
C515C
0 8-bit timer/counter with a
00
f
/6 x 32 f
OSC
/12 x 32
OSC
divide-by-32 prescaler 1 16-bit timer/counter 0 1 2 8-bit timer/counter with
10
8-bit autoreload 3 Timer/counter 0 used as one
11
/6 f
OSC
OSC
/12
f
8-bit timer/counter and one
8-bit timer / Timer 1 stops
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the count rate is f
OSC
/6.
In the “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is f
/12. External inputs INT0 and INT1 (P3.2, P3.3) can be
OSC
programmed to function as a gate to facilitate pulse width measurements. Figure 11 illustrates the input clock logic
P3.4/T0 P3.5/T1
Gate (TMOD)
P3.2/INT0 P3.3/INT1
OSC
=1
÷
6
C/T = 0
C/T = 1
Control
TR0 TR1
_
<
1
&
f
/6
OSC
Timer 0/1 Input Clock
MCS03117
Figure 11 Timer/Counter 0 and 1 Input Clock Logic
Semiconductor Group 33 1997-07-01
Page 34
C515C
Timer/Counter 2 with Compare/Capture/Reload
The timer 2 of the C515C provides additional compare/capture/reload features. which allow the selection of the following operating modes:
– Compare : up to 4 PWM signals with 16-bit/600 ns resolution – Capture : up to 4 high speed capture inputs with 600 ns resolution – Reload : modulation of timer 2 cycle time
The block diagram in figure 12 shows the general configuration of timer 2 with the additional compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as multifunctional port functions at port 1.
Figure 12 Timer 2 Block Diagram
Semiconductor Group 34 1997-07-01
Page 35
C515C
Timer 2 Operating Modes
The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag TF2 in SFR IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer 2 operation.
Timer Mode : In timer function, the count rate is derived from the oscillator frequency. A prescaler offers the possibility of selecting a count rate of 1/6 or 1/12 of the oscillator frequency.
Gated Timer Mode : In gated timer function, the external input pin T2 (P1.7) functions as a gate to the input of timer 2. lf T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the counting procedure. This facilitates pulse width measurements. The external gate signal is sampled once every machine cycle.
Event Counter Mode : In the event counter function. the timer 2 is incremented in response to a 1­to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input is sampled every machine cycle. Since it takes two machine cycles (12 oscillator periods) to recognize a 1-to-0 transition, the maximum count rate is 1/6 of the oscillator frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for at least one full machine cycle.
Reload of Timer 2 : Two reload modes are selectable: In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also causes the timer 2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software. In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the correspon­ding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1 has been set.
Semiconductor Group 35 1997-07-01
Page 36
C515C
Timer 2 Compare Modes
The compare function of a timer/register combination operates as follows : the 16-bit value stored in a compare or compare/capture register is compared with the contents of the timer register; if the count value in the timer register matches the stored value, an appropriate output signal is generated at a corresponding port pin and an interrupt can be generated.
Compare Mode 0 In compare mode 0, upon matching the timer and compare register contents, the output signal
changes from low to high. lt goes back to a low level on timer overflow. As long as compare mode 0 is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port will have no effect. Figure 13 shows a functional diagram of a port circuit when used in compare mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The input line from the internal bus and the write-to-latch line of the port latch are disconnected when compare mode 0 is enabled.
Compare Register
Circuit
Compare Reg.
16 Bit
Comparator
Bit16
Timer Register
Timer Circuit
Compare Match
Timer
Overflow
Figure 13 Port Latch in Compare Mode 0
Port Circuit
Internal Bus
Write to Latch
S D
Latch
CLK R
Read Latch
Q
Port
Q
Read Pin
V
CC
Port
Pin
MCS02661
Semiconductor Group 36 1997-07-01
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C515C
Compare Mode 1 If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the
new value will not appear at the output pin until the next compare match occurs. Thus, it can be choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the actual pin-level) or should keep its old value at the time when the timer value matches the stored compare value.
In compare mode 1 (see figure 14) the port circuit consists of two separate latches. One latch (which acts as a "shadow latch") can be written under software control, but its value will only be transferred to the port latch (and thus to the port pin) when a compare match occurs.
Port Circuit
Compare Register
Circuit
Compare Reg.
16 Bit
Comparator
16 Bit
Timer Register
Timer Circuit
Compare Match
Internal Bus
Write to Latch
Figure 14 Compare Function in Compare Mode 1
D
Shadow
Latch
CLK
Read Latch
Q
D
Port
Latch
Read Pin
V
CC
Q
QCLK
Port
Pin
MCS02662
Semiconductor Group 37 1997-07-01
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C515C
Serial Interface (USART)
The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 7.
Table 7 USART Operating Modes
Mode
SCON Description
SM0 SM1
0 0 0 Shift register mode, fixed baud rate
Serial data enters and exits through R×D; T×D outputs the shift clock; 8-bit are transmitted/received (LSB first)
1 0 1 8-bit UART, variable baud rate
10 bits are transmitted (through T×D) or received (at R×D)
2 1 0 9-bit UART, fixed baud rate
11 bits are transmitted (through T×D) or received (at R×D)
3 1 1 9-bit UART, variable baud rate
Like mode 2
For clarification some terms regarding the difference between "baud rate clock" and "baud rate" should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is 16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have to provide a "baud rate clock" (output signal in figure 15 to the serial interface which - there divided by 16 - results in the actual "baud rate". Further, the abrevation f
refers to the oscillator frequency
OSC
(crystal or external clock operation). The variable baud rates for modes 1 and 3 of the serial interface can be derived either from timer 1
or from a decdicated baud rate generator (see figure 15).
Semiconductor Group 38 1997-07-01
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C515C
Figure 15 Block Diagram of Baud Rate Generation for the Serial Interface
Table 8 below lists the values/formulas for the baud rate calculation of the serial interface with its dependencies of the control bits BD and SMOD.
Table 8 Serial Interface - Baud Rate Dependencies
Serial Interface Operating Modes
Mode 0 (Shift Register) – Mode 1 (8-bit UART)
Mode 3 (9-bit UART)
Active Control Bits Baud Rate Calculation
BD SMOD
f
/ 6
OSC
0 X Controlled by timer 1 overflow :
SMOD
(2
× timer 1 overflow rate) / 32
1 X Controlled by baud rate generator
SMOD
(2
× f
OSC
) /
(32 × baud rate generator overflow rate)
Mode 2 (9-bit UART) 0
1
f
/ 32
OSC
f
/ 16
OSC
Semiconductor Group 39 1997-07-01
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C515C
SSC Interface
The C515C microcontroller provides a Synchronous Serial Channel unit, the SSC. This interface is compatible to the popular SPI serial bus interface. Figure 16 shows the block diagram of the SSC. The central element of the SSC is an 8-bit shift register. The input and the output of this shift register are each connected via a control logic to the pin P4.2 / SRI (SSC Receiver In) and P4.3 / STO (SSC Transmitter Out). This shift register can be written to (SFR STB) and can be read through the Receive Buffer Register SRB.
Figure 16 SSC Block Diagram
The SSC has implemented a clock control circuit, which can generate the clock via a baud rate generator in the master mode, or receive the transfer clock in the slave mode. The clock signal is fully programmable for clock polarity and phase. The pin used for the clock signal is P4.1/ SCLK. When operating in slave mode, a slave select input is provided which enables the SSC interface and also will control the transmitter output. The pin used for this is P4.4 / SLS.
The SSC control block is responsible for controlling the different modes and operation of the SSC, checking the status, and generating the respective status and interrupt signals.
Semiconductor Group 40 1997-07-01
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C515C
CAN Controller
The on-chip CAN controller is the functional heart which provides all resources that are required to run the standard CAN protocol (11-bit identifiers) as well as the extended CAN protocol (29-bit identifiers). It provides a sophisticated object layer to relieve the CPU of as much overhead as possible when controlling many different message objects (up to 15). This includes bus arbitration, resending of garbled messages, error handling, interrupt generation, etc. In order to implement the physical layer, external components have to be connected to the C515C.
The internal bus interface connects the on-chip CAN controller to the internal bus of the microcontroller. The registers and data locations of the CAN interface are mapped to a specific 256 byte wide address range of the external data memory area (F700H to F7FFH) and can be accessed using MOVX instructions. Figure 17 shows a block diagram of the on-chip CAN controller.
Figure 17 CAN Controller Block Diagram
Semiconductor Group 41 1997-07-01
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C515C
The TX/RX Shift Register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from the Intelligent Memory.
The Bit Stream Processor (BSP) is a sequencer controlling the sequential data stream between the TX/RX Shift Register, the CRC Register, and the bus line. The BSP also controls the EML and the parallel data stream between the TX/RX Shift Register and the Intelligent Memory such that the processes of reception, arbitration, transmission, and error signalling are performed according to the CAN protocol. Note that the automatic retransmission of messages which have been corrupted by noise or other external error conditions on the bus line is handled by the BSP.
The Cyclic Redundancy Check Register (CRC) generates the Cyclic Redundancy Check code to be transmitted after the data bytes and checks the CRC code of incoming messages. This is done by dividing the data stream by the code generator polynomial.
The Error Management Logic (EML) is responsible for the fault confinement of the CAN device. Its counters, the Receive Error Counter and the Transmit Error Counter, are incremented and decremented by commands from the Bit Stream Processor. According to the values of the error counters, the CAN controller is set into the states error
active
, error
passive
and busoff.
The Bit Timing Logic (BTL) monitors the busline input RXDC and handles the busline related bit timing according to the CAN protocol. The BTL synchronizes on a transition at transition, if the CAN controller itself does not transmit a also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the Sample Point in the bit time. The programming of the BTL depends on the baudrate and on external physical delay times.
The Intelligent Memory (CAM/RAM array) provides storage for up to 15 message objects of maximum 8 data bytes length. Each of these objects has a unique identifier and its own set of control and status bits. After the initial configuration, the Intelligent Memory can handle the reception and transmission of data without further microcontroller actions.
Start of Frame
(hard synchronization) and on any further
dominant
recessive
recessive
bit (resynchronization). The BTL
to
dominant
to
dominant
busline
busline
Semiconductor Group 42 1997-07-01
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C515C
10-Bit A/D Converter
The C515C includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8 analog input channels. It operates with a successive approximation technique and uses self calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D converter provides the following features:
– 8 multiplexed input channels (port 6), which can also be used as digital inputs – 10-bit resolution – Single or continuous conversion mode – Internal or external start-of-conversion trigger capability – Interrupt request generation after each conversion – Using successive approximation conversion technique via a capacitor array
– Built-in hidden calibration of offset and linearity errors The main functional blocks of the A/D converter are shown in figure 19. The A/D converter uses basically two clock signals for operation : the input clock fIN (=1/tIN) and the
conversion clock f f
which is applied at the XTAL pins. The input clock fIN is equal to f
OSC
is limited to a maximum frequency of 2 MHz and therefore must be adapted to f programming the conversion clock prescaler. The table in figure 18 shows the prescaler ratios and the resulting A/D conversion times which must be selected for typical system clock rates.
ADC
(=1/t
). These clock signals are derived from the C515C system clock
ADC
. The conversion clock
OSC
OSC
by
MCU System Clock Rate (f
OSC
)
ADCL Conversion Clock
f
[MHz]
ADC
2 MHz 0 .5 4 MHz 0 1 6 MHz 0 1.5 8 MHz 0 2 10 MHz 1 1.25
Figure 18 A/D Converter Clock Selection
Semiconductor Group 43 1997-07-01
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C515C
Figure 19 A/D Converter Block Diagram
Semiconductor Group 44 1997-07-01
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C515C
Interrupt System
The C515C provides 17 interrupt sources with four priority levels. Seven interrupts can be generated by the on-chip peripherals (timer 0, timer 1, timer 2, serial interface, A/D converter, SSC interface, CAN controller), and ten interrupts may be triggered externally (P1.5/T2EX, P3.2/INT0, P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4, P1.2/INT5, P1.3/INT6, P7.0/INT7, P4.5/INT8). The wake-up from power-down mode interrupt has a special functionality which allows to exit from the software power-down mode by a short low pulse at pin P3.2/INT0.
In the C515C the 17 interrupt sources are combined to six groups of two or three interrupt sources. Each interrupt group can be programmed to one of the four interrupt priority levels. Figure 20 to 22 give a general overview of the interrupt sources and illustrate the interrupt request and control flags.
Semiconductor Group 45 1997-07-01
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C515C
Figure 20 Interrupt Request Sources (Part 1)
Semiconductor Group 46 1997-07-01
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C515C
Figure 21 Interrupt Request Sources (Part 2)
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C515C
Figure 22 Interrupt Request Sources (Part 3)
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C515C
Table 9 Interrupt Source and Vectors
Interrupt Source Interrupt Vector Address Interrupt Request Flags
External Interrupt 0 0003 Timer 0 Overflow 000B External Interrupt 1 0013 Timer 1 Overflow 001B Serial Channel 0023 Timer 2 Overflow / Ext. Reload 002B A/D Converter 0043 External Interrupt 2 004B External Interrupt 3 0053 External Interrupt 4 005B External Interrupt 5 0063 External Interrupt 6 006B Wake-up from power-down mode 007B CAN controller 008B External Interrupt 7 00A3 External Interrupt 8 00AB SSC interface 0093
H
H
H
H
H
H
H
H
H
H
H
H
H H H H
H
IE0 TF0 IE1 TF1 RI / TI TF2 / EXF2 IADC IEX2 IEX3 IEX4 IEX5 IEX6 – – – – TC / WCOL
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C515C
Fail Save Mechanisms
The C515C offers two on-chip peripherals which monitor the program flow and ensure an automatic "fail-safe" reaction for cases where the controller’s hardware fails or the software hangs up:
– A programmable watchdog timer (WDT) with variable time-out period from 512 microseconds
up to approx. 1.1 seconds at 6 MHz.
– An oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for a fast internal reset after power-on.
Programmable Watchdog Timer
The watchdog timer in the C515C is a 15-bit timer, which is incremented by a count rate of f to f
/192. For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog
OSC
timer can be written. Figure 23 shows the block diagram of the watchdog timer unit.
OSC
/6 up
Figure 23 Block Diagram of the Programmable Watchdog Timer
The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD, but it cannot be stopped during active mode of the C515C. If the software fails to refresh the running watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog timer. The refresh sequence consists of two consequtive instructions which set the bits WDT and SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor.
Semiconductor Group 50 1997-07-01
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Oscillator Watchdog
The oscillator watchdog unit serves for four functions:
Monitoring of the on-chip oscillator's function
The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC oscillator and the device is brought into reset; if the failure condition disappears (i.e. the on­chip oscillator has a higher frequency than the RC oscillator), the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again.
Fast internal reset after power-on
The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function.
Restart from the hardware power down mode.
If the hardware power down mode is terminated the oscillator watchdog has to control the correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog function is only part of the complete hardware power down sequence; however, the watchdog works identically to the monitoring function.
Control of external wake-up from software power-down mode
When the software power-down mode is left by a low level at the P3.2/INT0 pin, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power­down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the on-chip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize.
C515C
Semiconductor Group 51 1997-07-01
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C515C
Figure 24 Block Diagram of the Oscillator Watchdog
Power Saving Modes
The C515C provides two basic power saving modes, the idle mode and the power down mode. Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate in normal operating mode and it can be also used for further power reduction in idle mode.
Idle mode
The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to work. Idle mode is entered by software and can be left by an interrupt or reset.
Power down mode
The operation of the C515C is completely stopped and the oscillator is turned off. This mode is used to save the contents of the internal RAM with a very low standby current. Software power down mode : Software power down mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/INT0. Hardware power down mode : Hardware power down mode is entered when the pin HWPD is put to low level.
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C515C
Slow-down mode
The controller keeps up the full operating functionality, but its normal clock frequency is internally divided by 32. This slows down all parts of the controller, the CPU and all peripherals, to 1/32-th of their normal operating frequency. Slowing down the frequency significantly reduces power consumption. The slow down mode can be combined with the idle mode.
Table 10 gives a general overview of the entry and exit conditions of the power saving modes. Table 10
Power Saving Modes Overview Mode Entering
Leaving by Remarks (2-Instruction Example
Idle mode ORL PCON, #01H
ORL PCON, #20H
Ocurrence of an
interrupt from a
peripheral unit
Hardware Reset
CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock
Software Power-Down Mode
Hardware Power-Down Mode
ORL PCON, #02H ORL PCON, #40H
Hardware Reset Oscillator is stopped;
Short low pulse at
pin P3.2/INT0
contents of on-chip RAM and SFR’s are maintained;
HWPD = low HWPD = high C515C is put into its reset state
and the oscillator is stopped; ports become floating outputs
Slow Down Mode ORL PCON,#10H ANL PCON,#0EFH
or
Oscillator frequency is reduced to 1/32 of its nominal frequency
Hardware Reset
V
In the power down mode of operation,
can be reduced to minimize power consumption. It must
CC
be ensured, however, that VCC is not reduced before the power down mode is invoked, and that V is restored to its normal operating level, before the power down mode is terminated.
CC
If e.g. the idle mode is left through an interrupt, the microcontroller state (CPU, ports, peripherals) remains preserved. If a power saving mode is left by a hardware reset, the microcontroller state is disturbed and replaced by the reset state of the C515C.
Semiconductor Group 53 1997-07-01
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C515C
Absolute Maximum Ratings
Ambient temperature under bias (TA) ......................................................... – 40 to 110 °C
Storage temperature (T
Voltage on VCC pins with respect to ground (VSS) ....................................... – 0.5 V to 6.5 V
Voltage on any pin with respect to ground (VSS)......................................... – 0.5 V to VCC +0.5 V
Input current on any pin during overload condition..................................... – 10 mA to 10 mA
Absolute sum of all input currents during overload condition ..................... I 100 mA I
Power dissipation........................................................................................ TBD
Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions ( Voltage on
V
CC
absolute maximum ratings.
) .......................................................................... – 65 °C to 150 °C
stg
V
>
V
CC
or
pins with respect to ground (
IN
V
) must not exceed the values defined by the
SS
V
<
V
SS
) the
IN
Semiconductor Group 54 1997-07-01
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C515C
DC Characteristics
V
= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C515C-8R
CC
T
= – 40 to 85 °C for the SAF-C515C-8R
A
T
= – 40 to 110 °C for the SAH-C515C-8R
A
Parameter Symbol Limit Values Unit Test Condition
min. max.
Input low voltages all except EA, RESET, HWPD EA pin RESET and HWPD pins Port 5 in CMOS mode
Input high voltages all except XTAL2, RESET
, and HWPD) XTAL2 pin RESET and HWPD pins Port 5 in CMOS mode
Output low voltages Ports 1, 2, 3, 4, 5, 7 (incl. CMOS) Port 0, ALE, PSEN
, CPUR
P4.1, P4.3 in push-pull mode Output high voltages
Ports 1, 2, 3, 4, 5, 7
Port 0 in external bus mode, ALE, PSEN, CPUR Port 5 in CMOS mode P4.1, P4.3 in push-pull mode
Logic 0 input current Ports 1, 2, 3, 4, 5, 7
Logical 0-to-1 transition current Ports 1, 2, 3, 4, 5, 7
V V V V
V V V V
V V V
V
V
V V
I I
IL IL1 IL2 ILC
IH IH1 IH2 IHC
OL OL1 OL3
OH
OH2
OHC OH3
IL
TL
– 0.5 – 0.5 – 0.5 – 0.5
0.2 VCC + 0.9
0.7 V
CC
0.6 V
CC
0.7 V
CC
– – –
2.4
0.9 V
CC
2.4
0.9 V
CC
0.9 V
CC
0.9 V
CC
0.2 VCC – 0.1
0.2 VCC – 0.3
0.2 VCC + 0.1
0.3 V
CC
V
+ 0.5
CC
V
+ 0.5
CC
V
+ 0.5
CC
V
+ 0.5
CC
0.45
0.45
0.45
– – – – – –
V V V V
V V V V
V V V
V V V V V V
– – – –
– – – –
I
= 1.6 mA
OL
I
= 3.2 mA
OL
I
= 3.75 mA
OL
I
= – 80 µA
OH
I
= – 10 µA
OH
I
= – 800 µA
OH
I
= – 80 µA
OH
I
= – 800 µA
OH
I
= – 833 µA
OH
– 10 – 70 µA VIN = 0.45 V – 65 – 650 µA VIN = 2 V
1)
1)
1)
)
2)
Input leakage current Port 0, EA
, P6, HWPD, AIN0-7 I
LI
± 1 µA 0.45 < VIN < V
CC
Input low current To RESET for reset XTAL2 PE/SWD
Pin capacitance
Overload current
I I I
C
I
LI2 LI3 LI4
OV
– – –
IO
–10pFf ± 5mA
– 100 – 15 – 20
µA µA µA
V
= 0.45 V
IN
V
= 0.45 V
IN
V
= 0.45 V
IN
= 1 MHz,
c
T
= 25 °C
A
8) 9)
Semiconductor Group 55 1997-07-01
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C515C
Power Supply Current Parameter Symbol Limit Values Unit Test Condition
Active mode 6 MHz
10 MHz
Idle mode 6 MHz
10 MHz
Active mode with slow-down enabled
Idle mode with slow-down enabled
6 MHz 10 MHz
6 MHz 10 MHz
Power-down mode I
10)
typ.
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
I
CC
PD
12.0
18.9
6.9
10.5 TBD
TBD TBD
TBD TBD 50 µA VCC = 25.5 V
max.
16.1
25.5
9.8 15
TBD TBD
TBD TBD
11)
mA mA
mA mA
mA mA
mA mA
4)
5)
6)
7)
3)
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input.
V
2) Capacitive loading on ports 0 and 2 may cause the
V
0.9
specification when the address lines are stabilizing.
CC
on ALE and PSEN to momentarily fall below the
OH
3) IPD (power-down mode) is measured under following conditions:
= RESET = Port 0 = Port 6 = VCC ; XTAL1 = N.C.; XTAL2 = VSS ; PE/SWD = VSS ; HWPD = VCC ;
EA
V
= VSS ; V
AGND
I
(hardware power-down mode) is independent of any particular pin connection.
PD
= VCC ; all other pins are disconnected.
AREF
4) ICC (active mode) is measured with:
t
, t
XTAL2 driven with
= PE/SWD = Port 0 = Port 6 = VCC ; HWPD = VCC ; RESET = VSS ; all other pins are disconnected.
EA
CLCH
= 5 ns , VIL = VSS + 0.5 V, VIH =
CHCL
V
– 0.5 V; XTAL1 = N.C.;
CC
5) ICC (idle mode) is measured with all output pins disconnected and with all peripherals disabled;
t
, t
XTAL2 driven with RESET
= VCC ; EA = VSS ; Port0 = VCC ; all other pins are disconnected;
CLCH
= 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL1 = N.C.;
CHCL
6) ICC (active mode with slow-down mode) is measured : TBD
7) ICC (idle mode with slow-down mode) is measured : TBD
8) Overload conditions occur if the standard operating conditions are exceeded, ie. the voltage on any pin
V
exceeds the specified range (i.e.
> VCC + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VCC and VSS must
OV
remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.
9) Not 100% tested, guaranteed by design characterization
I
10)The typical
values are periodically measured at T
CC
11)The maximum ICC values are measured under worst case conditions (T
= +25 ˚C and V
A
= 5 V but not 100% tested.
CC
= 0 ˚C or -40 ˚C and V
A
= 5.5 V)
CC
Semiconductor Group 56 1997-07-01
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C515C
MCD03313
25
mA
Ι
CC
20
Ι
CC max
Ι
CC typ
Active Mode
Active Mode
15
10
5
0
02457
13 68MHz 10
Figure 25 ICC Diagram
Power Supply Current Calculation Formulas Parameter Symbol Formula
Idle Mode
Idle Mode
f
OSC
Active mode
Idle mode
Active mode with slow-down enabled
Idle mode with slow-down enabled
Note : f
is the oscillator frequency in MHz. ICC values are given in mA.
osc
I
CC typ
I
CC max
I
CC typ
I
CC max
I
CC typ
I
CC max
I
CC typ
I
CC max
1.72 * f
2.33 * f
0.9 * f
1.3 * f TBD
TBD TBD
TBD
OSC OSC
OSC OSC
+ 1.72 + 2.15
+ 1.5 + 2.0
Semiconductor Group 57 1997-07-01
Page 58
A/D Converter Characteristics
V
= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C515C-8R
CC
T
= – 40 to 85 °C for the SAF-C515C-8R
A
T
= – 40 to 110 °C for the SAH-C515C-8R
A
C515C
4 V V
VCC+0.1 V ; VSS-0.1 V V
AREF
VSS+0.2 V
AGND
Parameter Symbol Limit Values Unit Test Condition
min. max.
Analog input voltage
V
Sample time t
Conversion cycle time t
Total unadjusted error T Internal resistance of
R
reference voltage source Internal resistance of
R
analog source ADC input capacitance C
Notes see next page.
AIN
S
ADCC
UE
AREF
ASRC
AIN
V
AGND
16 x t
96 x t
V
AREF
8 x t
48 x t
V ns Prescaler ÷ 8
IN
IN
ns Prescaler ÷ 8
IN IN
± 2 LSB – t
ADC
/ 250
k
- 0.25
tS / 500
k
- 0.25
–50pF
1)
Prescaler ÷ 4
Prescaler ÷ 4
4)
t
in [ns]
ADC
t
in [ns]
S
6)
5) 6)
2) 6)
Clock calculation table :
2)
3)
Clock Prescaler
ADCL t
ADC
Ratio
÷ 8 1 8 x t ÷ 4 0 4 x t
Further timing conditions : t
min = 500 ns
ADC
tIN = 1 / f
t
16 x tIN 96 x tIN
IN
8 x tIN 48 x tIN
IN
OSC
t
S
= t
CLP
ADCC
Semiconductor Group 58 1997-07-01
Page 59
Notes:
1) V
2) During the sample time the input capacitance C
may exeed V
AIN
AGND
these cases will be X000
or V
or X3FFH, respectively.
H
up to the absolute maximum ratings. However, the conversion result in
AREF
can be charged/discharged by the external source. The
AIN
internal resistance of the analog source must allow the capacitance to reach their final voltage level within t After the end of the sample time t
, changes of the analog input voltage have no effect on the conversion
S
result.
C515C
S
.
3) This parameter includes the sample time t
calibration. Values for the conversion clock t
, the time for determining the digital result and the time for the
S
depend on programming and can be taken from the table on
ADC
the previous page.
4) T
is tested at V
UE
AREF
= 5.0 V, V
= 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all
AGND
other voltages within the defined voltage range. If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible.
5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing.
6) Not 100% tested, but guaranteed by design characterization.
Semiconductor Group 59 1997-07-01
Page 60
C515C
AC Characteristics
V
= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C515C-8R
CC
T
= – 40 to 85 °C for the SAF-C515C-8R
A
T
= – 40 to 110 °C for the SAH-C515C-8R
A
(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)
Program Memory Characteristics Parameter Symbol Limit Values Unit
ALE pulse width Address setup to ALE Address hold after ALE ALE to valid instruction in ALE to PSEN PSEN
PSEN
pulse width t
to valid instruction in t
Input instruction hold after PSEN Input instruction float after PSEN Address valid after PSEN Address to valid instruction in
Address float to PSEN
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
PLPH
PLIV
t
PXIX
t
PXIZ
t
PXAV
t
AVIV
t
AZPL
10-MHz clock
Duty Cycle
0.4 to 0.6
Variable Clock
1/CLP = 2 MHz to
10 MHz
min. max. min. max.
60 CLP - 40 ns 15 TCL 15 TCL
-25 – ns
Hmin
-25 – ns
Hmin
113 2 CLP - 87 ns 20 TCL 115 CLP+
TCL
75 CLP+
-20 ns
Lmin
–ns
-30
Hmin
TCL
Hmin
ns
- 65
00–ns
*)
30 TCL
*)
35 TCL
- 5 ns
Lmin
180 2 CLP +
TCL
Lmin
Hmin
-10 ns
ns
-60
0 0–ns
*)
Interfacing the C515C to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers.
Semiconductor Group 60 1997-07-01
Page 61
C515C
External Data Memory Characteristics Parameter Symbol Limit Values Unit
RD
pulse width
WR
pulse width
Address hold after ALE
to valid data in
RD
Data hold after RD Data float after RD ALE to valid data in Address to valid data in
ALE to WR
or RD
Address valid to WR WR
or RD high to ALE high
Data valid to WR
transition
Data setup before WR
Data hold after WR Address float after RD
t
RLRH
t
WLWH
t
LLAX2
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
WHLH
t
QVWX
t
QVWH
t
WHQX
t
RLAZ
10-MHz
clock
Variable Clock
1/CLP= 2 MHz to 10 MHz
Duty Cycle
0.4 to 0.6
min. max. min. max.
230 3 CLP - 70 ns 230 3 CLP - 70 ns 48 CLP - 15 ns – 150 2 CLP+
TCL
Hmin
- 90
ns
00–ns – 80 CLP - 20 ns – 267 4 CLP - 133 ns – 285 4 CLP +
TCL
Hmin
90 190 CLP +
TCL
Lmin
- 50
CLP+ TCL
Lmin
-155
+ 50
ns
ns
103 2 CLP - 97 ns 15 65 TCL 5 TCL 218 3 CLP +
TCL
13 TCL
- 25 TCL
Hmin
- 35 ns
Lmin
Hmin
+ 25 ns
–ns
- 122
Lmin
- 27 ns
Hmin
–0– 0 ns
Semiconductor Group 61 1997-07-01
Page 62
C515C
SSC Interface Characteristics Parameter Symbol Limit Values Unit
min. max.
Clock Cycle Time : Master Mode
Slave Mode Clock high time Clock low time Data output delay Data output hold Data input setup Data input hold TC bit set delay
t
SCLK
t
SCLK
t
SCH
t
SCL
t
D
t
HO
t
S
t
HI
t
DTC
0.4
1.0
– –
µs µs
360 ns 360 ns – 100 ns 0–ns 100 ns 100 ns – 8 CLP ns
External Clock Drive at XTAL2 Parameter Symbol CPU Clock = 10 MHz
Duty cycle 0.4 to 0.6
Variable CPU Clock
1/CLP = 2 to 10 MHz
Unit
min. max. min. max.
Oscillator period CLP 100 100 100 500 ns High time TCL Low time TCL Rise time Fall time
t
R
t
F
H
L
40 40 CLP-TCL 40 40 CLP-TCL
ns
L
ns
H
12 12 ns
12 12 ns Oscillator duty cycle DC 0.4 0.6 40 / CLP 1 - 40 / CLP – Clock cycle TCL 40 60 CLP * DC
min
CLP * DC
max
ns
Note: The 10 MHz values in the tables are given as an example for a typical duty cycle variation of
the oscillator clock from 0.4 to 0.6.
Semiconductor Group 62 1997-07-01
Page 63
ALE
t
C515C
LHLL
PSEN
Port 0
Port 2
Figure 26 Program Memory Read Cycle
t
AVLL PLPH
t
t
LLPL
t
LLIV
t
PLIV
t
AZPL
t
LLAX
t
t
PXAV
t
PXIZ
PXIX
A0 - A7 Instr.IN A0 - A7
t
AVIV
A8 - A15 A8 - A15
t
WHLH
MCT00096
ALE
PSEN
RD
Port 0
Port 2
Figure 27 Data Memory Read Cycle
t
LLDV
t
LLWL
t
AVLL
t
LLAX2
A0 - A7 from
Ri or DPL from PCL
t
AVWL
t
AVDV
t
RLDV
t
RLAZ
t
RLRH
Data IN
t
RHDZ
t
RHDX
A0 - A7 Instr.
A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH
IN
MCT00097
Semiconductor Group 63 1997-07-01
Page 64
ALE
PSEN
t
WHLH
C515C
WR
t
AVLL
Port 0
A0 - A7 from
Ri or DPL from PCL
t
AVWL
Port 2
Figure 28 Data Memory Write Cycle
t
t
LLAX2
LLWL
t
QVWX
t
WLWH
t
QVWH
Data OUT
t
WHQX
A0 - A7
A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH
Instr.IN
MCT00098
Figure 29 External Clock Drive at XTAL2
Semiconductor Group 64 1997-07-01
Page 65
SCLK
STO
SRI
t
SCLK
t
SCL
tt
D
t
SCH
HD
~
~~
~
MSB LSB
~
~
t
StHI
~
~
MSB LSB
~
~~
t
DTC
C515C
TC
~
MCT02417
Notes : Shown is the data/clock relationship for CPOL=CPHA=1. The timing diagram is valid
for the other cases accordingly. In the case of slave mode and CPHA=0, the output delay for the MSB applies to the
falling edge of SLS (if transmitter is enabled). In the case of master mode and CPHA=0, the MSB becomes valid after the data has
been written into the shift register, i.e. at least one half SCLK clock cycle before the first clock transition.
Figure 30 SSC Timing
Semiconductor Group 65 1997-07-01
Page 66
C515C
ROM Verification Mode 1 Parameter Symbol Limit Values Unit
min. max.
Address to valid data
Figure 31 ROM Verification Mode 1
t
AVQV
5 CLP ns
Semiconductor Group 66 1997-07-01
Page 67
C515C
ROM Verification Mode 2 Parameter Symbol Limit Values Unit
min. typ max.
ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency
ALE
Port 0
t
AWD
t
AS
t
DVA
t
AWD
t
ACY
t
DVA
t
DSA
t
AS
1/ CLP
t
DSA
CLP ns – 6 CLP ns – 2 CLP ns 4 CLP ns – t
CL
–ns
4–6MHz
t
ACY
Data Valid
P3.5
Figure 32 ROM Verification Mode 2
MCT02613
Semiconductor Group 67 1997-07-01
Page 68
V
-0.5 V
CC
V
+0.90.2
CC
Test Points
V
0.2 -0.1
CC
0.45 V
MCT00039
AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at V
for a logic ’1’ and V
IHmin
for a logic ’0’.
ILmax
Figure 33 AC Testing: Input, Output Waveforms
C515C
-0.1 V
V
OH
V
+0.1 V
OL
MCT00038
V
Load
V
V
Load
Load
+0.1 V
Timing Reference
Points
-0.1 V
For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.
I
OL/IOH
≥ ± 20 mA
Figure 34 AC Testing : Float Waveforms
Figure 35 Recommended Oscillator Circuits for Crystal Oscillator
Semiconductor Group 68 1997-07-01
Page 69
P-MQFP-80-1 (SMD)
(Plastic Metric Quad Flat Package)
C515C
Figure 36 Package Outlines
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”
SMD = Surface Mounted Device
GPM05249
Dimensions in mm
Semiconductor Group 69 1997-07-01
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