Datasheet SAB-C515A-4R24M, SAB-C515A-4RM, SAB-C515A-L24M, SAB-C515A-LM, SAF-C515A-4R24M Datasheet (Siemens)

Microcomputer Components

8-Bit CMOS Microcontroller

C515A

Data Sheet 10.97

C515A Data Sheet

Revision History: Current Version: 10.97

Previous Version: none
Page

(in previous
Version)

Page
(in current
Version)

Subjects (major changes since last revision)

Edition 10.97
Published by Siemens AG,

Bereich Halbleiter, Marketing­Kommunikation, Balanstraße 73,
81541 München

Siemens AG 1997.

©

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we
will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in­curred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components
written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

1

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems

2

with the express

8-Bit CMOS Microcontroller

Advance Information

Full upward compatibility with SAB 80C515A/83C515A-5

•

•

Up to 24 MHz external operating frequency
– 500 ns instruction cycle at 24 MHz operation

•

32K byte on-chip ROM (with optional ROM protection)
– alternatively up to 64K byte external program memory

•

Up to 64K byte external data memory

•

256 byte on-chip RAM

•

1K byte on-chip RAM (XRAM)

•

Six 8-bit parallel I/O ports

•

One input port for analog/digital input

•

Full duplex serial interface (USART)
– 4 operating modes, fixed or variable baud rates

•

Three 16-bit timer/counters
– Timer 0 / 1 (C501 compatible)
– Timer 2 for 16-bit reload, compare, or capture functions

C515A

(further features are on next page)

Oscillator
Watchdog

Power
Saving

Support Module

Modes

On-Chip Emulation

A / D Converter

Digital

Input

Watchdog

Timer

10-Bit

Port 5Port 6

I / O I / OAnalog /

T 2

Port 4

XRAM

1 K x 8

T 0

T 1

256 x 8

CPU

ROM

32 k x 8

RAM

USART

Port 0

Port 1

Port 2

Port 3

I / O

I / O

I / O

I / O

MCA03239

Figure 1
C515A Functional Units

Semiconductor Group 3 1997-10-01

Features (cont’d):

•

10-bit A/D converter
– 8 multiplexed analog inputs
– Built-in self calibration

•

16-bit watchdog timer

•

Power saving modes
– Slow down mode
– Idle mode (can be combined with slow down mode)
– Software power down mode with wake-up capability through INT0
– Hardware power down mode

•

12 interrupt sources (7 external, 5 internal) selectable at 4 priority levels

•

ALE switch-off capability

•

On-chip emulation support logic (Enhanced Hooks Technology

•

P-MQFP-80-1 package

•

Temperature Ranges: SAB-C515A

SAF-C515A
SAH-C515A
SAK-C515

T

= 0 to 70 ° C

A

T

= – 40 to 85 ° C

A

T

= – 40 to 85 ° C

A

T

= – 40 to 110 ° C (max. operating frequency: 18 MHz)

A

TM

C515A

pin

)

The C515A is an upward compatible version of the SAB 80C515A/83C515A-5 8-bit microcontroller
which additionally provides an improved 10-bit A/D converter, ALE switch-off capability, on-chip
emulation support, ROM protection, and enhanced power saving mode capabilities. With a
maximum external clock rate of 24 MHz it achieves a 500 ns instruction cycle time (1
The C515A is mounted in a P-MQFP-80 package.

Ordering Information
Type Ordering Code Package Description

(8-Bit CMOS microcontroller)

SAB-C515A-4RM Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (18 MHz)
SAF-C515A-4RM Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (18 MHz)

ext. temp. – 40 ° C to 85 ° C
SAB-C515A-4R24M Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (24 MHz)
SAF-C515A-4R24M Q67121-DXXXX P-MQFP-80-1 with mask programmable ROM (24 MHz)

ext. temp. – 40 ° C to 85 ° C
SAB-C515A-LM Q67121-C1068 P-MQFP-80-1 for external memory (18 MHz)
SAF-C515A-LM Q67121-C1069 P-MQFP-80-1 for external memory (18 MHz)

ext. temp. – 40 ° C to 85 ° C
SAB-C515A-L24M Q67121-C1070 P-MQFP-80-1 for external memory (24 MHz)

µ

s at 12 MHz).

SAF-C515A-L24M Q67127-C2020 P-MQFP-80-1 for external memory (24 MHz)

ext. temp. – 40 ° C to 85 ° C

Note: Versions for extended temperature ranges – 40 ° C to 110 ° C and – 40 ° C to 125 ° C

(SAH-C515A and SAK-C515A) are available on request. The ordering number of ROM
types (DXXXX extensions) is defined after program release (verification) of the customer.

Semiconductor Group 4 1997-10-01

C515A

XTAL1
XTAL2

ALE
PSEN
EA
RESET
PE / SWD
HWPD

V

AREF

V

AGND

V

CC

C515A

V

SS

Port 0
8-Bit Digit. I / O

Port 1
8-Bit Digit. I / O

Port 2
8-Bit Digit. I / O

Port 3
8-Bit Digit. I / O

Port 4
8-Bit Digit. I / O

Port 5
8-Bit Digit. I / O

Port 6
8-Bit Analog /
Digital Input

MCL03240

Figure 2
Logic Symbol

Additional Literature

For further information about the C515A the following literature is available:

Title Ordering Number

C515A 8-Bit CMOS Microcontroller User’s Manual B158-H7051-X-X-7600
C500 Microcontroller Family

B158-H6987-X-X-7600

Architecture and Instruction Set User’s Manual
C500 Microcontroller Family - Pocket Guide B158-H6986-X-X-7600

Semiconductor Group 5 1997-10-01

P5.7

P0.7 / AD7

P0.6 / AD6

P0.5 / AD5

P0.4 / AD4

P0.3 / AD3

P0.2 / AD2

P0.0 / AD0

P0.1 / AD1

N.C.

N.C.

EA

ALE

PSEN

N.C.

P2.7 / A15

P2.6 / A14

P2.4 / A12

P2.5 / A13

P2.3 / A11

C515A

P5.6
P5.5
P5.4
P5.3
P5.2
P5.1
P5.0

N.C.

HWPD

N.C.
N.C.

P4.0 / ADST

P4.1
P4.2

PE / SWD

P4.3
P4.4
P4.5
P4.6
P4.7

42434445464748495459 58 5657 55 5253 51

4150

40
39
38
37
36
35
34
33
32

31

30
29
28
27
26
25
24
23
22

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79

60

C515A

80 21

23456789 1311 12 14 15 16 17 18 19

20101

P2.2 / A10
P2.1 / A9
P2.0 / A8
XTAL1
XTAL2

V

SS

V

SS

V

CC

V

CC

P1.0 / INT3 / CC0
P1.1 / INT4 / CC1
P1.2 / INT5 / CC2
P1.3 / INT6 / CC3
P1.4 / INT2
P1.5 / T2EX
P1.6 / CLKOUT
P1.7 / T2
N.C.
P3.7 / RD
P3.6 / WR

N.C.

AREFVAGND

V

RESET

P6.1 / AIN1

P6.2 / AIN2

P6.4 / AIN4

P6.3 / AIN3

P6.0 / AIN0

P6.5 / AIN5

P6.6 / AIN6

P6.7 / AIN7

Figure 3
Pin Configuration P-MQFP-80 Package (top view)

N.C.

N.C.

P3.1 / TxD

P3.0 / RxD

P3.3 / INT1

P3.2 / INT0

P3.5 / T1

P3.4 / T0

MCP03241

Semiconductor Group 6 1997-10-01

Table 1
Pin Definitions and Functions

C515A

Symbol Pin Number

(P-MQFP-80)

P4.0-P4.7 72-74,

76-80

72

PE

/SWD 75 I

I/O*) Function

I/O Port 4

is an 8-bit quasi-bidirectional I/O port with internal pull­up resistors. Port 4 pins that have 1’s written to them are
pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port 4 pins being
externally pulled low will source current ( I
characteristics) because of the internal pull-up resistors.
P4 also contains the external A/D converter control pin.
The output latch corresponding to a secondary function
must be programmed to a one (1) for that function to
operate. The secondary function is assigned to port 6 as
follows:
P4.0 / ADST

Power Saving Mode

A low level on this pin allows the software to enter the
power down, idle, and slow down mode. In case the low
level is also seen during reset, the watchdog timer
function is off on default.
Use of the software controlled power saving modes is
blocked when this pin is held on high level. A high level
during reset performs an automatic start of the
watchdog timer immediately after reset.
When left unconnected this pin is pulled high by a weak
internal pull-up resistor.

Note: If PE
watchdog is disabled (testmode)!

external A/D converter start pin

Enable

/SWD is low and V

, in the DC

IL

/ Start Watchdog Timer

is low the oscillator

AREF

RESET

1I

RESET

A low level on this pin for the duration of two machine
cycles while the oscillator is running resets the C515A.
A small internal pullup resistor permits power-on reset

VAREF 3 –
VAGND 4 –
P6.0-P6.7 12-5 I

using only a capacitor connected to V

Reference Voltage for the A/D converter
Reference Ground for the A/D converter
Port 6

SS

.

is an 8-bit unidirectional input port to the A/D converter.
Port pins can be used for digital input, if voltage levels
simultaneously meet the specifications for high/low input
voltages and for the eight multiplexed analog inputs.

*) I = Input

O = Output

Semiconductor Group 7 1997-10-01

Table 1
Pin Definitions and Functions (cont’d)

C515A

Symbol Pin Number

(P-MQFP-80)

P3.0-P3.7 15-22

15

16

17

18

19
20
21

22

I/O*) Function

I/O Port 3

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 3 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 3 pins being
externally pulled low will source current (I IL, in the DC
characteristics) because of the internal pullup resistors.
Port 3 also contains the interrupt, timer, serial port and
external memory strobe pins that are used by various
options. The output latch corresponding to a secondary
function must be programmed to a one (1) for that
function to operate. The secondary functions are
assigned to the pins of port 3, as follows:
P3.0 / RxD Receiver data input (asynch.)

P3.1 / TxD Transmitter data output

P3.2 / INT0 External interrupt 0 input /

P3.3 / INT1 External interrupt 1 input /

P3.4 / T0 Timer 0 counter input
P3.5 / T1 Timer 1 counter input
P3.6 / WR

P3.7 / RD RD control output; enables

or data input/output (synch.)
of serial interface

(asynch.) or clock output
(synch.) of serial interface

timer 0 gate control input

timer 1 gate control input

WR control output; latches
the data byte from port 0 into
the external data memory

the external data memory

*) I = Input

O = Output

Semiconductor Group 8 1997-10-01

Table 1
Pin Definitions and Functions (cont’d)

C515A

Symbol Pin Number

(P-MQFP-80)

P1.0 - P1.7 31-24

31

30

29

28

27
26

25
24

I/O*) Function

I/O Port 1

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 1 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 1 pins being
externally pulled low will source current (I IL, in the DC
characteristics) because of the internal pullup resistors.
The port is used for the low-order address byte during
program verification. Port 1 also contains the interrupt,
timer, clock, capture and compare pins that are used by
various options. The output latch corresponding to a
secondary function must be programmed to a one (1) for
that function to operate (except when used for the
compare functions). The secondary functions are
assigned to the port 1 pins as follows:
P1.0 / INT3 / CC0 Interrupt 3 input /

P1.1 / INT4 / CC1 Interrupt 4 input /

P1.2 / INT5 / CC2 Interrupt 5 input /

P1.3 / INT6 / CC3 Interrupt 6 input /

P1.4 / INT2
P1.5 / T2EX Timer 2 external reload /

P1.6 / CLKOUT System clock output
P1.7 / T2 Counter 2 input

compare 0 output /
capture 0 input

compare 1 output /
capture 1 input

compare 2 output /
capture 2 input

compare 3 output /
capture 3 input
Interrupt 2 input

trigger input

V

CC

32, 33 – Supply Voltage

during normal, idle, and power down mode.

V

SS

34, 35 – Ground (0V)

during normal, idle, and power down operation.

*) I = Input

O = Output

Semiconductor Group 9 1997-10-01

Table 1
Pin Definitions and Functions (cont’d)

C515A

Symbol Pin Number

I/O*) Function

(P-MQFP-80)

XTAL2 36 – XTAL2

Input to the inverting oscillator amplifier and input to the
internal clock generator circuits. To drive the device
from an external clock source, XTAL2 should be driven,
while XTAL1 is left unconnected. Minimum and
maximum high and low times as well as rise/fall times
specified in the AC characteristics must be observed.

XTAL1 37 – XTAL1

Output of the inverting oscillator amplifier.

P2.0-P2.7 38-45 I/O Port 2

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 2 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 2 pins being
externally pulled low will source current (I
characteristics) because of the internal pullup resistors.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses strong
internal pullup resistors when issuing 1's. During
accesses to external data memory that use 8-bit
addresses (MOVX @Ri), port 2 issues the contents of
the P2 special function register.

, in the DC

IL

PSEN

47 O The Program Store Enable

output is a control signal that enables the external
program memory to the bus during external fetch
operations. It is activated every six oscillator periods,
except during external data memory accesses. The
signal remains high during internal program execution.

ALE 48 O The Address Latch Enable

output is used for latching the address into external
memory during normal operation. It is activated every
six oscillator periods, except during an external data
memory access. ALE can be switched off when the
program is executed internally.

*) I = Input

O = Output

Semiconductor Group 10 1997-10-01

Table 1
Pin Definitions and Functions (cont’d)

C515A

Symbol Pin Number

I/O*) Function

(P-MQFP-80)

EA 49 I External Access Enable

When held high, the C515A executes instructions from
the internal ROM (C515A-4R) as long as the PC is less
than 8000H. When held low, the C515A fetches all
instructions from external program memory. For the
C515A-L this pin must be tied low.

P0.0-P0.7 52-59 I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins
that have 1's written to them float, and in that state can
be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and data
memory. In this application it uses strong internal pullup
resistors when issuing 1's. Port 0 also outputs the code
bytes during program verification in the C515A-4R.
External pullup resistors are required during program
verification.

P5.0-P5.7 67-60 I/O Port 5

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 5 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that
state can be used as inputs. As inputs, port 5 pins being
externally pulled low will source current (I IL, in the DC
characteristics) because of the internal pullup resistors.

HWPD

69 I Hardware Power Down

A low level on this pin for the duration of one machine
cycle while the oscillator is running resets the C515A. A
low level for a longer period will force the C515A into
Hardware Power Down Mode with the pins floating.

N.C. 2, 13, 14, 23,

46, 50, 51, 68,
70, 71

*) I = Input

O = Output

– Not connected

These pins of the P-MQFP-80 package need not be
connected.

Semiconductor Group 11 1997-10-01

C515A

XTAl1
XTAL2
ALE
PSEN
EA
PE / SWD
RESET
HWPD

Oscillator

Watchdog

OSC & Timing

CPU

Programmable

Watchdog Timer

Timer 0

Timer 1

Timer 2

USART

Baud Rate

Generator

RAM XRAM

256 x 8

1 K x 8 32 K x 8

ROM

Emulation

Support

Logic

Port 0

Port 1

Port 2

Port 3

Port 4

Port 0
8-Bit Digit. I / O

Port 1
8-Bit Digit. I / O

Port 2
8-Bit Digit. I / O

Port 3
8-Bit Digit. I / O

Port 4
8-Bit Digit. I / O

V

AREF

V

AGND

Interrupt

Unit

A/D Converter

10-Bit

S&H

Analog

MUX

Port 5

Port 6

C515A

Port 5
8-Bit Digit. I / O

Port 6
8-Bit Analog /
Digital Input

MCB03242

Figure 4
Block Diagram of the C515A

Semiconductor Group 12 1997-10-01

C515A

CPU

The C515A is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15%
three-byte instructions. With a 18 MHz crystal, 58% of the instructions are executed in 666 ns
(24 MHz : 500 ns).

Special Function Register PSW (Address D0H) Reset Value : 00H

Bit No. MSB LSB

H

D7

CY AC

H

D6

H

D5

F0

H

D4

RS1 RS0 OV F1 PD0

Bit Function

CY Carry Flag

Used by arithmetic instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations.
F0 General Purpose Flag
RS1

RS0

Register Bank select control bits

These bits are used to select one of the four register banks.

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07
0 1 Bank 1 selected, data address 08H-0F
1 0 Bank 2 selected, data address 10H-17
1 1 Bank 3 selected, data address 18H-1F

H

D3

H

D2

H

D1

H

D0

H

PSW

H

H

H

H

OV Overflow Flag

Used by arithmetic instruction.
F1 General Purpose Flag
P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of “one” bits in the accumulator, i.e. even parity.

Semiconductor Group 13 1997-10-01

Memory Organization

The C515A CPU manipulates operands in the following five address spaces:

– up to 64 Kbyte of program memory (32K on-chip program memory for C515A-4R)
– up to 64 Kbyte of external data memory
– 256 bytes of internal data memory
– 1K bytes of internal XRAM data memory
– a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C515A.

Alternatively

C515A

Ext.

FFFF

H

Ext.

Data

Memory

Internal

XRAM

(1 KByte)

FBFF

H

FFFF

FC00

H

H

Indirect

8000

H

7FFF

H

Ext.

Addr.

Internal

RAM

Data

Memory

Int.

EA = 1)

Ext.

EA = 1)

Internal

RAM

0000

H

0000

H

"Code Space" "Data Space" "Internal Data Space"

Direct

Addr.

Special

Function

Regs.

7F

H

00

H

MCB03243

FF

80

H

H

Figure 5
C515A Memory Map

Semiconductor Group 14 1997-10-01

C515A

Reset and System Clock

The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the
oscillator is running. A pullup resistor is internally connected to VCC to allow a power-up reset with
an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting
the RESET pin to VSS via a capacitor. Figure 6 shows the possible reset circuitries.

Figure 6
Reset Circuitries

Semiconductor Group 15 1997-10-01

C515A

Figure 7 shows the recommended oscillator circuitries for crystal and external clock operation.

Crystal Oscillator Mode Driving from External Source

C

3.5 - 24
MHz

C

Crystal Mode: C = 20 pF 10 pF

(Incl. Stray Capacitance)

Figure 7
Recommended Oscillator Circuitries

XTAL1

XTAL2

N.C.

External Oscillator
Signal

XTAL1

XTAL2

MCS03245

Semiconductor Group 16 1997-10-01

C515A

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.

1)

The Enhanced Hooks Technology
together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.

TM

, which requires embedded logic in the C500 allows the C500

SYSCON

PCON
TCON

opt.

I/O Ports

C500
MCU

RESET

EA

ALE

PSEN
Port 0

Port 2

Port 1Port 3

Target System Interface

RPORT RPORT

ICE-System interface

to emulation hardware

RSYSCON

RPCON
RTCON

Enhanced Hooks

Interface Circuit

2

0

EH-IC

TEA TALE TPSEN

MCS03254

Figure 8
Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the program execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.

1 “Enhanced Hooks Technology” is a trademark and patent of Metalink Corporation licensed to Siemens.

Semiconductor Group 17 1997-10-01

C515A

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in
the special function register area. The special function register area consists of two portions: the
standard special function register area and the mapped special function register area. One special
function register of the C515A (PCON1) is located in the mapped special function register area. For
accessing this mapped special function register, bit RMAP in special function register SYSCON
must be set. All other special function registers are located in the standard special function register
area which is accessed when RMAP is cleared (“0“).

Special Function Register SYSCON (Address B1H) Reset Value : XX10XX01

Bit No. MSB LSB

76543210

B1

H

Bit Function

RMAP Special function register map bit

– Reserved bits for future use. Read by CPU returns undefined values.

As long as bit RMAP is set, the mapped special function register area (SFR PCON1) can be
accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped
registers are to be accessed, the bit RMAP must be cleared/set respectively by software.

––

The functions of the shaded bits are not described in this section.

RMAP = 0: The access to the non-mapped (standard) special function

RMAP = 1: The access to the mapped special function register area (SFR

EALE RMAP –

register area is enabled.

PCON1) is enabled.

–

XMAP1

XMAP0

SYSCON

B

The 49 special function registers (SFRs) in the standard and mapped SFR area include pointers
and registers that provide an interface between the CPU and the other on-chip peripherals. All
SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, …, F8H, FFH) are
bitaddressable. The SFRs of the C515A are listed in table 2 and table 3. In table 2 they are
organized in groups which refer to the functional blocks of the C515A. Table 3 illustrates the
contents of the SFRs in numeric order of their addresses.

Semiconductor Group 18 1997-10-01

C515A

Table 2
Special Function Registers - Functional Blocks

Block Symbol Name Address Contents after

Reset

CPU ACC

B
DPH
DPL
PSW
SP

SYSCON

A/D­Converter

ADCON0
ADCON1
ADDATH
ADDATL

Interrupt
System

IEN0
IEN1

2)

IP0

2)

IP1

2)

2)

IRCON
TCON
T2CON

2)

Timer 0/
Timer 1

SCON
TCON

TH0
TH1
TL0
TL1
TMOD

Compare/
Capture
Unit /
Timer 2

CCEN
CCH1
CCH2
CCH3
CCL1
CCL2
CCL3
CRCH
CRCL
TH2
TL2
T2CON

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X” means that the value is undefined and the location is reserved

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Program Status Word Register
Stack Pointer

2)

System/XRAM Control Register

2)

A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Register, High Byte
A/D Converter Data Register, low Byte

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
Interrupt Request Control Register

2)

Timer Control Register

2)

Timer 2 Control Register
Serial Channel Control Register

2)

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

Comp./Capture Enable Reg.
Comp./Capture Reg. 1, High Byte
Comp./Capture Reg. 2, High Byte
Comp./Capture Reg. 3, High Byte
Comp./Capture Reg. 1, Low Byte
Comp./Capture Reg. 2, Low Byte
Comp./Capture Reg. 3, Low Byte
Com./Rel./Capt. Reg. High Byte
Com./Rel./Capt. Reg. Low Byte
Timer 2, High Byte
Timer 2, Low Byte

2)

Timer 2 Control Register

E0
F0

83
82

D0

81
B1

D8

DC
D9
DA

A8
B8

A9
B9

C0
88
C8
98

88

8C
8D
8A
8B
89

C1
C3
C5
C7
C2
C4
C6
CB
CA
CD
CC

C8

H

H
H

H

H

H
H

H

H

H

H

H

H

H

H
H

H
H

H

H

H
H
H
H

H
H
H
H
H
H
H

H
H
H
H

H

H

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

4)

00

H

00

H

00

H

00

H

00

H

07

H

XX10 XX01
00

H

0XXX X000
00

H

00XX XXXX
00

H

00

H

00

H

XX00 0000
00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

3)

B

3)

B

3)

B

3)

B

Semiconductor Group 19 1997-10-01

C515A

Table 2
Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

Ports P0

P1
P2
P3
P4
P5
P6

XRAM XPAGE

SYSCON

Serial
Channel

ADCON0
PCON
SBUF
SCON
SRELL
SRELH

IEN1

2))

IP0

2)

IP1

2)

2)

Watchdog IEN0

WDTREL

Power
Saving

PCON
PCON1

Modes

Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6, Analog/Digital Input

Page Address Register for Extended
On-Chip RAM

2)

System/XRAM Control Register

2)

A/D Converter Control Register

2)

Power Control Register
Serial Channel Buffer Register

2)

Serial Channel Control Register
Serial Channel Reload Register, Low Byte
Serial Channel Reload Register, High Byte

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Priority Register 0
Interrupt Priority Register 1
Watchdog Timer Reload Register

2)

Power Control Register

4)

Power Control Register 1

80
90
A0
B0
E8
F8

DB
91

B1

D8

87
99

98

AA
BA

A8
B8

A9
B9
86

87
88

H
H

H

H

H
H

H

H
H

H

H
H
H

H

H

H
H

H
H

H

H
H

1)

1)

1)
1

1)

1)

1

1)

1)

1)

FF

H

FF

H

FF

H

FF

H

FF

H

FF

H

–
00

H

XX10 XX01
00

H

00

H

3)

XX

H

00

H

D9

H

XXXX XX11
00

H

00

H

00

H

XX00 0000
00

H

00

H

0XXX XXXX

3)

3)

B

3)

B

3)

B

B

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) “X” means that the value is undefined and the location is reserved.

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Semiconductor Group 20 1997-10-01

Table 3
Contents of the SFRs, SFRs in numeric order of their addresses

C515A

Addr Register Content

after
Reset

2)

80
81
82
83
86

87
88
88

P0 FF

H

SP 07

H

DPL 00

H

DPH 00

H

WDTREL 00

H

PCON 00

H

2)

TCON 00

H

3)

PCON1 0XXX-

H

XXXX

89

TMOD 00

H

8AHTL0 00
8BHTL1 00
8CHTH0 00
8DHTH1 00

2)

90

P1 FF

H

1)

H
H
H
H
H

H
H

B
H
H
H
H
H

H

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
WDT

.6 .5 .4 .3 .2 .1 .0

PSEL
SMOD PDS IDLS SD GF1 GF0 PDE IDLE
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
EWPD – – – – – – –

GATE C/T

M1 M0 GATE C/T M1 M0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
T2 CLK-

T2EX INT2 INT6 INT5 INT4 INT3

OUT
91
98
99
A0
A8
A9HIP0 00
AAHSRELL D9
B0
B1HSYSCON XX10-

B8
B9HIP1 XX00-

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

XPAGE 00

H

2)

SCON 00

H

SBUF XX

H

2)

P2 FF

H

2)

IEN0 00

H

2)

P3 FF

H

2)

IEN1 00

H

H
H

H

H
H
H

H

H

XX01

H

0000

.7 .6 .5 .4 .3 .2 .1 .0
SM0 SM1 SM2 REN TB8 RB8 TI RI
T2 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
EAL WDT ET2 ES ET1 EX1 ET0 EX0
OWDS WDTS .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
RD WR T1 T0 INT1 INT0 TxD RxD
– – EALE RMAP – – XMAP1 XMAP0

B

EXEN2 SWDT EX6 EX5 EX4 EX3 EX2 EADC
– – .5.4.3.2.1.0

B

Semiconductor Group 21 1997-10-01

Table 3
Contents of the SFRs, SFRs in numeric order of their addresses (cont’d)

C515A

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H
H

1)

––––––.1.0

B

EXF2 TF2 IEX6 IEX5 IEX4 IEX3 IEX2 IADC
COCAH3COCAL3COCAH2COCAL2COCAH1COCAL1COCAH0COCAL

Reset

BAHSRELH XXXX-

XX11

2)

C0

IRCON 00

H

C1HCCEN 00

0
C2HCCL1 00
C3HCCH1 00
C4HCCL2 00
C5HCCH2 00
C6HCCL3 00
C7HCCH3 00

2)

C8

T2CON 00

H

CAHCRCL 00
CBHCRCH 00
CCHTL2 00
CDHTH2 00

2)

D0
D8

PSW 00

H

2)

ADCON0 00

H

D9HADDATH 00

H
H
H
H
H
H
H
H
H
H
H
H
H
H

DAHADDATL 00XX-

XXXX

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
T2PS I3FR I2FR T2R1 T2R0 T2CM T2I1 T2I0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
CY AC F0 RS1 RS0 OV F1 P
BD CLK ADEX BSY ADM MX2 MX1 MX0
.9 .8 .7 .6 .5 .4 .3 .2
.1.0––––––

B

DBHP6 – .7.6.5.4.3.2.1.0
DCHADCON1 0XXX-

X000

2)

E0
E8
F0
F8

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

ACC 00

H

2)

P4 00

H

2)

B 00

H

2)

P5 FF

H

H
H
H

H

ADCL ––––MX2MX1MX0

B

.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0
.7 .6 .5 .4 .3 .2 .1 .0

Semiconductor Group 22 1997-10-01

C515A

Digital I/O Ports

The C515A allows for digital I/O on 48 lines grouped into 6 bidirectional 8-bit ports. Each port bit
consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0
through P5 are performed via their corresponding special function registers P0 to P5.

The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external
memory. In this application, port 0 outputs the low byte of the external memory address, time­multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory
address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR
contents.

Analog Input Ports

Ports 6 is available as input port only and provides two functions. When used as digital inputs, the
corresponding SFR P6 contains the digital value applied to the port 6 lines. When used for analog
inputs the desired analog channel is selected by a three-bit field in SFR ADCON0. Of course, it
makes no sense to output a value to these input-only ports by writing to the SFR P6. This will have
no effect.

If a digital value is to be read, the voltage levels are to be held within the input voltage specifications
(VIL/VIH). Since P6 is not bit-addressable, all input lines of P6 are read at the same time by byte
instructions.

Nevertheless, it is possible to use port 6 simultaneously for analog and digital input. However, care
must be taken that all bits of P6 that have an undetermined value caused by their analog function
are masked.

Semiconductor Group 23 1997-10-01

Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4:
Table 4

Timer/Counter 0 and 1 Operating Modes
Mode Description TMOD Input Clock

M1 M0 internal external (max)

C515A

0 8-bit timer/counter with a

00

f

OSC/12x32

f

OSC/24x32

divide-by-32 prescaler
1 16-bit timer/counter 1 1
2 8-bit timer/counter with

8-bit autoreload
3 Timer/counter 0 used as one

10

11

f

OSC/12

f

OSC/24

8-bit timer/counter and one

8-bit timer

Timer 1 stops

In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is f

OSC

/12.

In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is f

/24. External inputs INT0 and INT1 (P3.2, P3.3) can be

OSC

programmed to function as a gate to facilitate pulse width measurements. Figure 9 illustrates the
input clock logic.

f

/12

OSC

Timer 0/1
Input Clock

P3.4/T0
P3.5/T1
max

P3.2/INT0
P3.3/INT1

f

OSC

/24

f

OSC

TR 0/1
TCON

Gate

TMOD

=1

÷

12

C/T

TMOD

0

1

Control

&

_

<

1

MCS01768

Figure 9
Timer/Counter 0 and 1 Input Clock Logic

Semiconductor Group 24 1997-10-01

C515A

Timer/Counter 2 with Compare/Capture/Reload

The timer 2 of the C515A provides additional compare/capture/reload features. which allow the
selection of the following operating modes:

– Compare : up to 4 PWM signals with 16-bit/500 ns resolution
– Capture : up to 4 high speed capture inputs with 500 ns resolution
– Reload : modulation of timer 2 cycle time

The block diagram in figure 10 shows the general configuration of timer 2 with the additional
compare/capture/reload registers. The I/O pins which can used for timer 2 control are located as
multifunctional port functions at port 1.

P1.5/
T2EX

P1.7/
T2

OSC

Sync.

T2I0

T2I1

Sync.

&

÷ 12

f

OSC

÷ 24

T2PS

Bit16 16 Bit 16 Bit 16 Bit

Comparator

Comparator

Comparator

EXEN2

Reload

EXF2

Reload

Timer 2

TH2TL2

Compare

Comparator

Capture

_

<

1

TF2

Input/

Output

Control

Interrupt
Request

P1.0/
INT3/
CC0

P1.1/
INT4/
CC1

P1.2/
INT5/
CC2

P1.2/
INT6/

CCL3/CCH3

CCL2/CCH2

CCL1/CCH1

CRCL/CRCH

CC3

MCB03205

Figure 10
Timer 2 Block Diagram

Semiconductor Group 25 1997-10-01

C515A

Timer 2 Operating Modes

The timer 2, which is a 16-bit-wide register, can operate as timer, event counter, or gated timer. A
roll-over of the count value in TL2/TH2 from all 1’s to all 0’s sets the timer overflow flag TF2 in SFR
IRCON, which can generate an interrupt. The bits in register T2CON are used to control the timer 2
operation.

Timer Mode: In timer function, the count rate is derived from the oscillator frequency. A prescaler
offers the possibility of selecting a count rate of 1/12 or 1/24 of the oscillator frequency.

Gated Timer Mode: In gated timer function, the external input pin T2 (P1.7) functions as a gate to
the input of timer 2. If T2 is high, the internal clock input is gated to the timer. T2 = 0 stops the
counting procedure. This facilitates pulse width measurements. The external gate signal is sampled
once every machine cycle.

Event Counter Mode: In the event counter function. the timer 2 is incremented in response to a
1-to-0 transition at its corresponding external input pin T2 (P1.7). In this function, the external input
is sampled every machine cycle. Since it takes two machine cycles (24 oscillator periods) to
recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. There are
no restrictions on the duty cycle of the external input signal, but to ensure that a given level is
sampled at least once before it changes, it must be held for at least one full machine cycle.

Reload of Timer 2: Two reload modes are selectable:
In mode 0, when timer 2 rolls over from all 1’s to all 0’s, it not only sets TF2 but also causes the
timer 2 registers to be loaded with the 16-bit value in the CRC register, which is preset by software.
In mode 1, a 16-bit reload from the CRC register is caused by a negative transition at the
corresponding input pin P1.5/T2EX. This transition will also set flag EXF2 if bit EXEN2 in SFR IEN1
has been set.

Semiconductor Group 26 1997-10-01

C515A

Timer 2 Compare Modes

The compare function of a timer/register combination operates as follows: the 16-bit value stored in
a compare or compare/capture register is compared with the contents of the timer register; if the
count value in the timer register matches the stored value, an appropriate output signal is generated
at a corresponding port pin and an interrupt can be generated.

Compare Mode 0
In compare mode 0, upon matching the timer and compare register contents, the output signal

changes from low to high. It goes back to a low level on timer overflow. As long as compare mode 0
is enabled, the appropriate output pin is controlled by the timer circuit only and writing to the port
will have no effect. Figure 11 shows a functional diagram of a port circuit when used in compare
mode 0. The port latch is directly controlled by the timer overflow and compare match signals. The
input line from the internal bus and the write-to-latch line of the port latch are disconnected when
compare mode 0 is enabled.

Compare Register

Circuit

Compare Reg.

16 Bit

Comparator

Bit16

Timer Register

Timer Circuit

Compare
Match

Timer

Overflow

Figure 11
Port Latch in Compare Mode 0

Port Circuit

Internal
Bus

Write to
Latch

S
D

CLK
R

Port

Latch

Read Latch

Q

Q

Read Pin

V

CC

Port

Pin

MCS02661

Semiconductor Group 27 1997-10-01

C515A

Compare Mode 1
If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the

new value will not appear at the output pin until the next compare match occurs. Thus, it can be
choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the
actual pin-level) or should keep its old value at the time when the timer value matches the stored
compare value.

In compare mode 1 (see figure 12) the port circuit consists of two separate latches. One latch
(which acts as a “shadow latch”) can be written under software control, but its value will only be
transferred to the port latch (and thus to the port pin) when a compare match occurs.

Port Circuit

Compare Register

Circuit

Compare Reg.

16 Bit

Comparator

16 Bit

Timer Register

Timer Circuit

Compare
Match

Internal
Bus

Write to
Latch

Figure 12
Compare Function in Compare Mode 1

D

Shadow

Latch

CLK

Read Latch

Q

D

Port

Latch

Read Pin

V

CC

Q

QCLK

Port

Pin

MCS02662

Semiconductor Group 28 1997-10-01

C515A

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three
asynchronous modes) as illustrated in table 5. The possible baudrates can be calculated using the
formulas given in table 5.

Table 5
USART Operating Modes

Mode

SCON Description

SM0 SM1

0 0 0 Shift register mode

Serial data enters and exits through R×D/ T×D outputs the shift
clock; 8-bit are transmitted/received (LSB first); fixed baud rate

1 0 1 8-bit UART, variable baud rate

10 bits are transmitted (through T×D) or received (at R×D)

2 1 0 9-bit UART, fixed baud rate

11 bits are transmitted (through T×D) or received (at R×D)

3 1 1 9-bit UART, variable baud rate

Like mode 2

For clarification some terms regarding the difference between “baud rate clock” and “baud rate”
should be mentioned. In the asynchronous modes the serial interfaces require a clock rate which is
16 times the baud rate for internal synchronization. Therefore, the baud rate generators/timers have
to provide a “baud rate clock” (output signal in figure 13 to the serial interface which - there divided
by 16 - results in the actual “baud rate”. Further, the abbreviation f

refers to the oscillator

OSC

frequency (crystal or external clock operation).
The variable baud rates for modes 1 and 3 of the serial interface can be derived from either timer 1

or a dedicated baud rate generator (see figure 13).

Semiconductor Group 29 1997-10-01

C515A

Figure 13
Block Diagram of Baud Rate Generation for the Serial Interface

Table 6 below lists the values/formulas for the baud rate calculation of the serial interface with its
dependencies of the control bits BD and SMOD.

Table 6
Serial Interface - Baud Rate Dependencies

Serial Interface 0
Operating Modes

Mode 0 (Shift Register) – –
Mode 1 (8-bit UART)

Mode 3 (9-bit UART)

Active Control Bits Baud Rate Calculation

BD SMOD

f

/ 12

OSC

0 X Controlled by timer 1 overflow:

SMOD

(2

× timer 1 overflow rate) / 32

1 X Controlled by baud rate generator

SMOD

(2

× f

OSC

) /

(64 × baud rate generator overflow rate)

Mode 2 (9-bit UART) – 0

1

f

/ 64

OSC

f

/ 32

OSC

Semiconductor Group 30 1997-10-01

C515A

10-Bit A/D Converter

The C515A provides an A/D converter with the following features:

– 8 multiplexed input channels (port 6), which can also be used as digital inputs
– 10-bit resolution
– Single or continuous conversion mode
– Internal or external start-of-conversion trigger capability
– Interrupt request generation after each conversion
– Using successive approximation conversion technique via a capacitor array
– Built-in hidden calibration of offset and linearity errors

The A/D converter operates with a successive approximation technique and uses self calibration
mechanisms for reduction and compensation of offset and linearity errors. The externally applied
reference voltage range has to be held on a fixed value within the specifications. The main
functional blocks of the A/D converter are shown in figure 14.

Semiconductor Group 31 1997-10-01

IEN1 (B8 )

H

C515A

Internal

Bus

Port 6

f

OSC

V

AREF

/2

EXEN2

IRCON (C0 )

EXF2

ADCON1 (DC )

SWDT

H

TF2 IEX4

H

ADCL

ADCON0 (D8 )

BD

H

CLK ADEX BSY

MUX

Clock

Prescaler

8, 4

EX5EX6

IEX5IEX6

S&H

Conversion Clock

Input Clock

f

IN

EX4 EADC

EX3

IEX3

MX2 MX1

ADM MX2 MX1

EX2

IEX2 IADC

MX0

MX0

ADDATH

(D9 )

HH

Single/
Continuous Mode

.2
.3
.4
.5

f

ADC

A/D

Converter

.6
.7
.8

MSB

ADDATL
(DA )

LSB

.1

V

AGND

Start of
conversion

Internal

Bus

P4.0 / ADST

Shaded Bit locations are not used in ADC-functions.

Write to ADDATL

MCB03247

Figure 14
A/D Converter Block Diagram

Semiconductor Group 32 1997-10-01

C515A

Interrupt System

The C515A provides 12 interrupt sources with four priority levels. Five interrupts can be generated
by the on-chip peripherals (timer 0, timer 1, timer 2, A/D converter, and serial interface) and seven
interrupts may be triggered externally (P3.2/INT0, P3.3/INT1, P1.4/INT2, P1.0/INT3, P1.1/INT4,
P1.2/INT5, P1.3/INT6). The wake-up from power-down mode interrupt has a special functionality
which allows to exit from the software power-down mode by a short low pulse at pin P3.2/INT0.

This chapter shows the interrupt structure, the interrupt vectors and the interrupt related special
function registers. Figure 15 and 16 give a general overview of the interrupt sources and illustrate
the request and the control flags which are described in the next sections.

Semiconductor Group 33 1997-10-01

P3.2
INT0

IT0

TCON.0

A / D Converter

Timer 0
Overflow

P1.4 /
NT2

I2FR

T2CON.5

P3.3 /
INT1

IT1

TCON.2

IE0

TCON.1

IADC

IRCON.0

TF0

TCON.5

IEX2

IRCON.1

IE1

TCON.3

EX0

IEN0.0

EADC

IEN1.0

ET0

IEN0.1

EX2

IEN1.1

EX1

IEN0.2

0003

0043

000B

004B

0013

H

H

IP1.0 IP0.0

H

H

IP1.1

H

IP0.1

C515A

Highest
Priority Level

Lowest
Priority Level

P

o

l
l

i
n
g

S

e
q

u
e
n
c
e

P1.0 /
INT3

CC0

I3FR

IEX3

IRCON.2

EX3

IEN1.2

0013

H

IP1.2EAL

IP0.2

T2CON.6

IEN0.7

Bit addressable
Request flag is cleared by hardware

MCB03248

Figure 15
Interrupt Request Sources (Part 1)

Semiconductor Group 34 1997-10-01

Highest
Priority Level

C515A

Timer 1 Overflow

P1.1 /
INT4 /
CC1

USART

P1.2 /
INT5 /
CC2

Timer 2
Overflow

P1.5/
T2EX

EXEN2

P1.3 /

IEN1.7

INT6 /
CC3

Bit addressable
Request flag is cleared by hardware

SCON.0

RI

TI

SCON.1

IRCON.6

TF2

EXF2

IRCON.7

TF1

TCON.7

IEX4

IRCON.3

<1

IEX5

IRCON.4

<1

IEX6

IRCON.5

ET1

IEN0.3

EX4

IEN1.3

ES

IEN0.4

EX5

IEN1.4

ET2

IEN0.5

ET6

IEN1.5

001B

H

005B

H

0023

H

0063

H

002B

H

006B

H

EAL

IEN0.7

IP1.3 IP0.3

IP1.4

IP0.4

IP0.5IP1.5

Lowest
Priority Level

P
o

l
l

i
n
g

S
e
q

u
e
n
c
e

MCB03249

Figure 16
Interrupt Request Sources (Part 2)

Semiconductor Group 35 1997-10-01

C515A

Table 7
Interrupt Source and Vectors

Interrupt Source Interrupt Vector Address Interrupt Request Flags

External Interrupt 0 0003
Timer 0 Overflow 000B
External Interrupt 1 0013
Timer 1 Overflow 001B
Serial Channel 0023
Timer 2 Overflow / Ext. Reload 002B
A/D Converter 0043
External Interrupt 2 004B
External Interrupt 3 0053
External Interrupt 4 005B
External Interrupt 5 0063
External Interrupt 6 006B
Wake-up from power-down mode 007B

H

H

H
H
H
H
H
H
H
H

H

H
H

IE0
TF0
IE1
TF1
RI / TI
TF2 / EXF2
IADC
IEX2
IEX3
IEX4
IEX5
IEX6
–

Semiconductor Group 36 1997-10-01

C515A

Fail Save Mechanisms

The C515A offers enhanced fail safe mechanisms, which allow an automatic recovery from
software upset or hardware failure:

– a programmable watchdog timer (WDT), with variable time-out period from 512 µs up to

approx. 1.1 s at 12 MHz (256 µs up to approx. 0.65 s at 24 MHz)

– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the

microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.

The watchdog timer in the C515A is a 15-bit timer, which is incremented by a count rate of f
up to f

/384. The system clock of the C515A is divided by two prescalers, a divide-by-two and a

OSC

OSC

/24

divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bit of the
watchdog timer can be written. Figure 15 shows the block diagram of the watchdog timer unit.

07

f

/12

OSC

2

16

14

WDTL

8

WDT Reset-Request

WDTH

IP0 (A9 )

- ------

WDTS

H

WDTPSEL

External HW Reset
External HW Power-Down

PE/SWD

670

WDTREL (86 )

H

Control Logic

-

WDT

-

SWDT

-- -- --

-- -- --

IEN0 (A8 )
IEN1 (B8 )

H
H

MCB03250

Figure 17
Block Diagram of the Watchdog Timer

The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD,
but it cannot be stopped during active mode of the C515A. If the software fails to refresh the running
watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the
watchdog timer the content of the SFR WDTREL is transferred to the upper 7-bit of the watchdog
timer. The refresh sequence consists of two consecutive instructions which set the bits WDT and
SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined
by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the
idle mode and power down mode of the processor.

Semiconductor Group 37 1997-10-01

Oscillator Watchdog

The oscillator watchdog unit serves for four functions:

– Monitoring of the on-chip oscillator's function

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency
of the auxiliary RC oscillator in the watchdog unit, the internal clock is supplied by the RC
oscillator and the device is brought into reset; if the failure condition disappears (i.e. the
on-chip oscillator has a higher frequency than the RC oscillator), the part executes a final
reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog
reset is released and the part starts program execution again.

– Fast internal reset after power-on

The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator
has started. The oscillator watchdog unit also works identically to the monitoring function.

– Restart from the hardware power down mode.

If the hardware power down mode is terminated the oscillator watchdog has to control the
correct start-up of the on-chip oscillator and to restart the program. The oscillator watchdog
function is only part of the complete hardware power down sequence; however, the watchdog
works identically to the monitoring function.

– Control of external wake-up from software power-down mode

When the software power-down mode is left by a low level at the P3.2/INT0 pin, the oscillator
watchdog unit assures that the microcontroller resumes operation (execution of the
power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC
oscillator and the on-chip oscillator are stopped. Both oscillators are started again when
power-down mode is released. When the on-chip oscillator has a higher frequency than the
RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to
allow the on-chip oscillator to stabilize.

C515A

Semiconductor Group 38 1997-10-01

C515A

P3.2 / INT0

XTAL1
XTAL2

EWPD

Power-Down

(PCON1.0) Mode Activated

Control

Logic

Start /
Stop

RC

Oscillator

f

RC

3 MHz

Start /
Stop

5

f

1

Frequency

Comparator

f

2

On-Chip

Oscillator

OWDS

2

Power-Down Mode
Wake-Up Interrupt

Control

Logic

<

f

f

2

1

Delay

Internal Reset

>1

IP0 (A9 )

H

Figure 18
Block Diagram of the Oscillator Watchdog

Int. Clock

MCB03251

Semiconductor Group 39 1997-10-01

C515A

Power Saving Modes

The C515A provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock rate
in normal operating mode and it can be also used for further power reduction in idle mode.

– Idle mode

The CPU is gated off from the oscillator. All peripherals are still provided with the clock and
are able to work. Idle mode is entered by software and can be left by an interrupt or reset.

– Slow down mode

The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 8. This slows down all parts of the controller, the CPU and all peripherals,
to 1/8th of their normal operating frequency and also reduces power consumption.

– Software power down mode

The operation of the C515 is completely stopped and the oscillator is turned off. This mode is
used to save the contents of the internal RAM with a very low standby current. This power
down mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/
INT0.

– Hardware Power down mode

If pin HWPD gets active (low level) the part enters the hardware power down mode and starts
a complete internal reset sequence. Thereafter, both oscillators of the chip are stopped and
the port pins and several control lines enter a floating state.

In the power down mode of operation, VCC can be reduced to minimize power consumption. It must
be ensured, however, that VCC is not reduced before the power down mode is invoked, and that V

CC

is restored to its normal operating level, before the power down mode is terminated. Table 8 gives
a general overview of the entry and exit procedures of the power saving modes.

Semiconductor Group 40 1997-10-01

Table 8
Power Saving Modes Overview

C515A

Mode Entering

2-Instruction
Example

Idle mode ORL PCON, #01H

ORL PCON, #20H

Slow Down Mode In normal mode:

ORL PCON,#10H

With idle mode:
ORL PCON,#01H
ORL PCON, #30H

Software
Power Down Mode

Hardware
Power Down Mode

ORL PCON, #02H
ORL PCON, #40H

HWPD = 0 HWPD = 1 Oscillator is stopped; internal

Leaving by Remarks

Occurrence of an
interrupt from a
peripheral unit

Hardware Reset

ANL PCON,#0EFH
or
Hardware Reset

Occurrence of an
interrupt from a
peripheral unit

Hardware reset

Hardware Reset Oscillator is stopped;
Short low pulse at

pin P3.2/INT0

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock

Internal clock rate is reduced
to 1/8 of its nominal frequency

CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with 1/8
of its nominal frequency

contents of on-chip RAM and
SFR’s are maintained;

reset is executed;

Semiconductor Group 41 1997-10-01

C515A

Absolute Maximum Ratings

Ambient temperature under bias (TA) ......................................................... – 40 to + 125 °C

Storage temperature (T

Voltage on VCC pins with respect to ground (VSS) ....................................... – 0.5 V to 6.5 V

Voltage on any pin with respect to ground (VSS)......................................... – 0.5 V to VCC +0.5 V

Input current on any pin during overload condition..................................... – 10 mA to 10 mA

Absolute sum of all input currents during overload condition ..................... I 100 mA I

Power dissipation of package..................................................................... TBD

Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage of the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for longer
periods may affect device reliability. During overload conditions (
Voltage on

V

CC

absolute maximum ratings.

) .......................................................................... – 65 °C to 150 °C

stg

V

>

V

CC

or

pins with respect to ground (

IN

V

) must not exceed the values defined by the

SS

V

<

V

SS

) the

IN

Semiconductor Group 42 1997-10-01

C515A

DC Characteristics

V

= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C515A

CC

T

= – 40 to 85 °C for the SAF-C515A

A

T

= – 40 to 110 °C for the SAH-C515A

A

T

= – 40 to 125 °C for the SAK-C515A

A

Parameter Symbol Limit Values Unit Test Condition

min. max.

Input low voltage
Pins except EA,RESET,HWPD
EA pin
HWPD and RESET pins

Input high voltage
pins except RESET

, XTAL2 and
HWPD
XTAL2 pin
RESET and HWPD pin

Output low voltage
Ports 1, 2, 3, 4, 5
Port 0, ALE, PSEN

Output high voltage
Ports 1, 2, 3, 4, 5

Port 0 in external bus mode,
ALE, PSEN

Logic 0 input current
Ports 1, 2, 3, 4, 5 I

Logical 0-to-1 transition current,
Ports 1, 2, 3, 4, 5

Input leakage current
Port 0 and 6, EA

, HWPD I

Input low current
to RESET for reset
XTAL2
PE/SWD

Pin capacitance

Overload current

V
V
V

V
V
V

V
V

V

V

I

I
I
I

C

I

IL
IL1
IL2

IH
IH1
IH2

OL
OL1

OH

OH1

LI

TL

LI

IL2
IL3
IL4

IO

OV

– 0.5
– 0.5
– 0.5

0.2 VCC + 0.9

0.7 VCC

0.6 V

CC

–
–

2.4

0.9 V

CC

2.4

0.9 V

CC

– 10 – 70 µA V

– 65 – 650 µA V

0.2 VCC – 0.1

0.2 VCC – 0.3

0.2 VCC + 0.1

V

+ 0.5

CC

V

+ 0.5

CC

V

+ 0.5

CC

0.45

0.45

–
–
–
–

V
V
V

V
V
V

V
V

V
V
V
V

–
–
–

–
–
–

I

= 1.6 mA

OL

I

= 3.2 mA

OL

I

= – 80 µA

OH

I

= – 10 µA

OH

I

= – 800 µA

OH

I

= – 80 µA

OH

= 0.45 V

I N

= 2 V

I N

– ± 1 µA 0.45 < V

– 10
–
–

– 10 pF f
– ± 5mA

– 100
– 15
– 20

µA
µA
µA

V

= 0.45 V

IN

V

= 0.45 V

I N

V

= 0.45 V

I N

= 1 MHz,

C

T

= 25 °C

A

8) 9)

1)

1)

2)

< V

I N

CC

2)

Notes see next page

Semiconductor Group 43 1997-10-01

C515A

Power Supply Current
Parameter Symbol Limit Values Unit Test Condition

Active mode 18 MHz

24 MHz

Idle mode 18 MHz

24 MHz

Active mode with
slow-down enabled

Active mode with
slow-down enabled

18 MHz
24 MHz

18 MHz
24 MHz

Power-down mode I

10)

typ.

I

CC

I

CC

I

CC

I

CC

I

CC

I

CC

I

CC

I

CC

PD

16.9

21.7

8.5

11.0

5.6

6.6

3.0

3.3
10 50 µA VCC = 2…5.5 V

max.

23.1

29.4

12.1

15.0

8.0

9.6

4.1

4.7

11)

mA
mA

mA
mA

mA
mA

mA
mA

4)

5)

6)

7)

3)

Notes:

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the

V

OL

of ALE
and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these
pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise
pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger,
or use an address latch with a schmitt-trigger strobe input.

V

2) Capacitive loading on ports 0 and 2 may cause the

V

0.9

3)

I

EA = RESET

V
I

4)

I

XTAL2 driven with
EA = PE
all other pins are disconnected.

5)

I

XTAL2 driven with
RESET

6)

I

disabled; XTAL2 driven with
RESET

specification when the address lines are stabilizing.

CC

(software power-down mode) is measured under following conditions:

PD

= Port 0 = Port 6 = VCC ; XTAL1 = N.C.; XTAL2 = VSS ; PE/SWD = VSS ; HWPD = VCC ;

= VSS ; V

AGND

(hardware power-down mode): independent from any particular pin connection.

PD

(active mode) is measured with:

CC

= VCC ; all other pins are disconnected.

AREF

t

CLCH

, t

= 5 ns , VIL = VSS + 0.5 V, VIH =

CHCL

/SWD = Port 0 = Port 6 = VCC ; HWPD = VCC ; RESET = VSS ;

I

would be slightly higher if a crystal oscillator is used (appr. 1 mA).

CC

(idle mode) is measured with all output pins disconnected and with all peripherals disabled;

CC

t

CLCH

, t

= 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL1 = N.C.;

CHCL

= VCC ; HWPD = Port 0 = Port 6 = VCC ; EA = PE/SWD = VSS ; all other pins are disconnected;

(active mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

CC

t

CLCH

, t

= 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL1 = N.C.;

CHCL

= VCC ; HWPD = Port 6 = VCC ; EA = PE/SWD = VSS ; all other pins are disconnected; the

on ALE and PSEN to momentarily fall below the

OH

V

– 0.5 V; XTAL1 = N.C.;

CC

microcontroller is put into slow-down mode by software;

7)

I

(idle mode with slow-down mode) is measured with all output pins disconnected and with all peripherals

CC

disabled; XTAL2 driven with
RESET

= VCC ; HWPD = Port 6 = VCC ; EA = PE/SWD = VSS ; all other pins are disconnected;

t

CLCH

, t

= 5 ns, VIL = VSS + 0.5 V, VIH = VCC – 0.5 V; XTAL1 = N.C.;

CHCL

the microcontroller is put into idle mode with slow-down mode enabled by software;

8) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin
exceeds the specified range (i.e. VOV > VCC + 0.5 V or VOV < VSS - 0.5 V). The supply voltage VCC and VSS must
remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.

9) Not 100% tested, guaranteed by design characterization

10)The typical

11)The maximum

I

values are periodically measured at T

CC

I

values are measured under worst case conditions (T

CC

= +25 ˚C and V

A

= 5 V but not 100% tested.

CC

= 0 ˚C or -40 ˚C and V

A

= 5.5 V)

CC

Semiconductor Group 44 1997-10-01

C515A

30

mA

Ι

CC

25

20

15

10

5

0

0

Figure 19
ICC Diagram

Ι

CC max

Ι

CC typ

Active Mode

Active Mode

Idle Mode

Active + Slow Down Mode

Idle + Slow Down Mode

4 8 12 16 20

MCD03252

Idle Mode

MHz 24

f

OSC

Table 9
Power Supply Current Calculation Formulas

Parameter Symbol Formula

Active mode

Idle mode

Active mode with
slow-down enabled

Idle mode with
slow-down enabled

Note: f

is the oscillator frequency in MHz. ICC values are given in mA.

osc

I

CC typ

I

CC max

I

CC typ

I

CC max

I

CC typ

I

CC max

I

CC typ

I

CC max

0.79 * f

1.04 * f

0.43 * f

0.48 * f

0.17 * f

0.28 * f

0.06 * f

0.09 * f

OSC
OSC

OSC
OSC

OSC
OSC

OSC
OSC

+ 2.7
+ 4.4

+ 0.7
+ 3.5

+ 2.5
+ 2.9

+ 1.9
+ 2.5

Semiconductor Group 45 1997-10-01

A/D Converter Characteristics

V

= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C515A

CC

T

= – 40 to 85 °C for the SAF-C515A

A

T

= – 40 to 110 °C for the SAH-C515A

A

T

= – 40 to 125 °C for the SAK-C515A

A

C515A

4 V ≤ V

≤ VCC + 0.1 V; VSS – 0.1 V ≤ V

AREF

≤ VSS + 0.2 V

AGND

Parameter Symbol Limit Values Unit Test Condition

min. max.

Analog input voltage

V

Sample time t

Conversion cycle time t

Total unadjusted error
Internal resistance of

TUE

R

reference voltage source
Internal resistance of

R

analog source
ADC input capacitance C

Notes see next page.

AIN

S

ADCC

AREF

ASRC

AIN

V

AGND

– 16 × t

– 96 × t

V

AREF

8 × t

48 × t

V
ns Prescaler ÷ 8

IN

IN

ns Prescaler ÷ 8

IN
IN

– ± 2 LSB VSS + 0.5 V ≤ VIN ≤ VCC – 0.5 V
– t

ADC

/ 250

kΩ

– 1

– tS / 500

kΩ

– 0.8

–50pF

1)

Prescaler ÷ 4

Prescaler ÷ 4

t

in [ns]

ADC

t

in [ns]

S

6)

5) 6)

2) 6)

Clock calculation table:

2)

3)

4)

Clock Prescaler

ADCL t

ADC

Ratio

÷ 8 1 8 ×
÷ 4 0 4 ×

t

Further timing conditions:

min = 500 ns

ADC

t

= 2 / f

IN

tS t

t

IN

t

IN

OSC

16 × tIN 96 × tIN

8 × tIN 48 × tIN

= 2 t

CLCL

ADCC

Semiconductor Group 46 1997-10-01

Notes:

1) V

2) During the sample time the input capacitance C

may exceed V

AIN

AGND

these cases will be X000

or V

or X3FFH, respectively.

H

up to the absolute maximum ratings. However, the conversion result in

AREF

can be charged/discharged by the external source. The

AIN

internal resistance of the analog source must allow the capacitance to reach their final voltage level within t
After the end of the sample time t

, changes of the analog input voltage have no effect on the conversion

S

result.

C515A

S

.

3) This parameter includes the sample time t
calibration. Values for the conversion clock t

, the time for determining the digital result and the time for the

S

depend on programming and can be taken from the table on

ADC

the previous page.

4) T

is tested at V

UE

AREF

= 5.0 V, V

= 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all

AGND

other voltages within the defined voltage range.
If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input
overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB
is permissible.

5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference source must allow the capacitance to reach their final voltage level within the
indicated time. The maximum internal resistance results from the programmed conversion timing.

6) Not 100% tested, but guaranteed by design characterization.

Semiconductor Group 47 1997-10-01

C515A

AC Characteristics (18 MHz)

V

= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C515A

CC

T

= – 40 to 85 °C for the SAF-C515A

A

T

= – 40 to 110 °C for the SAH-C515A

A

T

= – 40 to 125 °C for the SAK-C515A

A

(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Program Memory Characteristics
Parameter Symbol Limit Values Unit

18 MHz

Clock

1/

Variable Clock

t

= 3.5 MHz to 18 MHz

CLCL

min. max. min. max.

ALE pulse width t
Address setup to ALE
Address hold after ALE
ALE low to valid instruction in
ALE to PSEN
PSEN pulse width
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instr in
Address float to PSEN

*)

Interfacing the C515A to devices with float times up to 48 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

PXAV

t

AVIV

t

AZPL

*)

71 – 2 t
26 – t
26 – t
– 122 – 4 t
31 – t
132 – 3 t
–92– 3 t

– 40 – ns

CLCL

– 30 – ns

CLCL

– 30 – ns

CLCL

– 100 ns

CLCL

– 25 – ns

CLCL

– 35 – ns

CLCL

– 75 ns

CLCL

0–0–ns
–46– t

*)

48 – t

– 8 – ns

CLCL

– 180 – 5 t

– 10 ns

CLCL

– 98 ns

CLCL

0–0–ns

Semiconductor Group 48 1997-10-01

C515A

AC Characteristics (18 MHz, cont’d)
External Data Memory Characteristics

Parameter Symbol Limit Values Unit

RD pulse width
WR pulse width
Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD

t

RLRH

t

WLWH

t

LLAX2

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

WHLH

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

18 MHz

Clock

1/

Variable Clock

t

= 3.5 MHz to 18 MHz

CLCL

min. max. min. max.

233 – 6 t
233 – 6 t
81 – 2 t
– 128 – 5 t

– 100 – ns

CLCL

– 100 – ns

CLCL

– 30 – ns

CLCL

– 150 ns

CLCL

0–0–ns
–51– 2 t
– 294 – 8 t
– 335 – 9 t
117 217 3 t
92 – 4 t
16 96 t
11 – t
239 – 7 t
16 – t

– 50 3 t

CLCL

– 130 – ns

CLCL

– 40 t

CLCL

– 45 – ns

CLCL

– 150 – ns

CLCL

– 40 – ns

CLCL

– 60 ns

CLCL

– 150 ns

CLCL

– 165 ns

CLCL

+ 50 ns

CLCL

+ 40 ns

CLCL

–0–0ns

External Clock Drive Characteristics
Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 3.5 MHz to 18 MHz

min. max.

Oscillator period t
High time
Low time
Rise time
Fall time

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

55.6 285.7 ns
15 t
15 t

CLCL

CLCL

– t
– t

CLCX

CHCX

ns

ns
–15ns
–15ns

Semiconductor Group 49 1997-10-01

C515A

AC Characteristics (24 MHz)

V

= 5 V + 10%, – 15%; VSS = 0 V TA = 0 to 70 °C for the SAB-C515A

CC

T

= – 40 to 85 °C for the SAF-C515A

A

T

= – 40 to 110 °C for the SAH-C515A

A

(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Program Memory Characteristics
Parameter Symbol Limit Values Unit

24 MHz

Clock

1/

Variable Clock

t

= 3.5 MHz to 24 MHz

CLCL

min. max. min. max.

ALE pulse width t
Address setup to ALE
Address hold after ALE
ALE low to valid instruction in
ALE to PSEN
PSEN pulse width
PSEN to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address valid after PSEN
Address to valid instr in
Address float to PSEN

*)

Interfacing the C515A to devices with float times up to 37 ns is permissible. This limited bus contention will not
cause any damage to port 0 drivers.

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

PXAV

t

AVIV

t

AZPL

*)

43 – 2 t
17 – t
17 – t
–80– 4 t
22 – t
95 – 3t
–60– 3 t

– 40 – ns

CLCL

– 25 – ns

CLCL

– 25 – ns

CLCL

– 87 ns

CLCL

– 20 – ns

CLCL

– 30 – ns

CLCL

– 65 ns

CLCL

0–0–ns
–32– t

*)

37 – t

– 5 – ns

CLCL

– 148 – 5 t

– 10 ns

CLCL

– 60 ns

CLCL

0–0–ns

Semiconductor Group 50 1997-10-01

C515A

AC Characteristics (24 MHz, cont’d)
External Data Memory Characteristics

Parameter Symbol Limit Values Unit

RD pulse width
WR pulse width
Address hold after ALE
RD to valid data in
Data hold after RD
Data float after RD
ALE to valid data in
Address to valid data in
ALE to WR or RD
Address valid to WR or RD
WR or RD high to ALE high
Data valid to WR transition
Data setup before WR
Data hold after WR
Address float after RD

t

RLRH

t

WLWH

t

LLAX2

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

WHLH

t

QVWX

t

QVWH

t

WHQX

t

RLAZ

24 MHz

Clock

1/

Variable Clock

t

= 3.5 MHz to 24 MHz

CLCL

min. max. min. max.

180 – 6 t
180 – 6 t
56 – 2 t
– 118 – 5 t

– 70 – ns

CLCL

– 70 – ns

CLCL

– 27 – ns

CLCL

– 90 ns

CLCL

0–0–ns
–63– 2 t
– 200 – 8 t
– 220 – 9 t
75 175 3 t
67 – 4 t
17 67 t
5–t
170 – 7 t
15 – t

– 50 3 t

CLCL

– 97 – ns

CLCL

– 25 t

CLCL

– 37 – ns

CLCL

– 122 – ns

CLCL

– 27 – ns

CLCL

– 20 ns

CLCL

– 133 ns

CLCL

– 155 ns

CLCL

+ 50 ns

CLCL

+ 25 ns

CLCL

–0–0ns

External Clock Drive Characteristics
Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 3.5 MHz to 24 MHz

min. max.

Oscillator period t
High time
Low time
Rise time
Fall time

CLCL

t

CHCX

t

CLCX

t

CLCH

t

CHCL

41.7 285.7 ns
12 t
12 t

CLCL

CLCL

– t
– t

CLCX

CHCX

ns

ns
–12ns
–12ns

Semiconductor Group 51 1997-10-01

ALE

t

C515A

LHLL

PSEN

Port 0

Port 2

t

AVLL PLPH

t

LLIV

t

t

PLIV

t

AZPL

t

LLAX

t

LLPL

t

t

PXAV

t

PXIZ

PXIX

A0 - A7 Instr.IN A0 - A7

t

AVIV

A8 - A15 A8 - A15

MCT00096

Figure 20
Program Memory Read Cycle

Semiconductor Group 52 1997-10-01

ALE

PSEN

RD

t

LLWL

t

LLDV

t

RLDV

t

RLRH

t

WHLH

C515A

t

AVLL

Port 0

A0 - A7 from

Ri or DPL from PCL

t

AVWL

Port 2

Figure 21
Data Memory Read Cycle

t

LLAX2

t

AVDV

t

RLAZ

Data IN

t

RHDZ

t

RHDX

A0 - A7 Instr.

A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

IN

MCT00097

Semiconductor Group 53 1997-10-01

ALE

PSEN

t

WHLH

C515A

WR

t

AVLL

t

Port 0

A0 - A7 from

Ri or DPL from PCL

t

AVWL

Port 2

Figure 22
Data Memory Write Cycle

t

LLWL

LLAX2

t

QVWX

t

WLWH

t

QVWH

Data OUT

t

WHQX

A0 - A7

A8 - A15 from PCHP2.0 - P2.7 or A8 - A15 from DPH

Instr.IN

MCT00098

t

CLCL

V

- 0.5V

CC

0.45V

0.2

0.7

V

CC

V

CC

- 0.1

t

CHCL

t

CLCX

t

CLCH

t

CHCX

MCT00033

Figure 23
External Clock Drive on XTAL2

Semiconductor Group 54 1997-10-01

C515A

ROM Verification Characteristics for the C515A-1RM
ROM Verification Mode 1

Parameter Symbol Limit Values Unit

min. max.

Address to valid data

P1.0-P1.7
P2.0-P2.6

Port 0

Data:
Addresses:

t

AVQV

Address New Address

Data Out

P0.0-P0.7
P1.0-P1.7
P2.0-P2.6

=

D0-D7

=

A0-A7

=

A8-A14

–

t

AVQV

10 t

ns

CLCL

New Data Out

PSENInputs:
ALE, EA
RESET =

=

V

SS

=

V

IH

V

IL2

MCS03253

Figure 24
ROM Verification Mode 1

Semiconductor Group 55 1997-10-01

C515A

ROM Verification Mode 2
Parameter Symbol Limit Values Unit

min. typ max.

ALE pulse width
ALE period

Data valid after ALE
Data stable after ALE
P3.5 setup to ALE low
Oscillator frequency

ALE

Port 0

t

AWD

t

AS

t

DVA

t

AWD

t

ACY

t

DVA

t

DSA

t

AS

1/

t

CLCL

t

DSA

–

2 t

– 12 t
––4 t
8 t

––ns

CLCL

– t

CLCL

–ns

CLCL

–ns

CLCL

–

CLCL

ns

3.5 – 24 MHz

t

ACY

Data Valid

ns

P3.5

Figure 25
ROM Verification Mode 2

MCT02613

Semiconductor Group 56 1997-10-01

V

-0.5 V

CC

V

+0.90.2

CC

Test Points

V

0.2 -0.1

CC

0.45 V

MCT00039

AC Inputs during testing are driven at VCC - 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’.
Timing measurements are made at V

for a logic ’1’ and V

IHmin

for a logic ’0’.

ILmax

Figure 26
AC Testing: Input, Output Waveforms

C515A

-0.1 V

V

OH

V

+0.1 V

OL

MCT00038

V

Load

V

V

Load

Load

+0.1 V

Timing Reference

Points

-0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage
occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.

I

OL/IOH

≥ ± 20 mA

Figure 27
AC Testing : Float Waveforms

Crystal Oscillator Mode Driving from External Source

C

XTAL1

N.C.

XTAL1

3.5 - 24
MHz

External Oscillator
Signal

XTAL2

XTAL2

C

Crystal Mode: C = 20 pF 10 pF

(Incl. Stray Capacitance)

MCS03245

Figure 28
Recommended Oscillator Circuits for Crystal Oscillator

Semiconductor Group 57 1997-10-01

Plastic Package, P-MQFP-80-1 (SMD)

(Plastic Metric Quad Flat Package)

C515A

Figure 29
P-MQFP-80-1 Package Outline

Sorts of Packing

Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”

SMD = Surface Mounted Device

GPM05249

Dimensions in mm

Semiconductor Group 58 1997-10-01