Datasheet SAB-C504-2R24M, SAB-C504-2R40M, SAB-C504-2RM, SAB-C504-L24M, SAB-C504-L40M Datasheet (Siemens)

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Data Sheet 05.96

Microcomputer Components

C504

8-Bit CMOS Microcontroller

Page 2

C504 Revision History: Current Version: 05.96

Previous Version: Page

(in previous Version)

Page (in new Version)

Subjects (major changes since last revision)

Edition 05.96

This edition was realized using the software system FrameMaker

Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München



Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer.

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Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express

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8-Bit CMOS Microcontroller C504

Advance Information

• Fully compatible to standard 8051 microcontroller

• Up to 40 MHz operating frequency

• 16 K×8 ROM (C504-2R only, optional ROM protection)

• 256×8 RAM

• 256×8 XRAM

• Four 8-bit ports, (2 ports with mixed analog/digital I/O capability)

• Three 16-bit timers/counters (timer 2 with up/down counter feature)

• Capture/compare unit for PWM signal generation and signal capturing

- 3-channel, 16-bit capture/compare unit

- 1-channel, 10-bit compare unit

• Compare unit

• USART

• 10-bit A/D Converter with 8 multiplexed inputs

• Twelve interrupt sources with two priority levels

• On-chip emulation support logic (Enhanced Hooks Technology

)

• Programmable 15-bit Watchdog Timer

• Oscillator Watchdog

• Fast Power On Reset

• Power Saving Modes

• M-QFP-44 package

• Temperature ranges: SAB-C504 T

SAF-C504 TA : – 40 to 85°C SAH-C504 TA : – 40 to 110°C (max. operating frequency.: TBD) SAK-C504 TA : – 40 to 125°C (max. operating frequency.: 12 MHz)

: 0 to 70°C

Semiconductor Group 3 05.96

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C504

The C504 with its capture compare unit (CCU) especially provides a functionality, which allows to use the microcontroller in motor control applications. Further, the C504 is functionally upward compatible with the SAB 80C52/C501 microcontroller and can replace it in existing applications. The C504-2R contains a non-volatile 16K×8 read-only program memory, a volatile on-chip 512×8 read/write data memory, four 8-bit wide ports, three 16-bit timers/counters, a 16-bit capture/ compare unit with compare timer, a 10-bit compare timer, a twelve source, two priority level interrupt structure, a serial port, versatile fail save mechanisms, on-chip emulation support logic, and a genuine 10-bit A/D converter. The C504-L is identical to the C504-2R, except that it lacks the program memory on chip. Therefore, the term C504 refers to all versions within this data sheet unless otherwise noted.

Ordering Information Type Ordering Code Package Description

(8-Bit CMOS microcontroller)

SAB-C504-LM Q67120-C1048 P-MQFP-44 for external memory (12 MHz) SAB-C504-L24M Q67120-C1049 P-MQFP-44 for external memory (24 MHz) SAB-C504-L40M Q67120-C1050 P-MQFP-44 for external memory (40 MHz) SAB-C504-2RM Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (12 MHz) SAB-C504-2R24M Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (24 MHz) SAB-C504-2R40M Q67120-DXXXX P-MQFP-44 with mask-programmable ROM (40 MHz)

Note: Versions for extended temperature ranges – 40 ˚C to 110 ˚C (SAH-C504) and – 40 ˚C to

125 ˚C (SAK-C504) are available on request. The ordering number of ROM types (DXXXX extensions) is defined after program release (verification) of the customer.

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C504

Figure 1 Logic Symbol

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C504

Figure 2 Pin Configuration (top view)

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Table 1 Pin Definitions and Functions

C504

Symbol Pin Number

(P-MQFP-44)

P1.0-P1.7 40-44,

1-3

I/O

Function

I/O Port 1

is an 8-bit bidirectional port. Port pins can be used for digital input/output. P1.0 - P1.3 can also be used as analog inputs of the A/D-converter. As secondary digital functions, port 1 contains the timer 2 pins and the capture/compare inputs/outputs. Port 1 pins are assigned to be used as analog inputs via the register P1ANA. The functions are assigned to the pins of port 1 as follows: P1.0 / AN0 / T2 Analog input channel 0 /

P1.1 / AN1 / T2EX Analog input channel 1 /

P1.2 / AN2 / CC0 Analog input channel 2 /

P1.3 / AN3 / COUT0 Analog input channel 3 /

P1.4 / CC1 Input/output of capture/compare

P1.5 / COUT1 Output of capture/compare

P1.6 / CC2 Input/output of capture/compare

P1.7 / COUT2 Output of capture/compare

input to counter 2

capture/reload trigger of timer 2 / up-down count

input/output of capture/compare channel 0

output of capture/compare channel 0

channel 1

channel 2

RESET 4 I RESET

A high level on this pin for one machine cycle while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VCC.

*) I = Input

O = Output

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Table 1 Pin Definitions and Functions (cont’d)

C504

Symbol Pin Number

(P-MQFP-44)

P3.0-P3.7 5, 7-13

I/O

Function

I/O Port 3

is an 8-bit bidirectional port. P3.0 (R×D) and P3.1 (T×D) operate as defined for the C501. P3.2 to P3.7 contain the external interrupt inputs, timer inputs, input and as an additional optinal function four of the analog inputs of the A/D-converter. Port 3 pins are assigned to be used as analog inputs via the bits of SFR P3ANA. P3.6/WR can be assigned as a third interrupt input. The functions are assigned to the pins of port 3 as follows: P3.0 / RxD Receiver data input (asynch.) or data

P3.1 / TxD Transmitter data output (asynch.) or

P3.2 / AN4 / INT0 Analog input channel 4 / external

P3.3 / AN5 / INT1 Analog input channel 5 / external

P3.4 / AN6 / T0 Analog input channel 6 / timer 0

P3.5 / AN7 / T1 Analog input channel 7 / timer 1

P3.6 / WR / INT2 WR control output; latches the data

P3.7 / RD RD control output; enables the

input/output (synch.) of serial interface

clock output (synch.) of serial interface

interrupt 0 input / timer 0 gate control input

interrupt 1 input / timer 1 gate control input

counter input

byte from port 0 into the external data memory / external interrupt 2 input

external data memory

CTRAP 6 I CCU Trap Input

With CTRAP = low the compare outputs of the CAPCOM unit are switched to the logic level as defined in the COINI register (if they are enabled by the bits in SFR TRCON). CTRAP is an input pin with an internal pullup resistor. For power saving reasons, the signal source which drives the CTRAP input should be at high or floating level during power-down mode.

*) I = Input

O = Output

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Table 1 Pin Definitions and Functions (cont’d)

C504

Symbol Pin Number

(P-MQFP-44)

I/O *)

Function

XTAL2 14 – XTAL2

Output of the inverting oscillator amplifier.

XTAL1 15 – XTAL1

Input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise/fall times specified in the AC characteristics must be observed.

P2.0-P2.7 18-25 I/O Port 2

is a bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current ( of the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register.

, in the DC characteris-tics) because

PSEN 26 O The Program Store Enable

output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periodes except during external data memory accesses. Remains high during internal program execution.

ALE 27 O The Address Latch Enable

output is used for latching the low-byte of the address into external memory during normal operation. It is activated every six oscillator periodes except during an external data memory access. When instructions are executed from internal ROM (

EA=1) the ALE generation can be disabled

by bit EALE in SFR SYSCON.

*) I = Input

O = Output

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Table 1 Pin Definitions and Functions (cont’d)

C504

Symbol Pin Number

(P-MQFP-44)

I/O *)

Function

COUT3 28 O 10-Bit compare channel output

This pin is used for the output signal of the 10-bit compare timer 2 unit. COUT3 can be disabled and set to a high or low state.

EA 29 I External Access Enable

When held at high level, instructions are fetched from the internal ROM (C504-2R only) when the PC is less than 4000H.When held at low level, the C504 fetches all instructions from external program memory. For the C504-L this pin must be tied low.

P0.0-P0.7 37-30 I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float, and in that state can be used as high-impendance inputs.Port 0 is also the multiplexed low-order address and data bus during accesses to external program or data memory. In this application it uses strong internal pullup resistors when issuing 1 s. Port 0 also outputs the code bytes during program verification in the C504-2R. External pullup resistors are required during program (ROM) verification.

AREF

AGND

*) I = Input

O = Output

38 – Reference voltage for the A/D converter. 39 – Reference ground for the A/D converter. 16 – Ground (0V) 17 – Power Supply (+5V)

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C504

Functional Description

The C504 basic architecture is fully compatible to the standard 8051 microcontroller family. While maintaining all architectural and operational characteristics of the SAB 80C52 / C501, the C504 incorporates some enhancements such as on-chip XRAM, A/D converter, fail save mechanisms, and a versatile capture/compare unit.

Figure 3 shows a block diagram of the C504.

Figure 3 Block Diagram of the C504

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C504

CPU

The C504 is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15 % threebyte instructions. With a 12 MHz crystal, 58 % of the instructions are executed in 1.0µs (24 MHz: 500 ns, 40 MHz : 300 ns).

Special Function Register PSW (Address D0H) Reset Value : 00

Bit No. MSB LSB

Bit Function

CY Carry Flag

AC Auxiliary Carry Flag

F0 General Purpose Flag RS1

RS0

CY AC

Used by arithmetic instruction.

Used by instructions which execute BCD operations.

RS1 RS0 Function

RS1 RS0 OV F1 PD0

PSW

0 0 Bank 0 selected, data address 00H-07 0 1 Bank 1 selected, data address 08H-0F 1 0 Bank 2 selected, data address 10H-17 1 1 Bank 3 selected, data address 18H-1F

OV Overflow Flag

Used by arithmetic instruction. F1 General Purpose Flag P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

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H H H H

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Memory Organization

The C504 CPU manipulates operands in the following four address spaces:

– up to 64 Kbyte of external program memory – up to 64 Kbyte of external data memory – 256 bytes of internal data memory – 256 bytes of internal XRAM data memory – a 128 byte special function register area

Figure 4 illustrates the memory address spaces of the C504.

C504

Figure 4 C504 Memory Map

The XRAM in the C504 is a memory area that is logically located at the upper end of the external memory space, but is integrated on the chip. Because the XRAM is used in the same way as external data memory the same instruction types (MOVX instructions) must be used for accessing the XRAM. The XRAM can be enabled and disabled by the XMAP bit in the SYSCON register.

ROM Protection

The C504-2R ROM version allows to protect the content of the internal ROM against read out by non authorized people. The type of ROM protection (protected or unprotected) is fixed with the ROM mask. Therefore, the customer of a C504-2R ROM version has to define whether ROM protection has to be selected or not.

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C504

Special Function Registers

All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 63 special function register (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. The SFRs of the C504 are listed in table 2 and table 3. In table 2 they are organized in groups which refer to the functional blocks of the C504. Table 3 illustrates the contents of the SFRs in numeric order of their addresses.

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C504

Table 2 Special Function Registers - Functional Blocks

Block Symbol Name Address Contents after

Reset

CPU ACC

B DPH DPL PSW SP

SYSCON

Interrupt System

IEN0 IEN1 CCIE IP0 IP1 ITCON

Ports P0

P1 P1ANA P2 P3 P3ANA

A/DConverter

ADCON0 ADCON1

ADDATH ADDATL P1ANA P3ANA

Serial Channels

PCON SBUF SCON

Timer 0/ Timer 1

TCON TH0 TH1 TL0 TL1 TMOD

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) X means that the value is undefined and the location is reserved

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer System Control Register

Interrupt Enable Register 0 Interrupt Enable Register 1

Capture/Compare Interrupt Enable Reg. Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Trigger Condition Register

Port 0 Port 1

Port 1 Analog Input Selection Register Port 2 Port 3

Port 3 Analog Input Selection Register A/D Converter Control Register 0

A/D Converter Control Register 1 A/D Converter Data Register High Byte A/D Converter Data Register Low Byte

Port 1 Analog Input Selection Register

Port 3 Analog Input Selection Register

Power Control Register Serial Channel Buffer Register Serial Channel Control Register

Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register

E0 F0

83 82

81 B1

A9 D6

B9 9A

80 90 90 A0 B0 B0

DC D9 DA 90 B0

87 99

98 88

8C 8D 8A 8B 89

H H

H H H

H H

H H H

H H H H

1) 4)

XX10XXX0 0X000000

XX000000 00

XX000000 XX000000 00101010

XXXX1111 FF

XX1111XX XX000000

01XXX000 00

00XXXXXX XXXX1111 XX1111XX

000X0000

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C504

Table 2 Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

Timer 2 T2CON

T2MOD RC2H RC2L TH2 TL2

Capture / Compare Unit

CT1CON CCPL CCPH CT1OFL CT1OFH CMSEL0 CMSEL1 COINI TRCON CCL0 CCH0 CCL1 CCH1 CCL2 CCH2 CCIR CCIE CT2CON CP2L CP2H CMP2L CMP2H BCON

Watchdog WDCON

WDTREL

Power Save Mode

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) X means that the value is undefined and the location is reserved

4) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

PCON PCON1

Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload Capture Register, High Byte Timer 2 Reload Capture Register, Low Byte Timer 2 High Byte Timer 2 Low Byte

Compare timer 1 control register Compare timer 1 period register, low byte Compare timer 1 period register, high byte Compare timer 1 offset register, low byte Compare timer 1 offset register, high byte Capture/compare mode select register 0 Capture/compare mode select register 1 Compare output initialization register Trap enable control register Capture/compare register 0, low byte Capture/compare register 0, high byte Capture/compare register 1, low byte Capture/compare register 1, high byte Capture/compare register 2, low byte Capture/compare register 2, high byte Capture/compare interrupt request flag reg.

Capture/compare interrupt enable register Compare timer 2 control register Compare timer 2 period register, low byte Compare timer 2 period register, high byte Compare timer 2 compare register, low byte Compare timer 2 compare register, high byte Block commutation control register

Watchdog Timer Control Register Watchdog Timer Reload Register

Power Control Register Power Control Register 1

C9 CB CA CD CC

E1 DE DF E6 E7 E3 E4 E2 CF C2 C3 C4 C5 C6 C7 E5 D6 C1 D2 D3 D4 D5 D7

86 87

H H

H H H H H

H H H H H H H H H H H H H H

H H H H

XXXXXXX0 00

00010000 00

XXXXXX00 00

XXXX0000 00

000X0000 0XXXXXXX

3))

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Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses

C504

Addr Register Content

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

after

H H H H

.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 WDT

.6 .5 .4 .3 .2 .1 .0

80 81 82 83 86

P0 FF

SP 07

DPL 00

DPH 00

WDTREL 00

Reset

PSEL

88 88

89 8A 8B 8C 8D 90 90

98 99 9A

A0 A8

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

PCON 000X-

TCON 00

PCON1 0XXX-

TMOD 00

TL0 00

TL1 00

TH0 00

TH1 00

P1 FF

2)3)

P1ANA XXXX-

SCON 00

SBUF XX

ITCON 0010-

P2 FF

IEN0 0X00-

IEN1 XX00-

P3 FF

0000

XXXX

H H H H H

1111

1010

0000

SMOD PDS IDLS – GF1 GF0 PDE IDLE

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 EWPD – – – – – – –

GATE C/

T M1 M0 GATE C/TM1 M0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 T2EX T2 – – – – EAN3 EAN2 EAN1 EAN0

SM0 SM1 SM2 REN TB8 RB8 TI RI .7 .6 .5 .4 .3 .2 .1 .0 IT2 IE2 I2ETF I2ETR I1ETF I1ETR I0ETF I0ETR

.7 .6 .5 .4 .3 .2 .1 .0 EA – ET2 ES ET1 EX1 ET0 EX0

– – ECT1 ECCM ECT2 ECEM EX2 EADC

RD WR T1 T0 INT1 INT0 TxD RxD

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Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d)

C504

Addr Register Content

after

B H H H H H H H

C2 C3 C4 C5 C6 C7 C8

2)3)

P3ANA XX11-

SYSCON XX10-

IP0 XX00-

IP1 XX00-

WDCON

CT2CON 0001-

CCL0 00

CCH0 00

CCL1 00

CCH1 00

CCL2 00

CCH2 00

T2CON 00

Reset

11XX

XXX0

0000

0000 XXXX-

0000

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

– – EAN7 EAN6 EAN5 EAN4 – –

– – EALE RMAP – – – XMAP

– – PT2 PS PT1 PX1 PT0 PX0

– – PCT1 PCCM PCT2 PCEM PX2 PADC

– – – – OWDS WDTS WDT SWDT

CT2P ECT2O STE2 CT2

CT2R CLK2 CLK1 CLK0

RES .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/

RL2

CA CB CC CD CF D0 D2

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

3) SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

T2MOD XXXX-

RC2L 00

RC2H 00

TL2 00

TH2 00

TRCON 00

PSW 00

CP2L 00

XXX0

H H H H H H H

– – – – – – – DCEN

.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 TRPEN TRF TREN5 TREN4 TREN3 TREN2 TREN1 TREN0 CY AC F0 RS1 RS0 OV F1 P .7 .6 .5 .4 .3 .2 .1 .0

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Table 3 Contents of the SFRs, SFRs in Numeric Order of their Addresses (cont’d)

C504

Addr Register Content

after

B H H H

D4 D5

D9 DA

DE DF E0 E1

CP2H XXXX.

CMP2L 00

CMP2H XXXX.

CCIE 00

BCON 00

ADCON0 XX00-

ADDATH 00

ADDATL 00XX-

ADCON1 01XX-

CCPL 00

CCPH 00

ACC 00

CT1CON 0001-

COINI FF

Reset

XX00

0000

XXXX

X000

0000

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

––––––.1.0

.7 .6 .5 .4 .3 .2 .1 .0 ––––––.1.0

ECTP ECTC CC2

FEN

BCMP

PWM1 PWM0 EBCE

CC2 REN

CC1 FEN

BCERR

CC1 REN

CC0 FEN

CC0 REN

BCEN BCM1 BCM0

BCEM – – IADC BSY ADM MX2 MX1 MX0

.9 .8 .7 .6 .5 .4 .3 .2 .1.0––––––

ADCL1 ADCL0 – – – MX2 MX1 MX0

.7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 CTM ETRP STE1 CT1

CT1R CLK2 CLK1 CLK0

RES

COUT3ICOUTXICOUT2ICC2I COUT1ICC1I COUT0ICC0I

E5 E6 E7 F0

1) X means that the value is undefined and the location is reserved

2) Bit-addressable special function registers

CMSEL0 00

CMSEL1 00

CCIR 00

CT1OFL 00

CT1OFH 00

B 00

H H H H

CMSEL13CMSEL12CMSEL11CMSEL10CMSEL03CMSEL02CMSEL01CMSEL

0000

CT1FP CT1FC CC2F CC2R CC1F CC1R CC0F CC0R .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0 .7 .6 .5 .4 .3 .2 .1 .0

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CMSEL23CMSEL22CMSEL21CMSEL

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Timer / Counter 0 and 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in table 4. Table 4

Timer/Counter 0 and 1 Operating Modes Mode Description TMOD Input Clock

C504

T M1 M0 internal external (max)

OSC/12 × 32

OSC/24 × 32

0 8-bit timer/counter with a

Gate C/

XX00

divide-by-32 prescaler 1 16-bit timer/counter X X 1 1 f 2 8-bit timer/counter with

XX00f

OSC/12

OSC/24

8-bit autoreload 3 Timer/counter 0 used as one

XX11f

OSC/12

OSC/24

8-bit timer/counter and one

8-bit timer

Timer 1 stops In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the

count rate is f

OSC

/12. In the “counter” function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is f

/24. External inputs INT0 and INT1 (P3.2, P3.3) can be

OSC

programmed to function as a gate to facilitate pulse width measurements. Figure 5 illustrates the input clock logic.

Figure 5 Timer/Counter 0 and 1 Input Clock Logic

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C504

Timer 2

Timer 2 is a 16-bit Timer/Counter with an up/down count feature. It can operate either as timer or as an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in table 5.

Table 5 Timer/Counter 2 Operating Modes

Mode

16-bit Autoreload

16-bit Capture

Baud Rate Generator

R×CLK

T×CLK

0 0

T2CON T2MOD

CP/

RL2

TR2 internal

DCEN

0 0

1 1

T2CON

EXEN

X X

P1.1/

T2EX

Remarks

reload upon overflow

↓

reload trigger (falling edge)

Down counting

Up counting

X↓16 bit Timer/

Counter (only up-counting) capture TH2, TL2 → RC2H, RC2L

X↓no overflow

interrupt request (TF2) extra external interrupt (“Timer 2”)

Input Clock

/12

OSC

/12

OSC

external

(P1.0/T2)

max

/24

OSC

max

/24

OSC

max

/24

OSC

off X X 0 X X X Timer 2 stops – –

Note: ↓ = falling edge

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C504

Capture/Compare Unit

The Capture / Compare Unit (CCU) of the C504 is built up by a 16-bit 3-channel capture/compare unit (CAPCOM) and a 10-bit 1-channel compare unit (COMP). In compare mode, the CAPCOM unit provides two output signals per channel, which can have inverted signal polarity and nonoverlapping pulse transitions. The COMP unit can generate a single PWM output signal and is further used to modulate the CAPCOM output signals. In capture mode, the value of the compare timer 1 is stored in the capture registers if a signal transition occurs at the pins CCx. Figure 6 shows the block diagram of the CCU.

Figure 6 Block Diagram of the CCU

Semiconductor Group 22

Page 23

C504

The compare timer 1 and 2 are free running, processor clock coupled 16-bit / 10-bit timers which have each a count rate with a maximum of its possible compare output signal waveforms are shown in figure 7.

OSC

/2 up to

/256. The compare timer operations with

OSC

Figure 7 Basic Operating Modes of the CAPCOM Unit

Compare timer 1 runs only in operating mode 1 with one output signal of selectable signal polarity at the pin COUT3.

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Page 24

C504

Serial Interface (USART)

The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in table 6. The possible baudrates can be calculated using the formulas given in table 6.

Table 6 USART Operating Modes

Mode

SCON Baudrate Description

SM0 SM1

000

/12 Serial data enters and exits through R×D.

OSC

T×D outputs the shift clock. 8-bit are transmitted/received (LSB first)

1 0 1 Timer 1/2 overflow rate 8-bit UART

10 bits are transmitted (through T×D) or received (R×D)

210

OSC

/32 or f

/64 9-bit UART

OSC

11 bits are transmitted (T×D) or received (R×D)

3 1 1 Timer 1/2 overflow rate 9-bit UART

Like mode 2 except the variable baud rate

Figure 8 Block Diagram of Baud Rate Generation for the Serial Interface

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Page 25

The possible baudrates can be calculated using the formulas given in table 7.

Table 7 Formulas for Calculating Baudrates

C504

Baud Rate

derived from

Oscillator 0

Timer 1 (16-bit timer)

(8-bit timer with

8-bit autoreload)

Timer 2 1,3

Interface Mode Baudrate

/12

OSC

SMOD

1,3 1,3

SMOD

× timer 1 overflow rate) /32

× f

OSC

/ (32 × (65536-(RC2H, RC2L))

SMOD

OSC

× f

OSC

) / (32 × 12 × (256-TH1))

) / 64

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Page 26

C504

10-Bit A/D Converter

The C504 has a high performance 10-bit A/D converter (figure 9) with 8 inputs included which uses successive approximation technique for the conversion of analog input voltages.

Figure 9 A/D Converter Block Diagram

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C504

The A/D converter uses two clock signals for operation : the conversion clock f the input clock fIN (= 1/ tIN). Both clock signals are derived from the C504 system clock f is applied at the XTAL pins. The duration of an A/D conversion is a multiple of the period of the f

ADC

(= 1/ t

ADC

OSC

) and

which

clock signal. The table in figure 10 shows the prescaler ratios and the resulting A/D conversion times which must be selected for typical system clock rates.

MCU System Clock Rate (f

OSC

)

3.5 MHz 1.75 ÷ 4 0 0 .438 48 x t 12 MHz 6 ÷ 4 0 0 1.5 48 x t 16 MHz 8 ÷ 4 0 0 2 48 x t 24 MHz 12 ÷ 8 0 1 1.5 96 x t 32 MHz 16 ÷ 8 0 1 2 96 x t 40 MHz 20 ÷ 16 1 0 1.25 192 x t

[MHz]

Prescaler f

Ratio ADCL1 ADCL0

ADC

[MHz]

A/D Conversion

Time [µs]

= 27.4

= 8

= 6

= 8

= 6

= 9.6

Figure 10 A/D Converter Clock Selection

The analog inputs are located at port 1 and port 3 (4 lines on each port). The corresponding port 1 and port 3 pins have a port structure, which allows to use it either as digital I/Os or analog inputs. The analog input function of these mixed digital/analog port lines is selected via the registers P1ANA and P3ANA.

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Page 28

C504

Interrupt System

The C504 provides 12 interrupt sources with two priority levels. Figure 11 and 12 give a general overview of the interrupt sources and illustrate the interrupt request and control flags.

Figure 11 Interrupt Request Sources (Part 1)

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C504

Figure 12 Interrupt Request Sources (Part 2)

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Page 30

Table 8 Interrupt Vector Addresses

Request Flags Interrupt Source Vector Address

C504

IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 IADC IE2 TRF, BCERR CT2P CC0F-CC2F, CC0R-CC2R CT1FP, CT1FC –

A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another lowpriority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown in table 9.

External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port interrupt Timer 2 interrupt A/D converter interrupt External interrupt 2 CAPCOM emergency interrupt Compare timer 2 interrupt Capture / compare match interrupt Compare timer 1 interrupt Power-down interrupt

0003 000B 0013 001B 0023 002B 0043 004B 0053 005B 0063 006B 007B

H H

Table 9 Interrupt Source Structure

Interrupt Source Priority

High Priority

External Interrupt 0 Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt Serial Channel Timer 2 Interrupt

A/D Converter External Interrupt 2 CCU Emergency Interrupt Compare Timer 2 Interrupt Capture / Compare Match Interrupt Compare Timer 1 Interrupt

Low Priority

High h

Low

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C504

Fail Save Mechanisms

The C504 offers enhanced fail safe mechanisms, which allow an automatic recovery from software upset or hardware failure.

– 15-bit reloadable watchdog timer – Oscillator Watchdog

Watchdog Timer

The watchdog timer in the C504 is a 15-bit timer, which is incremented by a count rate of either f 12 or f

/32. From the 15-bit watchdog timer count value only the upper 7 bits can be

CYCLE

programmed. Figure 5 shows the block diagram of the programmable watchdog timer.

SOC

Figure 13 Block Diagram of the Programmable Watchdog Timer

The watchdog timer can be started by software (bit SWDT in SFR WDCON), but it cannot be stopped during active mode of the device. If the software fails to refresh the running watchdog timer an internal reset will be initiated. The reset cause (external reset or reset caused by the watchdog) can be examined by software (status flag WDTS in WDCON is set). A refresh of the watchdog timer is done by setting bits WDT (SFR WDCON) and SWDT consecutively. This double instruction sequence has been implemented to increase system security. It must be noted, however, that the watchdog timer is halted during the idle mode and power down mode of the processor. Therefore, it is possible to use the idle mode in combination with the watchdog timer function.

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Page 32

Oscillator Watchdog

The oscillator watchdog of the C504 serves for three functions :

– Monitoring of the on-chip oscillator's function

The watchdog supervises the on-chip oscillator's frequency; if it is lower than the frequency of an auxiliary RC oscillator, the internal clock is supplied by this RC oscillator and the C504 is put into reset state; if the failure condition again disappears, the part executes a final reset phase of typ. 1 ms in order to allow the oscillator to stabilize; then the oscillator watchdog reset is released and the part starts program execution again.

– Fast internal reset after power-on

The oscillator watchdog unit provides a clock supply for the reset before the on-chip oscillator has started. The oscillator watchdog unit also works identically to the monitoring function.

– Control of external wake-up from software power-down mode

When the power-down mode is left by a low level at the INT0 pin, the oscillator watchdog unit assures that the microcontroller resumes operation (execution of the power-down wake-up interrupt) with the nominal clock rate. In the power-down mode the RC oscillator and the onchip oscillator are stopped. Both oscillators are started again when power-down mode is released. When the on-chip oscillator has a higher frequency than the RC oscillator, the microcontroller starts operation after a final delay of typ. 1 ms in order to allow the on-chip oscillator to stabilize.

C504

Figure 14 Block Diagram of the Programmable Watchdog Timer

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Page 33

Power Saving Modes

Two power down modes are available, the idle mode and power down mode.

– In the idle mode the oscillator of the C504 continues to run, but the CPU is gated off from the

clock signal. However, the interrupt system, the serial port, the A/D converter, and all timers with the exception of the watchdog timer are further provided with the clock. The CPU status is preserved in its entirety: the stack pointer, program counter, program status word, accumulator, and all other registers maintain their data during idle mode.

– In the power down mode, the RC oscillator and the on-chip oscillator which operates with the

XTAL pins is stopped. Therefore all functions of the microcontroller are stopped and only the contents of the on-chip RAM, XRAM and the SFR's are maintained. The port pins, which are controlled by their port latches, output the values that are held by their SFR's.

Table 10 gives a general overview of the power saving modes. Table 10

Power Saving Modes Overview

C504

Mode Entering

Leaving by Remarks 2-Instruction Example

Idle mode ORL PCON, #01H

ORL PCON, #20H

Ocurrence of an

interrupt from a

peripheral unit

Hardware Reset

CPU clock is stopped; CPU maintains their data; peripheral units are active (if enabled) and provided with clock

Power-Down Mode

ORL PCON, #02H ORL PCON, #40H

Hardware Reset Oscillator is stopped;

Wake-up from power

down

contents of on-chip RAM and SFR’s are maintained;

In the power down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that VCC is not reduced before the power down mode is invoked, and that V

is restored to its normal operating level, before the power down mode is terminated. The idle mode can be terminated by activating any enabled peripheral interrupt or by resetting the C504. The power down mode can be terminated using an interrupt by a short low pulse at the pin P3.2/AN4/INT0 or by resetting the C504. If a power saving mode is left through an interrupt, the microcontroller state (CPU, ports, peripherals) remains preserved. If a power saving mode is left by a reset operation, the microcontroller state is disturbed and replaced by the reset state of the C504.

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C504

Absolute Maximum Ratings

Ambient temperature under bias (TA) .............................................................. 0˚C to + 70 ˚C

Storage temperature (TST)................................................................................– 65 ˚C to + 150 ˚C

Voltage on VCC pins with respect to ground (VSS) ............................................– 0.5 V to 6.5 V

Voltage on any pin with respect to ground (VSS)..............................................– 0.5 V to VCC + 0.5 V

Input current on any pin during overload condition..........................................– 10 mA to + 10 mA

Absolute sum of all input currents during overload condition ..........................| 100 mA |

Power dissipation.............................................................................................TBD

Note:

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions ( Voltage on

pins with respect to ground (

) must not exceed the values defined by the

absolute maximum ratings.

) the

Semiconductor Group 34

Page 35

C504

DC Characteristics

= 5 V + 10%, – 15%; VSS=0V TA= 0 to 70 °C for the SAB-C504

= – 40 to 85 °C for the SAF-C504

= – 40 to 110 °C for the SAH-C504

= – 40 to 125 °C for the SAK-C504

Parameter Symbol Limit Values Unit Test Condition

min. max.

Input low voltage (except

EA,

RESET, CTRAP) Input low voltage (

EA) V

Input low voltage (RESET, CTRAP)

Input high voltage (except XTAL1, RESET and

CTRAP) Input high voltage to XTAL1 Input high voltage to RESET and

CTRAP Output low voltage (ports 1, 2, 3,

COUT3) Output low voltage (port 0, ALE,

PSEN) Output high voltage (ports 1, 2, 3) V

Output high voltage (ports 1,3 pins in push-pull mode and COUT3)

– 0.5 0.2 VCC –

V–

0.1

IL1

– 0.5 0.2 VCC –

V–

0.3

IL2

– 0.5 0.2 VCC +

V–

0.1

0.2 VCC+

+ 0.5 V –

0.9

IH1

IH2

OL1

OH1

0.7 V

0.6 V

+ 0.5 V –

– 0.45 V IOL= 1.6 mA

– 0.45 V IOL= 3.2 mA

2.4

0.9 V

– –

–VI

V IOH=–80µA,

=–10µA

= – 800 µA

Output high voltage (port 0 in external bus mode, ALE,

PSEN) Logic 0 input current (ports 1, 2, 3) I Logical 1-to-0 transition current

OH2

2.4

0.9 V –10 –50 µA VIN= 0.45 V – 65 – 650 µA VIN=2V

(ports 1, 2, 3) Input leakage current (port 0, Pin capacitance C

Overload current

EA) I

– ± 1 µA 0.45 < VIN< V –10pFf

– ± 5mA

Semiconductor Group 35

– –

V IOH= – 800 µA2),

=–80µA

= 1 MHz,

=25°C

7) 8)

Page 36

C504

Parameter Symbol Limit Values Unit Test Condition

typ.

Power supply current:

Active mode, 12 MHz Idle mode, 12 MHz

Active mode, 24 MHz Idle mode, 24 MHz

Active mode, 40 MHz Idle mode, 40 MHz

Power-down mode

1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE

and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed 0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input.

16 8 25 13 38 17 1

max.

TBD TBD TBD TBD TBD TBD 50

mA mA mA mA mA mA µA

=5V,

=2…5.5 V

2) Capacitive loading on ports 0 and 2 may cause the

0.9

specification when the address lines are stabilizing.

on ALE and PSEN to momentarily fall below the

3) IPD (power-down mode) is measured under following conditions:

EA = Port0 =

; RESET = VSS; XTAL2 = N.C.; XTAL1 = VSS;V

= VSS; all other pins are disconnected.

AGND

4) ICC (active mode) is measured with:

, t

XTAL1 driven with

CLCH

EA = Port0 = Port1 = RESET =

= 5 ns , VIL= VSS+ 0.5 V, VIH= VCC– 0.5 V; XTAL2 = N.C.;

CHCL

; all other pins are disconnected. ICC would be slightly higher if a crystal

oscillator is used (appr. 1 mA).

(idle mode) is measured with all output pins disconnected and with all peripherals disabled;

XTAL1 driven with RESET = EA =

6) I

at other frequencies is given by:

CC max

, t

CLCH

; Port0 = VCC; all other pins are disconnected.

= 5 ns, VIL= VSS+ 0.5 V, VIH= VCC– 0.5 V; XTAL2 = N.C.;

CHCL

active mode: TBD idle mode: TBD

where

is the oscillator frequency in MHz. ICC values are given in mA and measured at VCC=5V.

osc

7) Overload conditions occur if the standard operating conditions are exceeded, i.e. the voltage on any pin

exceeds the specified range (i.e.

> VCC+ 0.5 V or VOV< V

– 0.5 V). The supply voltage V

and V

must remain within the specified limits. The absolute sum of input currents on all port pins may not exceed 50 mA.

8) Not 100 % tested, guaranteed by design characterization.

9) The typical

values are periodically measured at TA= +25 ˚C but not 100% tested.

Semiconductor Group 36

Page 37

A/D Converter Characteristics

= 5 V + 10%, – 15%; VSS=0V TA= 0 to 70 °C for the SAB-C504

4V ≤ V

– 0.1 V ≤ V

AREF

≤ V

+ 0.1 V; TA= – 40 to 85 °C for the SAF-C504

≤ V

AGND

+ 0.2 V; TA= – 40 to 110 °C for the SAH-C504

= – 40 to 125 °C for the SAK-C504

Parameter Symbol Limit Values Unit Test Condition

min. max.

Analog input voltage Sample time t

Conversion cycle time t

Total unadjusted error T

AIN

ADCC

AGND

– 64 x t

– 384 x t

AREF

32 x t 16 x t 8 x t

192 x t 96 x t 48 x t

V ns Prescaler ÷ 32

IN IN IN

ns Prescaler ÷ 32

IN IN IN

– ± 2 LSB VSS+ 0.5V ≤ VIN≤ VCC– 0.5V

Prescaler ÷ 16 Prescaler ÷ 8 Prescaler ÷ 4

– ± 4 LSB VSS < VIN < VSS+ 0.5V

VCC– 0.5V < VIN < V

Internal resistance of reference voltage source

Internal resistance of analog source

ADC input capacitance C

AREF

ASRC

AIN

– t

ADC

/ 250

kΩ

ADC

– 0.25

– tS / 500

kΩ

in [ns]

– 0.25

–50pF

in [ns]

5) 6)

2) 6)

C504

Notes see next page.

Clock calculation table : Clock Prescaler

ADCL1, 0 t

ADC

Ratio

÷ 32 1 1 32 x t ÷ 16 1 0 16 x t ÷ 8 0 1 8 x t ÷ 4 0 0 4 x t

Further timing conditions : t

min = 500 ns

ADC

tIN = 2 / f

IN IN

OSC

IN IN

64 x t 32 x t 16 x t 8 x t

= 2 t

CLCL

Semiconductor Group 37

IN IN IN

ADCC

384 x t 192 x t 96 x t 48 x t

IN IN IN

Page 38

Notes:

1) V

may exceed V

AIN

these cases will be X000

2) During the sample time the input capacitance C

or V

AGND

AREF

or X3FFH, respectively.

up to the absolute maximum ratings. However, the conversion result in

can be charged/discharged by the external source. The

AIN

internal resistance of the analog source must allow the capacitance to reach their final voltage level within t After the end of the sample time t

, changes of the analog input voltage have no effect on the conversion

result.

C504

3) This parameter includes the sample time t calibration. Values for the conversion clock t

, the time for determining the digital result and the time for the

depend on programming and can be taken from the table on

ADC

the previous page.

4) T

is tested at V

AREF

= 5.0 V, V

= 0 V, VCC = 4.9 V. It is guaranteed by design characterization for all

AGND

other voltages within the defined voltage range. If an overload condition occurs on maximum 2 not selected analog input pins and the absolute sum of input overload currents on all analog input pins does not exceed 10 mA, an additional conversion error of 1/2 LSB is permissible.

5) During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal resistance of the reference source must allow the capacitance to reach their final voltage level within the indicated time. The maximum internal resistance results from the programmed conversion timing.

6) Not 100 % tested, but guaranteed by design characterization.

Semiconductor Group 38

Page 39

C504

AC Characteristics for C504-L / C504-2R

= 5 V + 10%, – 15%; VSS=0V TA= 0 to 70 °C for the SAB-C504

= – 40 to 85 °C for the SAF-C504

= – 40 to 110 °C for the SAH-C504

= – 40 to 125 °C for the SAK-C504

(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Program Memory Characteristics Parameter Symbol Limit Values Unit

12-MHz clock Variable Clock

min. max. min. max.

= 3.5 MHz to

CLCL

12 MHz

ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to

PSEN t PSEN pulse width t PSEN to valid instr in t Input instruction hold after Input instruction float after Address valid after

PSEN t

PSEN t PSEN t

Address to valid instr in Address float to

Interfacing the C504 to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers.

PSEN t

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

PXAV

AVIV

AZPL

127 – 2t 43 – t 30 – t – 233 – 4t 58 – t 215 – 3t – 150 – 3t

–40 – ns

CLCL

–40 – ns

CLCL

–23 – ns

CLCL

– 100 ns

CLCL

–25 – ns

CLCL

–35 – ns

CLCL

– 100 ns

CLCL

0–0–ns

–63– t

75 – t

–8 – ns

CLCL

– 302 – 5t

–20 ns

CLCL

– 115 ns

CLCL

0–0–ns

Semiconductor Group 39

Page 40

C504

AC Characteristics for C504-L / C504-2R (cont’d) External Data Memory Characteristics

Parameter Symbol Limit Values Unit

12-MHz clock Variable Clock

= 3.5 MHz to

CLCL

12 MHz

min. max. min. max.

RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after Data float after

RD ALE to valid data in Address to valid data in ALE to Address valid to

WR or RD

WR or RD WR or RD high to ALE high Data valid to Data setup before Data hold after Address float after

WR transition

RLRH

WLWH

LLAX2

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

WHLH

QVWX

QVWH

WHQX

RLAZ

400 – 6t 400 – 6t 114 – 2t – 252 – 5t

– 100 – ns

CLCL

– 100 – ns

CLCL

–53 – ns

CLCL

– 165 ns

CLCL

0–0–ns –97– 2t – 517 – 8t – 585 – 9t 200 300 3t 203 – 4t 43 123 t 33 – t 433 – 7t 33 – t

–50 3t

CLCL

– 130 – ns

CLCL

–40 t

CLCL

–50 – ns

CLCL

– 150 – ns

CLCL

–50 – ns

CLCL

–70 ns

CLCL

– 150 ns

CLCL

– 165 ns

CLCL

+50 ns

CLCL

+40 ns

CLCL

–0–0ns

External Clock Drive Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 3.5 MHz to 12 MHz

min. max.

Oscillator period High time Low time Rise time Fall time

CLCL

CHCX

CLCX

CLCH

CHCL

83.3 294 ns 20 t 20 t

CLCL

– t – t

CLCX

CHCX

ns –20ns –20ns

Semiconductor Group 40

Page 41

C504

AC Characteristics for C504-L24 / C504-2R24

= 5 V + 10 %, – 15 %; VSS=0V TA= 0 to 70 °C for the SAB-C504

= – 40 to 85 °C for the SAF-C504

(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Program Memory Characteristics Parameter Symbol Limit Values Unit

24-MHz clock Variable Clock

= 3.5 MHz to

CLCL

24 MHz

min. max. min. max.

ALE pulse width Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to

PSEN t PSEN pulse width t PSEN to valid instr in t Input instruction hold after Input instruction float after Address valid after

PSEN t

PSEN t PSEN t

Address to valid instr in Address float to

Interfacing the C504 to devices with float times up to 37 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers.

PSEN t

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

PXAV

AVIV

AZPL

43 – 2t 17 – t 17 – t –80– 4t 22 – t 95 – 3t –60– 3t

–40 – ns

CLCL

–25 – ns

CLCL

–25 – ns

CLCL

–87 ns

CLCL

–20 – ns

CLCL

–30 – ns

CLCL

–65 ns

CLCL

0–0–ns

–32– t

37 – t

–5 – ns

CLCL

– 148 – 5t

–10 ns

CLCL

–60 ns

CLCL

0–0–ns

Semiconductor Group 41

Page 42

C504

AC Characteristics for C504-L24 / C504-2R24 (cont’d) External Data Memory Characteristics

Parameter Symbol Limit Values Unit

24-MHz clock Variable Clock

= 3.5 MHz to

CLCL

24 MHz

min. max. min. max.

RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after Data float after

RD ALE to valid data in Address to valid data in ALE to Address valid to

WR or RD

WR WR or RD high to ALE high Data valid to Data setup before Data hold after Address float after

WR transition

RLRH

WLWH

LLAX2

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

WHLH

QVWX

QVWH

WHQX

RLAZ

180 – 6t 180 – 6t 56 – 2t – 118 – 5t

–70 – ns

CLCL

–70 – ns

CLCL

–27 – ns

CLCL

–90 ns

CLCL

0 0–ns –63– 2t – 200 – 8t – 220 – 9t 75 175 3t 67 – 4t 17 67 t 5–t 170 – 7t 15 – t

–50 3t

CLCL

–97 – ns

CLCL

–25 t

CLCL

–37 – ns

CLCL

– 122 – ns

CLCL

–27 – ns

CLCL

–20 ns

CLCL

– 133 ns

CLCL

– 155 ns

CLCL

+50 ns

CLCL

+25 ns

CLCL

–0–0ns

External Clock Drive Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 3.5 MHz to 24 MHz

min. max.

Oscillator period High time Low time Rise time Fall time

CLCL

CHCX

CLCX

CLCH

CHCL

41.7 294 ns 12 t 12 t

CLCL

– t – t

CLCX

CHCX

ns –12ns –12ns

Semiconductor Group 42

Page 43

C504

AC Characteristics for C504-L40 / C504-2R40

= 5 V + 10 %, – 15 %; VSS=0V TA= 0 to 70 °C for the SAB-C504

= – 40 to 85 °C for the SAF-C504

(CL for port 0, ALE and PSEN outputs = 100 pF; CL for all other outputs = 80 pF)

Program Memory Characteristics Parameter Symbol Limit Values Unit

40-MHz clock Variable Clock

= 3.5 MHz to

CLCL

40 MHz

min. max. min. max.

ALE pulse width t Address setup to ALE Address hold after ALE ALE low to valid instr in ALE to

PSEN t PSEN pulse width t PSEN to valid instr in t Input instruction hold after Input instruction float after Address valid after

PSEN t

PSEN t PSEN t

Address to valid instr in Address float to

Interfacing the C504 to devices with float times up to 25 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers.

PSEN t

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

PXAV

AVIV

AZPL

35 – 2t 10 – t 10 – t –55– 4t 10 – t 60 – 3t –25– 3t

–15 – ns

CLCL

–15 – ns

CLCL

–15 – ns

CLCL

–45 ns

CLCL

–15 – ns

CLCL

–15 – ns

CLCL

–50 ns

CLCL

0–0–ns

–20– t

20 – t

–5 – ns

CLCL

–65– 5t

–5 ns

CLCL

–60 ns

CLCL

– 5 – – 5 – ns

Semiconductor Group 43

Page 44

C504

AC Characteristics for C504-L40 / C504-2R40 (cont’d) External Data Memory Characteristics

Parameter Symbol Limit Values Unit

40-MHz clock Variable Clock

= 3.5 MHz to

CLCL

40 MHz

min. max. min. max.

RD pulse width WR pulse width Address hold after ALE RD to valid data in Data hold after Data float after

RD ALE to valid data in Address to valid data in ALE to Address valid to

WR or RD

WR WR or RD high to ALE high Data valid to Data setup before Data hold after Address float after

WR transition

RLRH

WLWH

LLAX2

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

WHLH

QVWX

QVWH

WHQX

RLAZ

120 – 6t 120 – 6t 35 – 2t –75– 5t

–30 – ns

CLCL

–30 – ns

CLCL

–15 – ns

CLCL

–50 ns

CLCL

0 0–ns –38– 2t – 150 – 8t – 150 – 9t 60 90 3t 70 – 4t 10 40 t 5–t 125 – 7t 5–t

–15 3t

CLCL

–30 – ns

CLCL

–15 t

CLCL

–20 – ns

CLCL

–50 – ns

CLCL

–20 – ns

CLCL

–12 ns

CLCL

–50 ns

CLCL

–75 ns

CLCL

+15 ns

CLCL

+15 ns

CLCL

–0–0ns

External Clock Drive Parameter Symbol Limit Values Unit

Variable Clock

Freq. = 3.5 MHz to 40 MHz

min. max.

Oscillator period High time Low time Rise time Fall time

CLCL

CHCX

CLCX

CLCH

CHCL

25 294 ns 10 t 10 t

CLCL

– t – t

CLCX

CHCX

ns –10ns –10ns

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C504

Figure 15 Program Memory Read Cycle

Figure 16 Data Memory Read Cycle

Semiconductor Group 45

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C504

Figure 17 Data Memory Write Cycle

Figure 18 External Clock Cycle

Semiconductor Group 46

Page 47

C504

ROM Verification Characteristics for C504-2R ROM Verification Mode 1

Parameter Symbol Limit Values Unit

min. max.

Address to valid data ENABLE to valid data Data float after ENABLE Oscillator frequency

AVQV

ELQV

EHQZ

CLCL

–48t –48t 048t

CLCL

ns ns ns

4 6 MHz

Figure 19 ROM Verification Mode 1

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Page 48

C504

ROM Verification Mode 2 Parameter Symbol Limit Values Unit

min. typ max.

ALE pulse width ALE period Data valid after ALE Data stable after ALE P3.5 setup to ALE low Oscillator frequency

AWD

ACY

DVA

DSA

CLCL

–2t –12t

CLCL

––4t 8 t

CLCL

– t

––ns

CLCL

–ns –ns

CLCL

–ns

4–6MHz

Figure 20 ROM Verification Mode 2

Semiconductor Group 48

Page 49

AC Inputs during testing are driven at VCC– 0.5 V for a logic ’1’ and 0.45 V for a logic ’0’. Timing measurements are made at V

for a logic ’1’ and V

IHmin

for a logic ’0’.

ILmax

Figure 21 AC Testing: Input, Output Waveforms

C504

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs.

OL/IOH

≥±20 mA

Figure 22 AC Testing : Float Waveforms

Figure 23 Recommended Oscillator Circuits for Crystal Oscillator

Semiconductor Group 49