Datasheet SAB9082 Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

SAB9082

NTSC Picture-In-Picture (PIP)
controller

Preliminary specification
File under Integrated Circuits, IC02

1999 Feb 18

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

FEATURES

• Double window PIP in interlaced mode at 8-bit
resolution

• Internal DRAM of 1 Mbit

• Three 8-bit Analog-to-Digital Converters (ADCs) (7-bit

performance) with clamp circuit for each acquisition
channel

• One PLL which generates the line-locked clocks for the
subchannel

• One PLL which generates the line-locked clocks for the
main and display channel

• Three 8-bit Digital-to-Analog Converters (DACs)

• Linear zoom in both horizontal and vertical direction for

the subchannel

• Linear zoom in horizontal direction for the main channel

• Three multi PIP modes are available.

GENERAL DESCRIPTION

The SAB9082 is an NTSC Picture-in-Picture controller
which can be used in double window applications.

It inserts one or two live video signals with reduced size
into another live video signal. The incoming video signals
are expected to be analog baseband signals.

The conversion into the digital environment is done on
chip with ADCs. Processing and storage of the video data
is done entirely in the digital domain. The conversion back
to the analog domain is done by means of DACs. Internal
clocks are generated by PLLs which lock on to the applied
horizontal and vertical syncs.

The main input channel is compressed horizontally with a
factor of 2 and directly fed to the output. After compressing
a horizontal expansion of 2 is possible for the main
channel.

The subchannel is also compressed horizontally with a
factor of 2 but stored in memory before it is fed to the
outputs.

The SAB9082 can also create three multi PIP modes, one
with three PIPs placed in a column (MP3) and two with two
columns of three PIPs (MP6, MP6S). The reduction factors
of these PIPs is horizontal 1/2 and vertical 1/3. In the first
two modes the column(s) can be placed on the left or right
side of the screen.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V
V
I

DDD

I

DDA

DDD
DDA

digital supply voltage 3.0 3.3 3.6 V
analog supply voltage 3.0 3.3 3.6 V
digital supply current tbf 65 tbf mA
analog supply current tbf 185 tbf mA

PLL

f

sys

B
t

jitter

loop

system frequency 1792×HSYNC − 28 − MHz
loop bandwidth − 4 − kHz
short term stability jitter during 64 µs −−4ns

ζ damping factor − 0.7 −

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

SAB9082 QFP100 plastic quad flat package; 100 leads (lead length 1.95 mm);

PACKAGE

SOT317-2

body 14 × 20 × 2.8 mm

1999 Feb 18 2

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1999 Feb 18 3

handbook, full pagewidth

BLOCK DIAGRAM

NTSC Picture-In-Picture (PIP) controller SAB9082

Philips Semiconductors Preliminary specification

V

bias(SA)

V

ref(T)(SA)

V

ref(B)(SA)

SHSYNC
SVSYNC

V

bias(MA)

V

ref(T)(MA)

V

ref(B)(MA)

SU
SV
SY

MU
MY
MV

V

DDA(MF)

79
81
83
84
82
80

87
72

2
98
100
97
99
1

V

SSA(MA)

V

DDA(MA)

34

V

DDA(DA)

56

CLAMP AND ADC

PLL AND CLOCK

GENERATOR

CLAMP AND ADC

V

SSA(DA)

V

714

DDD(DA)

V

SSD(DA)

V

SSD(P1)

15 16

V

DDD(RP)

V

DDD(P1)

17 20

HORIZONTAL

AND

VERTICAL

FILTER

LINE MEMORY INTERNAL DRAM

HORIZONTAL

FILTER

V

DDD(RL)

V

SSD(RL)

V

39 40

V

DDD(RM)

SSD(RM)

41 42

V

SSD(RP)

V

DDD(P2)

61 64

V

SSD(P2)

V

SSD(D)

V

DDD(D)

65 66

SAB9082

V

DDA(SA)

67 76

DAC AND BUFFER

V

V

SSA(SA)

77 78

DISPLAY

CONTROL

DDA(SF)

V

SSD(SA)

V

DDD(SA)

85 86

18, 19

48 to 51

62, 63

8
10
12

9
11
13

69
68

30

DY
DV
DU

V

bias(DA)

V

ref(T)(DA)

V

ref(B)(DA)

PKOFF
FBL

V

SSD(T1, T2)

V

SSD(T3)

V

SSD(T4 to T7)

V

SSD(T8, T9)

DHSYNC
DVSYNC

94
70

V

DDA(SP)

PLL AND CLOCK

GENERATOR

89

90 91 92 95

V

SSA(DP)

V

SSA(SP)

V

DDA(DP)

V

DDD(MA)

V

SSD(MA)

96

21 to 29, 31,
52 to 60

n.c.

2

I

C-BUS

CONTROL

74

75

SDA

POR

Fig.1 Block diagram.

TEST

CONTROL

73 88 93 44 43 45 46 47

T7

T6

SCL

TCBD TCBR

TCLKTMTCBC

32 to 37

MGL582

71

DCLK

38

TC
T5 to T0

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

PINNING

SYMBOL PIN I/O DESCRIPTION

V

ref(B)(MA)

MU 2 I analog U input for main channel
V

DDA(MF)

V

SSA(MA)

V

DDA(MA)

V

DDA(DA)

V

SSA(DA)

DY 8 O analog Y output of DAC
V

bias(DA)

DV 10 O analog V output of DAC
V

ref(T)(DA)

DU 12 O analog U output of DAC
V

ref(B)(DA)

V

DDD(DA)

V

SSD(DA)

V

SSD(P1)

V

DDD(P1)

V

SSD(T1)

V

SSD(T2)

V

DDD(RP)

n.c. 21 to 29 − not connected
V

SSD(T3)

n.c. 31 − not connected
T5 32 I/O test data input/output bit 5 (CMOS levels)
T4 33 I/O test data input/output bit 4 (CMOS levels)
T3 34 I/O test data input/output bit 3 (CMOS levels)
T2 35 I/O test data input/output bit 2 (CMOS levels)
T1 36 I/O test data input/output bit 1 (CMOS levels)
T0 37 I/O test data input/output bit 0 (CMOS levels)
TC 38 I test control input (CMOS levels)
V

DDD(RL)

V

SSD(RL)

V

SSD(RM)

V

DDD(RM)

TCLK 43 I test clock input (CMOS levels)
TM 44 I test mode input (CMOS levels)
TCBD 45 I test control block data input (CMOS levels)
TCBC 46 I test control block clock input (CMOS levels)
TCBR 47 I test control block reset input (CMOS levels)
V

SSD(T4-T7)

1 I/O analog bottom reference voltage for main channel ADCs

3 S analog supply voltage for main channel front-end buffers
4 S analog ground for main channel ADCs
5 S analog supply voltage for main channel ADCs
6 S analog supply voltage for DACs
7 S analog ground for DACs

9 I/O input/output analog bias voltage reference for DACs

11 I/O input/output analog top reference voltage for DACs

13 I/O analog bottom reference voltage for DACs
14 S digital supply voltage for DACs
15 S digital ground for DACs
16 S digital ground for periphery
17 S digital supply voltage for periphery
18 − digital ground for test
19 − digital ground for test
20 S digital supply voltage for memory periphery

30 − digital ground for test

39 S digital supply voltage for memory logic
40 S digital ground for memory logic
41 S digital ground for memory core
42 S digital supply voltage for memory core

48 to 51 − digital ground for test

1999 Feb 18 4

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

SYMBOL PIN I/O DESCRIPTION

n.c. 52 to 60 − not connected
V

SSD(RP)

V

SSD(T8,T9)

V

DDD(P2)

V

SSD(P2)

V

SSD(D)

V

DDD(D)

FBL 68 O fast blanking control signal output (CMOS levels; +5 V tolerant)
PKOFF 69 O peak off control signal output (CMOS levels; +5 V tolerant)
DVSYNC 70 I vertical sync display channel input (CMOS levels; +5 V tolerant)
DCLK 71 I test clock input (28 MHz) (CMOS levels)
SVSYNC 72 I vertical sync for subchannel input (CMOS levels; +5 V tolerant)
SCL 73 I/O input/output serial clock (I
SDA 74 I/O input/output serial data/acknowledge output (I
POR 75 I power-on reset input (CMOS levels; pull-up resistor connected to V
V

DDA(SA)

V

SSA(SA)

V

DDA(SF)

SU 79 I analog U input for subchannel
V

ref(B)(SA)

SV 81 I analog V input for subchannel
V

ref(T)(SA)

SY 83 I analog Y input for subchannel
V

bias(SA)

V

SSD(SA)

V

DDD(SA)

SHSYNC 87 I horizontal sync input for subchannel (V
T6 88 I/O test data input/output bit 7 (CMOS levels)
V

DDA(SP)

V

SSA(SP)

V

SSA(DP)

V

DDA(DP)

T7 93 I/O test data input/output bit 6 (CMOS levels)
DHSYNC 94 I horizontal sync display input for channel (V
V

DDD(MA)

V

SSD(MA)

V

bias(MA)

MY 98 I analog Y input for main channel
V

ref(T)(MA)

MV 100 I analog V input for main channel

61 S digital ground for memory periphery

62 and 63 − digital ground for test

64 S digital supply voltage for periphery
65 S digital ground for periphery
66 S digital ground for digital core
67 S digital supply voltage for digital core

2

C-bus) (CMOS levels; +5 V tolerant)

2

C-bus) (+5 V tolerant)

76 S analog supply voltage for subchannel ADCs
77 S analog ground for subchannel ADCs
78 S analog supply voltage for subchannel front-end buffers and clamps

80 I/O input/output analog bottom reference voltage for subchannel ADCs

82 I/O input/output analog top reference voltage for subchannel ADCs

84 I/O analog bias reference voltage for subchannel ADCs
85 S digital ground for subchannel ADCs
86 S digital supply voltage for subchannel ADCs

i<VSHSYNC

)

89 S analog supply voltage for subchannel PLL
90 S analog ground for subchannel PLL
91 S analog ground for display channel PLL
92 S analog supply voltage for display channel PLL

i<VDHSYNC

)
95 S digital supply voltage for main channel ADCs
96 S digital ground for main channel ADCs
97 I/O analog bias reference voltage for main channel ADCs

99 I/O analog top reference voltage for main channel ADCs

DD

)

1999 Feb 18 5

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

handbook, full pagewidth

ref(T)(MA)

V

ref(B)(MA)

V

DDA(MF)

V

SSA(MA)

V

DDA(MA)

V

DDA(DA)

V

SSA(DA)

V

bias(DA)

V

ref(T)(DA)

V

ref(B)(DA)

V

DDD(DA)

V

SSD(DA)

V

SSD(P1)

V

DDD(P1)

V

SSD(T1)

V

SSD(T2)

V

DDD(RP)

V

SSD(T3)

MU

DY

DV

DU

n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.

MV
100

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19

20
21
22
23
24
25
26
27
28
29
30

bias(MA)VSSD(MA)VDDD(MA)

V

MY

V

99989796959493929190898887868584838281

DDA(DP)VSSA(DP)VSSA(SP)VDDA(SP)

DHSYNCT7V

SAB9082

T6

SHSYNC

DDD(SA)VSSD(SA)Vbias(SA)

V

SY

ref(T)(SA)

V

SV

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

V

ref(B)(SA)
SU
V

DDA(SF)
V

SSA(SA)
V

DDA(SA)
POR

SDA
SCL
SVSYNC
DCLK
DVSYNC
PKOFF
FBL

V

DDD(D)
V

SSD(D)
V

SSD(P2)
V

DDD(P2)
V

SSD(T9)
V

SSD(T8)
V

SSD(RP)
n.c.

n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
V

SSD(T7)

31323334353637383940414243444546474849

T5T4T3T2T1

n.c.

T0

TC

DDD(RL)

V

Fig.2 Pin configuration.

1999 Feb 18 6

SSD(RL)

SSD(RM)

V

V

TCLK

DDD(RM)

V

TM

TCBD

TCBC

TCBR

50

MGL583

SSD(T4)VSSD(T5)VSSD(T6)

V

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

FUNCTIONAL DESCRIPTION
Acquisition

The internal pixel rate is 28 MHz for the Y, U and V channels. It is expected that the bandwidth of the input signals is
limited to 4.5 MHz for the Y input and 1.125 MHz for the U and V input. Inset synchronization is achieved via the
acquisition HSYNC and VSYNC pins of the main channel. The display is driven by the main channel clock. With the
acquisition fine positioning added to a system constant the starting point of the acquisition can be controlled. With a
nominal input HSYNC frequency, resulting in a nominal system frequency of 1792 × HSYNC (approximately 28 MHz)
and standard NTSC signals 1408 samples are acquired and processed by the SAB9082.

PIP modes

handbook, full pagewidth

SUB

MAIN SUB

MAIN

SUB

REPLAY

MAIN

Fig.3 PIP modes.

MGM810

1999 Feb 18 7

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

handbook, full pagewidth

S0

S0

S0

S1

S0

S2

S4

S0

S2

S4

S0

S2

S1

S2

S1

S3

S5

MAIN

MAIN

S1

S3

S5

S1

S3

S0

S1

S2

S0

S2

S4

S1

S3

S5

MAIN

S1

S2

MAIN

MAIN

S0

S2

S4

S2

S4

S3

S5

S0

S1

S2

S1

S3

S5

MGL587

S4

S5

Fig.4 Multi PIP modes.

1999 Feb 18 8

1999 Feb 18 9

I2C-bus description

The I2C-bus provides bidirectional 2-line communication between different ICs. The SDA line is the serial data line and the SCL serves as serial clock
line. Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be
initiated only when the bus is not busy. The SAB9082 has the I2C-bus addresses 2C. Valid subaddresses are 00H to 18H, registers 15H to 18H are
reserved for future extensions. I2C-bus control is according to the I2C-bus protocol: First a START sequence must be put on the I2C-bus, then the
I2C-bus address of the circuit must be sent, then a subaddress. After this sequence the data of the subaddresses must be sent. An auto increment
function gives the option to send data of the incremented subaddresses until a STOP sequence is sent. Table 1 gives an overview of the I2C-bus
addresses. The data bits which are not used should be set to zero.

2

Table 1 Overview of I

C-bus addresses

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

SUB
ADD

00H MPIPON SPIPON S1FLD SFreeze DNonint PipMode2 PipMode1 PipMode0
01H SHBlow1 SHBlow0 SHRed5 SHRed4 SHRed3 SHRed2 SHRed1 SHRed0
02H SVBlow SVRed6 SVRed5 SVRed4 SVRed3 SVRed2 SVRed1 SVRed0
03H BGVfp3 BGVfp2 BGVfp1 BGVfp0 BGHfp3 BGHfp2 BGHfp1 BGHfp0
04H SDHfp7 SDHfp6 SDHfp5 SDHfp4 SDHfp3 SDHfp2 SDHfp1 SDHfp0
05H SDVfp7 SDVfp6 SDVfp5 SDVfp4 SDVfp3 SDVfp2 SDVfp1 SDVfp0
06H SHPic7 SHPic6 SHPic5 SHPic4 SHPic3 SHPic2 SHPic1 SHPic0
07H SVPic7 SVPic6 SVPic5 SVPic4 SVPic3 SVPic2 SVPic1 SVPic0
08H MAHfp3 MAHfp2 MAHfp1 MAHfp0 SAHfp3 SAHfp2 SAHfp1 SAHfp0
09H SAVfp7 SAVfp6 SAVfp5 SAVfp4 SAVfp3 SAVfp2 SAVfp1 SAVfp0
0AH DUVPol DVSPol DFPol DHsync SUVPol SVSPol SFPol SHsync
0BH MainFidPos7 MainFidPos6 MainFidPos5 MainFidPos4 MainFidPos3 MainFidPos2 MainFidPos1 MainFidPos0
0CH SubFidPos7 SubFidPos6 SubFidPos5 SubFidPos4 SubFidPos3 SubFidPos2 SubFidPos1 SubFidPos0
0DH BGon Bon MFidPOn SFidPOn Prio AlgOff SFblkPkff1 SFblkPkff0
0EH BSel1 BSel0 SBBrt1 SBBrt0 − SBCol2 SBCol1 SBCol0
0FH −−SLSel5 SLSel4 SLSel3 SLSel2 SLSel1 SLSel0
10H I2CHold SV SDSel5 SDSel4 SDSel3 SDSel2 SDSel1 SDSel0
11H MDHfp7 MDHfp6 MDHfp5 MDHfp4 MDHfp3 MDHfp2 MDHfp1 MDHfp0
12H MDVfp7 MDVfp6 MDVfp5 MDVfp4 MDVfp3 MDVfp2 MDVfp1 MDVfp0
13H MHBlow − MHRED5 MHRED4 MHRED3 MHRED2 MHRED1 MHRED0
14H − VBwidth2 VBwidth1 VBwidth0 − HBwidth2 HBwidth1 HBwidth0
15H to

18H

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

DATA BYTES

all bits are reserved

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

MPIPON (DOUBLE WINDOW)
With MPIPON the main channel PIP is switched on

(logic 1) or off (logic 0).

SPIPON
With SPIPON the sub PIPs are switched on (logic 1) or off

(logic 0).

S1FLD
If S1FLD is set to logic 0 two fields are used for the live

PIP. When a 50/60 Hz or a 60/50 Hz mode is detected the
SAB908x automatically switches to the 1 Field mode
(1 Field resolution vertically).

If S1FLD is set to logic 1 only one field is used. This
causes joint line errors but saves memory. In normal
modes this bit should not be set.

SF

REEZE

With SFreeze set to logic 1 the current live sub PIP will be
frozen. If set to logic 0 it is unfrozen.

A

LGOFF

In double window mode precautions are taken to prevent
a joint line error. Under some conditions this feature should
be switched off. This can be realized by setting this bit to
logic 1. AlgOff should be set to logic 0.

ONINT

DN
In normal mode (this bit is logic 0) the SAB9082 calculates

whether a signal is non-interlaced or not and reacts
accordingly. With the DNonint bit set to logic 1 the display
channel is forced into the non-interlaced mode. In the
non-interlaced mode only one field is used during
processing of the PIPs.

PIP

MODE AND REPLAY

The PIP modes for the SAB9082 are shown in Table 2.

Table 2 PIP modes

BITS MODE

000 double window mode
001 replay PIP
010 multi PIP 3
011 multi PIP 6
100 reserved
111 multi PIP 6 split

SHRED AND SVRED (DOUBLE WINDOW)
SHRed and SVRed determine the reduction factor in the

double window mode.
The horizontal reduction is equal to SHRed/96 and the

vertical reduction is equal to SVRed/96. SHRed should lie
in the range from 0 to 48, if set to logic 0 the PIP is off.
SVRed should lie in the range from 0 to 96, if set to logic 0
the PIP is off.

For the horizontal reduction factor, when the reduction
factor is 48/96, 704 samples are processed. The HRed is
linear so when HRed is e.g 24/96 352 samples are
processed. For the vertical reduction factor the same holds
but then with the number of lines. For NTSC the number of
processed lines can be calculated from VRed/96 × 228
lines.

IC AND SVPIC (MULTI PIP MODES)

SHP
SHPic and SVPic control the picture size in the multi PIP

modes. The horizontal range is 256 steps of four 28 MHz
clocks. The vertical range is 256 steps of one line/field.

In double window and replay modes the picture size is
determined by the reduction factors (SHRed and SVRed)
and HBlow and VBlow.

BGH

FP AND BGVFP

These bits control the horizontal and vertical positioning of
the PIP configuration on the screen. The horizontal range
is adjustable in 16 steps of four 28 MHz clocks.
The vertical range is 16 steps of 1 line/field.
The background colour can be adjusted with bits Bsel,
SBBrt and SBCol.

SDH

FP AND SDVFP

These bytes control the horizontal and vertical positioning
of the sub PIPs on the screen. The horizontal range is
256 steps of eight 28 MHz clocks. The vertical range is
256 steps of 1 line/field.

MAH

FP, SAHFP AND SAVFP

These bytes control the horizontal and vertical inset
starting point of the acquired data. The horizontal range is
16 steps of eight 28 MHz clocks. The vertical range is
256 steps of 1 line/field.

1999 Feb 18 10

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

DUVPOL, DVSPOL, DFPOL AND DHSYNC
These bits control the PLL/deflection settings. With

DUVPol the polarity of the border UV signals can be
inverted in case the deflection circuit behind the SAB9082
expects inverted signals. With DVSPol set to logic 0 the
SAB9082 triggers on positive edges of the DVSYNC. If it
is set to logic 1 it triggers on negative edges. DHSYNC
determines the timing of the DHSYNC pulse. If it is set to
logic 0 a burstkey is expected and if it is set to logic 1 a
H-sync is expected. DFPol can invert the field ID of the
incoming fields.

SUVP

OL, SVSPOL, SFPOL AND SHSYNC

These bits control the PLL/Decoder settings. With SUVPol
the polarity of the video UV signals can be inverted in case
the decoder circuit before the SAB9082 gives inverted
signals out.

With SVSPol set to logic 0 the SAB9082 triggers on
positive edges of the SVSYNC. If it is set to logic 1 it
triggers on the negative edges. SHSYNC determines the
timing of the SHSYNC pulse. If it is set to logic 0 a burstkey
is expected and if it is set to logic 1 a H-sync is expected.
SFPol can invert the field ID of the incoming fields.

M

AIN, SUB FID POS ON (MFIDPON AND SFIDPON)

MFidPon (main) and SFidPon (sub) enable the field
identification position fine tuning. The default value is off
(logic 0), no fine positioning; when on (logic 1) the field
identification position is determined by the value of M/S
FIDPos.

BGO

N

BGOn determines whether a the background is visible.
The background has a size of 720 pixels and 240 lines for
NTSC. The background colour can be adjusted with bits
Bsel, SBBrt and SBCol.

B

ON, SBBRT , SBCOL AND BSEL

Table 3 Bsel modes

BSEL BORDER COLOUR SET

00 main
01 sub
10 background
11 sub-border select

FP AND MDVFP

MDH
These bytes control the horizontal and vertical positioning

of the main PIP on the screen. The horizontal range is
256 steps size of eight 28 MHz clocks. The vertical range
is 256 steps of 1 line/field.

MHR

ED

MHRed can set the horizontal reduction factor, equal to
MHRed/96, in a range from 0 to 48. If it is set to logic 0 the
PIP is off, if it is set to 48 (the maximum value of MHRed)
the horizontal reduction factor is 0.5.

LOW AND SVBLOW (REPLAY MODE)

SHB
SHBlow and SVBlow are used in the replay mode. These

bits can expand a pixel on the display side by a factor two
(01) or four (11) in the horizontal direction (SHBlow) and a
factor of two (1) in the vertical direction (SVBlow). Zero
values indicate no expansion.

MHB

LOW

MHBlow can expand the main picture by a factor of two in
the horizontal direction.

SLS

EL (REPLAY MODE)

In the replay PIP mode SLSel determines at which
memory location the PIP data is written, the range
depends on the memory usage for each PIP.
The maximum number of PIPs that can be stored in NTSC
mode is 42.

Bon can switch the sub-borders on (logic 1) or off (logic 0).
SBBrt and SBCol set the brightness and colour type of the
selected border. The brightness is set in 4 levels of 30%,
50%, 70% and 100% IRE. The colour type is one of black
(grey), blue, red, magenta, green, cyan, yellow or white
(gray). Bsel selects which colour is set, background or
border.

1999 Feb 18 11

SLS

EL (MULTI PIP MODES)

SLSel selects which of the PIPs in a multi PIP mode is live.
In MP3 modes SLSel must be in the range from 0 to 2. In
all MP6 modes SLSel must be in the range from 0 to 5.

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

SDSEL (REPLAY MODE)
SDSel selects which PIP is read from memory. Valid

numbers are dependent on the maximum value of SLSel.

SFB

LKPKOFF 1:0

SFBlkPkoff shifts the signals Fblk and Pkoff with respect to
the YUV output, by half pixels.

Table 4 Shifts of FBLK and PKOff

SFBLKPKOFF SHIFT OF FBLK AND PKOff

00 +0.5 pixel
01 no shift
10 −0.5 pixel
11 −1 pixel

I2CHOLD
I2CHOLD controls the updating of the I2C-bus controlled

function towards the PIP. If set to logic 1 some register
updates are on hold until the bit is set to logic 0. At the next
main Vsync all settings are passed to the PIP functions.

The registers which are on hold when the I2CHold bit is set
to logic 1 are:

1. MPIPON and SPIPON.

2. SHBlow and SVBlow.

3. SHRed and SVRed.

4. BGHfp and BGVfp.

5. BGOn and Bon.

6. SBBrt and SBCol.

7. MDHfp and MDVfp.

8. HBWidth and VBWidth.

9. DNonint.

10. BSel

11. SHPic and SVPic

12. SLSel.

SV
SV controls the internal horizontal offset of the

background. When set to logic 0 the offset is 0.86 µs,
when set to logic 1 the offset is 4.56 µs.

NOTES

1. When the SAB9082 is set in the 1 field mode, joint line
errors can occur. The SAB9082 is set in the 1 field
mode by setting the 1Fld bit to logic 1.

2. When the SAB9082 is set in the non-interlace mode,
joint line errors can occur. The SAB9082 is set in the
non-interlace mode by setting the NonInt bit to logic 1.

3. When the input signals for the main and/or subchannel
are non-interlaced signals, joint line errors can occur.
When non-interlaced signals are input the SAB9082
switches automatically to the non-interlaced mode.

4. When the prevent joint line error algorithm is switched
off (AlgOff is set to logic 1) joint line errors can still
occur in the 2 field mode.

Acquisition channel ADCs and clamping

The analog input signals are converted to digital signals by
means of three ADCs. The resolution of the ADCs is 8-bit
(DNL is 7-bit and INL is 6-bit) and the sampling is
performed at the system frequency of 28 MHz for the
Y input. A bias voltage (V

) is used for decoupling the

bias

AC components on internal references.
The inputs should be AC-coupled and an internal clamp

circuit, using external clamp capacitors, will clamp the
input to V
(V

ref(T)(DA)

ref(B)(DA)

for the luminance channels and to

− V

ref(B)(DA)

)/2 + LSB/2 for the chrominance
channels. The clamping starts at the active edge of the
burst key. Internal video buffers amplify the standard input
signals Y, U and V to the correct ADC levels.

PLL

The PLL generates an internal system clock of
1792 × HSYNC, from the HSYNC, which is approximately
28 MHz.

DACs and video buffers

The 28 MHz digital video signals are fed to the 8-bit DACs
which produce the required analog video signals.
The video buffers amplify these signals prior to being fed
to the output to drive another device.

HBW

IDTH AND VBWIDTH

These bits control the horizontal and vertical border size in
steps of 2 pixels and 1 line. The default horizontal border
size is 4 pixels and the vertical border size is 2 lines.
Default means after power-up and no I2C-bus data sent to
the Picture-in-Picture controller.

In MP6 mode the minimum value of HBWidth is two.

1999 Feb 18 12

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

T

stg

T

amb

V

esd

R

thj-a

P

max

QUALITY SPECIFICATION

supply voltage range −0.5 tbf V
storage temperature −25 +150 °C
operating ambient temperature 0 70 °C
electrostatic discharge handling − 3kV
thermal resistance − 45 K/W
maximum power dissipation − 1.0 W

In accordance with

“SNW-FQ-611, Part E”

, dated 14 december 1992.

1999 Feb 18 13

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

ESD LEVELS
Table 5 ESD performance

PIN SYMBOL HUMAN BODY MODEL (V) MACHINE MODEL (V)

20 V

DD(RP)

32 T5 400 > 150
33 T4 400 < 150 (estimated 50)
34 T3 400 < 150 (estimated 50)
35 T2 400 > 150
36 T1 400 > 150
37 T0 400 > 150
38 TC > 500 > 150
39 V
40 V
41 V
42 V

DDD(RL)
SSD(RL)
SSD(RM)

DDD(RM)

43 TCLK > 500 <150 (estimated50)
44 TM > 500 > 150
45 TCBD >500 > 150
46 TCBC >500 > 150
47 TCBR >500 < 150 (estimated 50)
61 V

SSD(RP)

68 FBL 1000 standard specification
69 PKOFF 1000 standard specification
70 DVSYNC 1000 standard specification
72 SVSYNC 1000 standard specification
73 SCL 1000 standard specification
81 SV > 3000 150
93 T7 > 3000 > 325

rest in range 1 to 17 all other pins > 3000 > 325

rest in range 64 to 100 all other pins > 3000 > 325

> 500 > 150

> 500 > 150
> 500 > 150
> 500 > 150
> 500 > 150

> 500 > 150

1999 Feb 18 14

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

ANALOG CHARACTERISTICS

= 3.3 V; T

V

DDA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DD

V

SS

∆V

DD(max)

∆V

SS(max)

I

DDD(q)

I

DDA(DP)

I

DDA(SP

I

DDA(MA)

I

DDA(SA)

I

DDA(DA)

I

DDA(tot)

I

DDD(tot)

Analog-to-digital converter and clamping

V

ref(T)

V

ref(B)

V

iY(p-p)

V

i(V)(p-p)

V

i(U)(p-p)

I

i

C

i

f

s

RES resolution 8 8 8 bit
DNL differential non-linearity −1.1 − +1.1 LSB
INL integral non-linearity −2.0 − +2.0 LSB

α

cs

PSRR power supply rejection ratio − 48 − dB
V

clamp(Y)

V

clamp(U,V)

=25°C; unless otherwise specified.

amb

positive supply voltage 3.0 3.3 3.6 V
ground voltage − 0 − V
maximum DC difference

− 0 100 mV

between supply voltages
maximum DC difference

− 0 100 mV

between ground voltages
quiescent current of digital

note 1 − 050µA

supply voltages
display PLL supply current − 1 − mA
sub PLL supply current − 1 − mA
main ADCs supply current note 2 − 65 − mA
sub ADCs supply current note 2 − 65 − mA
DACs supply current − tbf − mA
total analog supply current note 2 − tbf − mA
total digital supply current − tbf − mA

top reference voltage note 3 tbf 2.90 tbf V
bottom reference voltage note 3 tbf 1.10 tbf V
Y input signal amplitude

note 4 tbf 1.00 tbf V

(peak-to-peak value)
V input signal amplitude

note 4 tbf 1.05 tbf V

(peak-to-peak value)
U input signal amplitude

note 4 tbf 1.33 tbf V

(peak-to-peak value)
input current clamping off − 0.1 −µA

clamping on − tbf −µA
input capacitance − 5 − pF
sample frequency note 5 − 1792 × HSYNC − kHz

channel separation − 48 − dB

Y clamping voltage level note 6 − 1.28 − V
U/V clamping voltage level note 6 − 2.00 − V

1999 Feb 18 15

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital-to-analog converter and output stage

V

ref(T)

V

ref(B)

R

L

C

L

f

s

RES resolution 8 8 8 bit
DNL differential non-linearity −1.0 − +1.0 LSB
INL integral non-linearity −1.0 − +1.0 LSB

α

cs

PSRR power supply rejection ratio − 48 − dB

Display PLL and clock generation

f

i(PLL)

Sub PLL and clock generation

f

i(subPLL)

Notes

1. Digital clocks are silent, POR and TM are connected to V

2. This value is measured with an external bias resistor of 39 kΩ resulting in a bias current of 50 µA.

3. The V
V

ref(T)

ref(T)

4. The input signal are amplified to meet an internal peak-to-peak voltage level of 0.8 × [V

5. The internal system frequency is 1792 times the HSYNC input frequency for the subchannel.

6. The clamp level is not necessarily equal to the V

7. The UV-channels are clamped to:

top reference voltage note 2 tbf 1.19 tbf V
bottom reference voltage tbf 0.19 tbf V
load resistance 1 − 1000 kΩ
load capacitance 0 − 5pF
sample frequency 1FH, note 5 − 1792 × HSYNC − kHz

channel separation − 48 − dB

input frequency note 1 14 15.75 (NTSC) 17 kHz

input frequency note 1 14 15.75 (NTSC) 17 kHz

.

DDA

and V

V

DDA

are made by a resistor division of the VDD. They can be calculated with the formulas:

ref(B)

2.90

------------------------­V

DDA(nom)

and

V×= V

ref(B)

V

---------------------------------------------------------------

V

DDA

++()

ref(B)Vref(T)VLSB

2

1.10

------------------------­V

DDA(nom)

of the ADCs.

ref(B)

V×=

− V

ref(T)

ref(B)

].

1999 Feb 18 16

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

DIGITAL CHARACTERISTICS

= 3.0 to 3.6 V; T

V

DDD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DC characteristics

V

IH

V

IL

V

hys

V

OH

V

OL

|I

| input leakage current VI=0 −− 1 µA

LI

|I

| 3-state output leakage

OZ

HIGH-level input voltage default 0.8V

LOW-level input voltage default −0.5 − 0.2V

hysteresis voltage 0.8 −−V
HIGH-level output voltage IOL= −X mA;

LOW-level output voltage IOL=X mA;

current

I

lu(I/O)

R

pu

I/O latch-up current V < 0V; V > V
internal pull-up resistor 16 33 78 kΩ

AC characteristics

f

sys

t

r

t

f

system frequency note 2 − 1792 × HSYNC − kHz
rise time − 625ns
fall time − 625ns

= 0 to 70 °C; unless otherwise specified.

amb

pin 74 0.8V
5 V tolerant pins 68,

69, 70, 72, 73

pins tbf −0.5 − 0.2V

V

= 3.0 V; note 1

DDD

V

= 3.0 V; note 1

DDD

I

= 2 mA;

OL

V

= 3.0 V

DDD

V

I=VDDD

VO= 0 V or
VO=V

DDD

DDD

0.8V

0.85V

− V

DDD

− tbf V

DDD

− tbf V

DDD

−−V

DDD

DDD

DDD
DDD

+ 0.5 V

V
V

−− 0.4 V

−− 0.4 V

−− 1 µA

−− 1 µA

200 −−mA

Note

1. X is the source/sink current under worst case conditions. X is reflected in the name of the I/O cell according to the

drive capability. Minimum value of X is 1 mA.

2. The internal system frequency is 1792 times the HSYNC input frequency for the subchannel.

1999 Feb 18 17

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

TEST AND APPLICATION INFORMATION

The application diagram in a standard configuration is shown in Figure 5. The input signals main CVBS and sub CVBS
of different video sources are processed by the SAB9082 and inserted by the YUV/RGB switch.

handbook, full pagewidth

sub CVBS

main CVBS

SUB

DECODER

TDA8310

MAIN

DECODER

TDA8310

HS/VS

YUV

HS/VS

YUV

FBL

SAB9082

YUV

PIP

CONTROLLER

YUV

RGB

TDA4780

Fig.5 Application diagram.

to

HS/VS

YUV

RGB

HS/VS

YUV/RGB

PROCESSING

AND

DEFLECTION

CIRCUIT

RGB

MGL581

1999 Feb 18 18

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

PACKAGE OUTLINE

QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

c

y

X

E

e

w M

p

A

A

H

E

E

2

A

A

1

80 51

81

pin 1 index

100

1

50

Z

b

31

30

detail X

L

p

L

SOT317-2

(A )

3

θ

w M

b

e

p

Z

D

D

H

D

0 5 10 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

A

max.

3.20

0.25

0.05

2.90

2.65

0.25

UNIT A1A2A3b

cE

p

0.40

0.25

0.25

0.14

(1)

(1) (1)(1)

D

20.1

19.9

eH

14.1

13.9

0.65

24.2

23.6

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

OUTLINE
VERSION

IEC JEDEC EIAJ

REFERENCES

SOT317-2

1999 Feb 18 19

v M

A

B

v M

B

E

18.2

17.6

LL

p

1.0

0.6

0.15 0.10.21.95

H

D

EUROPEAN

PROJECTION

Z

D

0.8

0.4

Zywv θ

E

o

1.0

7

o

0.6

0

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

SOLDERING
Introduction to soldering surface mount packages

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“Data Handbook IC26; Integrated Circuit Packages”

our
(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Wave soldering

Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Feb 18 20

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, SQFP not suitable suitable

SOLDERING METHOD

HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

1999 Feb 18 21

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

2

PURCHASE OF PHILIPS I

C COMPONENTS

2

Purchase of Philips I
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

C components conveys a license under the Philips’ I2C patent to use the

1999 Feb 18 22

Philips Semiconductors Preliminary specification

NTSC Picture-In-Picture (PIP) controller SAB9082

NOTES

1999 Feb 18 23

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Tel. [phone], Fax. [phone]
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Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
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Middle East: see Italy
Netherlands: Postbus 90050, 5600PB EINDHOVEN, Bldg. VB,

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Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

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Metro MANILA, Tel. [phone], Fax. [phone]

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United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

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For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1999 SCA62
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545004/25/01/pp24 Date of release: 1999 Feb 18 Document order number: 9397 750 03295